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Stefano Babicf8f8acd2010-07-06 19:32:09 +02001/*
2 * (C) Copyright 2010
3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
4 *
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <asm/io.h>
28#include <asm/arch/imx-regs.h>
Jason Liuff9f4752010-10-18 11:09:26 +080029#include <asm/arch/mx5x_pins.h>
Stefano Babicf8f8acd2010-07-06 19:32:09 +020030#include <asm/arch/crm_regs.h>
31#include <asm/arch/iomux.h>
32#include <mxc_gpio.h>
33#include <asm/arch/sys_proto.h>
34#include <asm/errno.h>
35#include <i2c.h>
36#include <mmc.h>
37#include <fsl_esdhc.h>
38#include <fsl_pmic.h>
39#include <mc13892.h>
Stefano Babica0152c42010-10-21 10:34:39 +020040#include <linux/fb.h>
Stefano Babicf8f8acd2010-07-06 19:32:09 +020041
42DECLARE_GLOBAL_DATA_PTR;
43
44static u32 system_rev;
45
Stefano Babica0152c42010-10-21 10:34:39 +020046extern int mx51_fb_init(struct fb_videomode *mode);
47
Stefano Babica0152c42010-10-21 10:34:39 +020048static struct fb_videomode nec_nl6448bc26_09c = {
49 "NEC_NL6448BC26-09C",
50 60, /* Refresh */
51 640, /* xres */
52 480, /* yres */
53 37650, /* pixclock = 26.56Mhz */
54 48, /* left margin */
55 16, /* right margin */
56 31, /* upper margin */
57 12, /* lower margin */
58 96, /* hsync-len */
59 2, /* vsync-len */
60 0, /* sync */
61 FB_VMODE_NONINTERLACED, /* vmode */
62 0, /* flag */
63};
64
Fabio Estevamc08f68c2011-05-10 07:50:46 +000065#ifdef CONFIG_HW_WATCHDOG
66#include <watchdog.h>
Stefano Babicf8f8acd2010-07-06 19:32:09 +020067void hw_watchdog_reset(void)
68{
69 int val;
70
71 /* toggle watchdog trigger pin */
72 val = mxc_gpio_get(66);
73 val = val ? 0 : 1;
74 mxc_gpio_set(66, val);
75}
76#endif
77
78static void init_drive_strength(void)
79{
80 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
81 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
82 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
83 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
84 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
85 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
86 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
87 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
88 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
89 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
90 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
91 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
92 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
93 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
94 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
95 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
96 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
97 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
98 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
99 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
100 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
101 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
102 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
103 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
104 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
105 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
106 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
107
108 /* Setting pad options */
109 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
110 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
111 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
112 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
113 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
114 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
115 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
116 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
117 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
118 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
119 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
120 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
121 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
122 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
123 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
124 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
125 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
126 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
127 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
128 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
129 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
130 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
131 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
132 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
133 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
134 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
135 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
136 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
137 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
138 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
139 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
140 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
141 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
142 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
143 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
144 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
145 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
146 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
147 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
148 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
149 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
150 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
151}
152
153u32 get_board_rev(void)
154{
155 system_rev = get_cpu_rev();
156
157 return system_rev;
158}
159
160int dram_init(void)
161{
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200162 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
163 PHYS_SDRAM_1_SIZE);
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200164
165 return 0;
166}
167
168static void setup_weim(void)
169{
170 struct weim *pweim = (struct weim *)WEIM_BASE_ADDR;
171
172 pweim->csgcr1 = 0x004100b9;
173 pweim->csgcr2 = 0x00000001;
174 pweim->csrcr1 = 0x0a018000;
175 pweim->csrcr2 = 0;
176 pweim->cswcr1 = 0x0704a240;
177}
178
179static void setup_uart(void)
180{
181 unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
182 PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST;
183 /* console RX on Pin EIM_D25 */
184 mxc_request_iomux(MX51_PIN_EIM_D25, IOMUX_CONFIG_ALT3);
185 mxc_iomux_set_pad(MX51_PIN_EIM_D25, pad);
186 /* console TX on Pin EIM_D26 */
187 mxc_request_iomux(MX51_PIN_EIM_D26, IOMUX_CONFIG_ALT3);
188 mxc_iomux_set_pad(MX51_PIN_EIM_D26, pad);
189}
190
191#ifdef CONFIG_MXC_SPI
192void spi_io_init(void)
193{
194 /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
195 mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
196 mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
197 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
198
199 /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
200 mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
201 mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
202 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
203
204 /* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */
205 mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
206 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0,
207 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
208 PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
209
210 /*
211 * SS1 will be used as GPIO because of uninterrupted
212 * long SPI transmissions (GPIO4_25)
213 */
214 mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
215 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1,
216 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
217 PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
218
219 /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
220 mxc_request_iomux(MX51_PIN_DI1_PIN11, IOMUX_CONFIG_ALT7);
221 mxc_iomux_set_pad(MX51_PIN_DI1_PIN11,
222 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
223 PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
224
225 /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
226 mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
227 mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
228 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
229}
230
231static void reset_peripherals(int reset)
232{
233 if (reset) {
234
235 /* reset_n is on NANDF_D15 */
236 mxc_gpio_set(89, 0);
237 mxc_gpio_direction(89, MXC_GPIO_DIRECTION_OUT);
238
239#ifdef CONFIG_VISION2_HW_1_0
240 /*
241 * set FEC Configuration lines
242 * set levels of FEC config lines
243 */
244 mxc_gpio_set(75, 0);
245 mxc_gpio_set(74, 1);
246 mxc_gpio_set(95, 1);
247 mxc_gpio_direction(75, MXC_GPIO_DIRECTION_OUT);
248 mxc_gpio_direction(74, MXC_GPIO_DIRECTION_OUT);
249 mxc_gpio_direction(95, MXC_GPIO_DIRECTION_OUT);
250
251 /* set direction of FEC config lines */
252 mxc_gpio_set(59, 0);
253 mxc_gpio_set(60, 0);
254 mxc_gpio_set(61, 0);
255 mxc_gpio_set(55, 1);
256 mxc_gpio_direction(59, MXC_GPIO_DIRECTION_OUT);
257 mxc_gpio_direction(60, MXC_GPIO_DIRECTION_OUT);
258 mxc_gpio_direction(61, MXC_GPIO_DIRECTION_OUT);
259 mxc_gpio_direction(55, MXC_GPIO_DIRECTION_OUT);
260
261 /* FEC_RXD1 - sel GPIO (2-23) for configuration -> 1 */
262 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
263 /* FEC_RXD2 - sel GPIO (2-27) for configuration -> 0 */
264 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT1);
265 /* FEC_RXD3 - sel GPIO (2-28) for configuration -> 0 */
266 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT1);
267 /* FEC_RXER - sel GPIO (2-29) for configuration -> 0 */
268 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT1);
269 /* FEC_COL - sel GPIO (3-10) for configuration -> 1 */
270 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT3);
271 /* FEC_RCLK - sel GPIO (3-11) for configuration -> 0 */
272 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT3);
273 /* FEC_RXD0 - sel GPIO (3-31) for configuration -> 1 */
274 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT3);
275#endif
276
277 /*
278 * activate reset_n pin
279 * Select mux mode: ALT3 mux port: NAND D15
280 */
281 mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT3);
282 mxc_iomux_set_pad(MX51_PIN_NANDF_D15,
283 PAD_CTL_DRV_VOT_HIGH | PAD_CTL_DRV_MAX);
284 } else {
285 /* set FEC Control lines */
286 mxc_gpio_direction(89, MXC_GPIO_DIRECTION_IN);
287 udelay(500);
288
289#ifdef CONFIG_VISION2_HW_1_0
290 /* FEC RDATA[3] */
291 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
292 mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
293
294 /* FEC RDATA[2] */
295 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
296 mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
297
298 /* FEC RDATA[1] */
299 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
300 mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
301
302 /* FEC RDATA[0] */
303 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
304 mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
305
306 /* FEC RX_CLK */
307 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
308 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
309
310 /* FEC RX_ER */
311 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
312 mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
313
314 /* FEC COL */
315 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
316 mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
317#endif
318 }
319}
320
321static void power_init_mx51(void)
322{
323 unsigned int val;
324
325 /* Write needed to Power Gate 2 register */
326 val = pmic_reg_read(REG_POWER_MISC);
327
328 /* enable VCAM with 2.775V to enable read from PMIC */
329 val = VCAMCONFIG | VCAMEN;
330 pmic_reg_write(REG_MODE_1, val);
331
332 /*
333 * Set switchers in Auto in NORMAL mode & STANDBY mode
334 * Setup the switcher mode for SW1 & SW2
335 */
336 val = pmic_reg_read(REG_SW_4);
337 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
338 (SWMODE_MASK << SWMODE2_SHIFT)));
339 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
340 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
341 pmic_reg_write(REG_SW_4, val);
342
343 /* Setup the switcher mode for SW3 & SW4 */
344 val = pmic_reg_read(REG_SW_5);
345 val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
346 (SWMODE_MASK << SWMODE3_SHIFT));
347 val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
348 (SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
349 pmic_reg_write(REG_SW_5, val);
350
351
352 /* Set VGEN3 to 1.8V, VCAM to 3.0V */
353 val = pmic_reg_read(REG_SETTING_0);
354 val &= ~(VCAM_MASK | VGEN3_MASK);
355 val |= VCAM_3_0;
356 pmic_reg_write(REG_SETTING_0, val);
357
358 /* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */
359 val = pmic_reg_read(REG_SETTING_1);
360 val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
361 val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8;
362 pmic_reg_write(REG_SETTING_1, val);
363
364 /* Configure VGEN3 and VCAM regulators to use external PNP */
365 val = VGEN3CONFIG | VCAMCONFIG;
366 pmic_reg_write(REG_MODE_1, val);
367 udelay(200);
368
369 /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
370 val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
371 VVIDEOEN | VAUDIOEN | VSDEN;
372 pmic_reg_write(REG_MODE_1, val);
373
374 val = pmic_reg_read(REG_POWER_CTL2);
375 val |= WDIRESET;
376 pmic_reg_write(REG_POWER_CTL2, val);
377
378 udelay(2500);
379
380}
381#endif
382
383static void setup_gpios(void)
384{
385 unsigned int i;
386
387 /* CAM_SUP_DISn, GPIO1_7 */
388 mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
389 mxc_iomux_set_pad(MX51_PIN_GPIO1_7, 0x82);
390
391 /* DAB Display EN, GPIO3_1 */
392 mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT4);
393 mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, 0x82);
394
395 /* WDOG_TRIGGER, GPIO3_2 */
396 mxc_request_iomux(MX51_PIN_DI1_PIN13, IOMUX_CONFIG_ALT4);
397 mxc_iomux_set_pad(MX51_PIN_DI1_PIN13, 0x82);
398
399 /* Now we need to trigger the watchdog */
400 WATCHDOG_RESET();
401
402 /* Display2 TxEN, GPIO3_3 */
403 mxc_request_iomux(MX51_PIN_DI1_D0_CS, IOMUX_CONFIG_ALT4);
404 mxc_iomux_set_pad(MX51_PIN_DI1_D0_CS, 0x82);
405
406 /* DAB Light EN, GPIO3_4 */
407 mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4);
408 mxc_iomux_set_pad(MX51_PIN_DI1_D1_CS, 0x82);
409
410 /* AUDIO_MUTE, GPIO3_5 */
411 mxc_request_iomux(MX51_PIN_DISPB2_SER_DIN, IOMUX_CONFIG_ALT4);
412 mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIN, 0x82);
413
414 /* SPARE_OUT, GPIO3_6 */
415 mxc_request_iomux(MX51_PIN_DISPB2_SER_DIO, IOMUX_CONFIG_ALT4);
416 mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIO, 0x82);
417
418 /* BEEPER_EN, GPIO3_26 */
419 mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT3);
420 mxc_iomux_set_pad(MX51_PIN_NANDF_D14, 0x82);
421
422 /* POWER_OFF, GPIO3_27 */
423 mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT3);
424 mxc_iomux_set_pad(MX51_PIN_NANDF_D13, 0x82);
425
426 /* FRAM_WE, GPIO3_30 */
427 mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT3);
428 mxc_iomux_set_pad(MX51_PIN_NANDF_D10, 0x82);
429
430 /* EXPANSION_EN, GPIO4_26 */
431 mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3);
432 mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x82);
433
Stefano Babica0152c42010-10-21 10:34:39 +0200434 /* PWM Output GPIO1_2 */
435 mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT1);
436
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200437 /*
438 * Set GPIO1_4 to high and output; it is used to reset
439 * the system on reboot
440 */
441 mxc_gpio_set(4, 1);
442 mxc_gpio_direction(4, MXC_GPIO_DIRECTION_OUT);
443
444 mxc_gpio_set(7, 0);
445 mxc_gpio_direction(7, MXC_GPIO_DIRECTION_OUT);
446 for (i = 65; i < 71; i++) {
447 mxc_gpio_set(i, 0);
448 mxc_gpio_direction(i, MXC_GPIO_DIRECTION_OUT);
449 }
450
451 mxc_gpio_set(94, 0);
452 mxc_gpio_direction(94, MXC_GPIO_DIRECTION_OUT);
453
454 /* Set POWER_OFF high */
455 mxc_gpio_set(91, 1);
456 mxc_gpio_direction(91, MXC_GPIO_DIRECTION_OUT);
457
458 mxc_gpio_set(90, 0);
459 mxc_gpio_direction(90, MXC_GPIO_DIRECTION_OUT);
460
461 mxc_gpio_set(122, 0);
462 mxc_gpio_direction(122, MXC_GPIO_DIRECTION_OUT);
463
464 mxc_gpio_set(121, 1);
465 mxc_gpio_direction(121, MXC_GPIO_DIRECTION_OUT);
466
467 WATCHDOG_RESET();
468}
469
470static void setup_fec(void)
471{
472 /*FEC_MDIO*/
473 mxc_request_iomux(MX51_PIN_EIM_EB2, IOMUX_CONFIG_ALT3);
474 mxc_iomux_set_pad(MX51_PIN_EIM_EB2, 0x1FD);
475
476 /*FEC_MDC*/
477 mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
478 mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
479
480 /* FEC RDATA[3] */
481 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
482 mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
483
484 /* FEC RDATA[2] */
485 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
486 mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
487
488 /* FEC RDATA[1] */
489 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
490 mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
491
492 /* FEC RDATA[0] */
493 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
494 mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
495
496 /* FEC TDATA[3] */
497 mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
498 mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
499
500 /* FEC TDATA[2] */
501 mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
502 mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
503
504 /* FEC TDATA[1] */
505 mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
506 mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
507
508 /* FEC TDATA[0] */
509 mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
510 mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
511
512 /* FEC TX_EN */
513 mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
514 mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
515
516 /* FEC TX_ER */
517 mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
518 mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
519
520 /* FEC TX_CLK */
521 mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
522 mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
523
524 /* FEC TX_COL */
525 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
526 mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
527
528 /* FEC RX_CLK */
529 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
530 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
531
532 /* FEC RX_CRS */
533 mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
534 mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
535
536 /* FEC RX_ER */
537 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
538 mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
539
540 /* FEC RX_DV */
541 mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
542 mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
543}
544
545struct fsl_esdhc_cfg esdhc_cfg[1] = {
546 {MMC_SDHC1_BASE_ADDR, 1},
547};
548
549int get_mmc_getcd(u8 *cd, struct mmc *mmc)
550{
551 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
552
553 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
554 *cd = mxc_gpio_get(0);
555 else
556 *cd = 0;
557
558 return 0;
559}
560
561#ifdef CONFIG_FSL_ESDHC
562int board_mmc_init(bd_t *bis)
563{
564 mxc_request_iomux(MX51_PIN_SD1_CMD,
565 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
566 mxc_request_iomux(MX51_PIN_SD1_CLK,
567 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
568 mxc_request_iomux(MX51_PIN_SD1_DATA0,
569 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
570 mxc_request_iomux(MX51_PIN_SD1_DATA1,
571 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
572 mxc_request_iomux(MX51_PIN_SD1_DATA2,
573 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
574 mxc_request_iomux(MX51_PIN_SD1_DATA3,
575 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
576 mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
577 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
578 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
579 PAD_CTL_PUE_PULL |
580 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
581 mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
582 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
583 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
584 PAD_CTL_PUE_PULL |
585 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
586 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
587 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
588 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
589 PAD_CTL_PUE_PULL |
590 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
591 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
592 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
593 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
594 PAD_CTL_PUE_PULL |
595 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
596 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
597 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
598 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
599 PAD_CTL_PUE_PULL |
600 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
601 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
602 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
603 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
604 PAD_CTL_PUE_PULL |
605 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
606 mxc_request_iomux(MX51_PIN_GPIO1_0,
607 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
608 mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
609 PAD_CTL_HYS_ENABLE);
610 mxc_request_iomux(MX51_PIN_GPIO1_1,
611 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
612 mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
613 PAD_CTL_HYS_ENABLE);
614
615 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
616}
617#endif
618
619int board_early_init_f(void)
620{
621
622
623 init_drive_strength();
624
625 /* Setup debug led */
626 mxc_gpio_set(6, 0);
627 mxc_gpio_direction(6, MXC_GPIO_DIRECTION_OUT);
628 mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
629 mxc_iomux_set_pad(MX51_PIN_GPIO1_6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
630
631 /* wait a little while to give the pll time to settle */
632 sdelay(100000);
633
634 setup_weim();
635 setup_uart();
636 setup_fec();
637 setup_gpios();
638
639 spi_io_init();
640
641 return 0;
642}
643
Stefano Babica0152c42010-10-21 10:34:39 +0200644static void backlight(int on)
645{
646 if (on) {
647 mxc_gpio_set(65, 1);
648 udelay(10000);
649 mxc_gpio_set(68, 1);
650 } else {
651 mxc_gpio_set(65, 0);
652 mxc_gpio_set(68, 0);
653 }
654}
655
656void lcd_enable(void)
657{
658 int ret;
659
660 mxc_request_iomux(MX51_PIN_DI1_PIN2, IOMUX_CONFIG_ALT0);
661 mxc_request_iomux(MX51_PIN_DI1_PIN3, IOMUX_CONFIG_ALT0);
662
663 mxc_gpio_set(2, 1);
664 mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0);
665
666 ret = mx51_fb_init(&nec_nl6448bc26_09c);
667 if (ret)
668 puts("LCD cannot be configured\n");
669}
670
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200671int board_init(void)
672{
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200673 gd->bd->bi_arch_number = MACH_TYPE_TTC_VISION2; /* board id for linux */
674 /* address of boot parameters */
675 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
676
677 return 0;
678}
679
680int board_late_init(void)
681{
682 power_init_mx51();
683
684 reset_peripherals(1);
685 udelay(2000);
686 reset_peripherals(0);
687 udelay(2000);
688
689 /* Early revisions require a second reset */
690#ifdef CONFIG_VISION2_HW_1_0
691 reset_peripherals(1);
692 udelay(2000);
693 reset_peripherals(0);
694 udelay(2000);
695#endif
696
697 return 0;
698}
699
700int checkboard(void)
701{
702 u32 system_rev = get_cpu_rev();
703 u32 cause;
704 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
705
706 puts("Board: TTControl Vision II CPU V");
707
708 switch (system_rev & 0xff) {
709 case CHIP_REV_3_0:
710 puts("3.0 [");
711 break;
712 case CHIP_REV_2_5:
713 puts("2.5 [");
714 break;
715 case CHIP_REV_2_0:
716 puts("2.0 [");
717 break;
718 case CHIP_REV_1_1:
719 puts("1.1 [");
720 break;
721 case CHIP_REV_1_0:
722 default:
723 puts("1.0 [");
724 break;
725 }
726
727 cause = src_regs->srsr;
728 switch (cause) {
729 case 0x0001:
730 puts("POR");
731 break;
732 case 0x0009:
733 puts("RST");
734 break;
735 case 0x0010:
736 case 0x0011:
737 puts("WDOG");
738 break;
739 default:
740 printf("unknown 0x%x", cause);
741 }
742 puts("]\n");
743
744 return 0;
745}
746
Stefano Babica0152c42010-10-21 10:34:39 +0200747int do_vision_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
748{
749 int on;
750
751 if (argc < 2)
752 return cmd_usage(cmdtp);
753
754 on = (strcmp(argv[1], "on") == 0);
755 backlight(on);
756
757 return 0;
758}
759
760U_BOOT_CMD(
761 lcdbl, CONFIG_SYS_MAXARGS, 1, do_vision_lcd,
762 "Vision2 Backlight",
763 "lcdbl [on|off]\n"
764);