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Shengzhou Liu48c6f322014-11-24 17:11:56 +08001/**
2 * Copyright 2014 Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 *
6 */
7
8struct cpld_data {
9 u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */
10 u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */
11 u8 hw_ver; /* 0x02 - Hardware Revision Register */
12 u8 sw_ver; /* 0x03 - Software Revision register */
13 u8 res0[12]; /* 0x04 - 0x0F - not used */
14 u8 reset_ctl1; /* 0x10 - Reset control Register1 */
15 u8 reset_ctl2; /* 0x11 - Reset control Register2 */
16 u8 int_status; /* 0x12 - Interrupt status Register */
17 u8 flash_csr; /* 0x13 - Flash control and status register */
18 u8 fan_ctl_status; /* 0x14 - Fan control and status register */
19 u8 led_ctl_status; /* 0x15 - LED control and status register */
20 u8 sfp_ctl_status; /* 0x16 - SFP control and status register */
21 u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/
22 u8 boot_override; /* 0x18 - Boot override register */
23 u8 boot_config1; /* 0x19 - Boot config override register*/
24 u8 boot_config2; /* 0x1A - Boot config override register*/
25} cpld_data_t;
26
27
28/* Pointer to the CPLD register set */
29
30u8 cpld_read(unsigned int reg);
31void cpld_write(unsigned int reg, u8 value);
32
33#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
34#define CPLD_WRITE(reg, value)\
35 cpld_write(offsetof(struct cpld_data, reg), value)
36
37/* CPLD on IFC */
38#define CPLD_LBMAP_MASK 0x3F
39#define CPLD_BANK_SEL_MASK 0x07
40#define CPLD_BANK_OVERRIDE 0x40
41#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
42#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */
43#define CPLD_LBMAP_RESET 0xFF
44#define CPLD_LBMAP_SHIFT 0x03
45#define CPLD_BOOT_SEL 0x80
Shengzhou Liue26416a2014-12-17 16:51:08 +080046
47#define CPLD_PCIE_SGMII_MUX 0x80
48#define CPLD_OVERRIDE_BOOT_EN 0x01
49#define CPLD_OVERRIDE_MUX_EN 0x02 /* PCIE/2.5G-SGMII mux override enable */