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Prabhakar Kushwaha7d436072013-09-12 11:11:28 +05301/*
York Sunc60dee02014-03-27 17:54:48 -07002 * Copyright 2013-2014 Freescale Semiconductor, Inc.
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +05303 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#ifndef __CONFIG_H
24#define __CONFIG_H
25
26/*
27 * T1040 QDS board configuration file
28 */
29#define CONFIG_T1040QDS
30#define CONFIG_PHYS_64BIT
vijay rai2aea6612014-11-18 12:21:13 +053031#define CONFIG_SYS_GENERIC_BOARD
32#define CONFIG_DISPLAY_BOARDINFO
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053033
34#ifdef CONFIG_RAMBOOT_PBL
35#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
36#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Masahiro Yamadae4536f82014-03-11 11:05:16 +090037#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
38#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053039#endif
40
41/* High Level Configuration Options */
42#define CONFIG_BOOKE
43#define CONFIG_E500 /* BOOKE e500 family */
44#define CONFIG_E500MC /* BOOKE e500mc family */
45#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053046#define CONFIG_MP /* support multiple processors */
47
Tang Yuantian48f6a9a2014-04-17 15:33:44 +080048/* support deep sleep */
49#define CONFIG_DEEP_SLEEP
tang yuantian7d0e97a2014-12-18 10:20:07 +080050#if defined(CONFIG_DEEP_SLEEP)
Tang Yuantian48f6a9a2014-04-17 15:33:44 +080051#define CONFIG_SILENT_CONSOLE
tang yuantian7d0e97a2014-12-18 10:20:07 +080052#define CONFIG_BOARD_EARLY_INIT_F
53#endif
Tang Yuantian48f6a9a2014-04-17 15:33:44 +080054
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053055#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053056#define CONFIG_SYS_TEXT_BASE 0xeff40000
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053057#endif
58
59#ifndef CONFIG_RESET_VECTOR_ADDRESS
60#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
61#endif
62
63#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
64#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
65#define CONFIG_FSL_IFC /* Enable IFC Support */
Ruchika Gupta737537e2014-10-15 11:35:31 +053066#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053067#define CONFIG_PCI /* Enable PCI/PCIE */
68#define CONFIG_PCI_INDIRECT_BRIDGE
69#define CONFIG_PCIE1 /* PCIE controler 1 */
70#define CONFIG_PCIE2 /* PCIE controler 2 */
71#define CONFIG_PCIE3 /* PCIE controler 3 */
72#define CONFIG_PCIE4 /* PCIE controler 4 */
73
74#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
75#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
76
77#define CONFIG_FSL_LAW /* Use common FSL init code */
78
79#define CONFIG_ENV_OVERWRITE
80
81#ifdef CONFIG_SYS_NO_FLASH
82#define CONFIG_ENV_IS_NOWHERE
83#else
84#define CONFIG_FLASH_CFI_DRIVER
85#define CONFIG_SYS_FLASH_CFI
86#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
87#endif
88
89#ifndef CONFIG_SYS_NO_FLASH
90#if defined(CONFIG_SPIFLASH)
91#define CONFIG_SYS_EXTRA_ENV_RELOC
92#define CONFIG_ENV_IS_IN_SPI_FLASH
93#define CONFIG_ENV_SPI_BUS 0
94#define CONFIG_ENV_SPI_CS 0
95#define CONFIG_ENV_SPI_MAX_HZ 10000000
96#define CONFIG_ENV_SPI_MODE 0
97#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
98#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
99#define CONFIG_ENV_SECT_SIZE 0x10000
100#elif defined(CONFIG_SDCARD)
101#define CONFIG_SYS_EXTRA_ENV_RELOC
102#define CONFIG_ENV_IS_IN_MMC
103#define CONFIG_SYS_MMC_ENV_DEV 0
104#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530105#define CONFIG_ENV_OFFSET (512 * 1658)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530106#elif defined(CONFIG_NAND)
107#define CONFIG_SYS_EXTRA_ENV_RELOC
108#define CONFIG_ENV_IS_IN_NAND
109#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530110#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530111#else
112#define CONFIG_ENV_IS_IN_FLASH
113#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
114#define CONFIG_ENV_SIZE 0x2000
115#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
116#endif
117#else /* CONFIG_SYS_NO_FLASH */
118#define CONFIG_ENV_SIZE 0x2000
119#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
120#endif
121
122#ifndef __ASSEMBLY__
123unsigned long get_board_sys_clk(void);
124unsigned long get_board_ddr_clk(void);
125#endif
126
127#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
128#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
129
130/*
131 * These can be toggled for performance analysis, otherwise use default.
132 */
133#define CONFIG_SYS_CACHE_STASHING
134#define CONFIG_BACKSIDE_L2_CACHE
135#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
136#define CONFIG_BTB /* toggle branch predition */
137#define CONFIG_DDR_ECC
138#ifdef CONFIG_DDR_ECC
139#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
140#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
141#endif
142
143#define CONFIG_ENABLE_36BIT_PHYS
144
145#define CONFIG_ADDR_MAP
146#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
147
148#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
149#define CONFIG_SYS_MEMTEST_END 0x00400000
150#define CONFIG_SYS_ALT_MEMTEST
151#define CONFIG_PANIC_HANG /* do not reset board on panic */
152
153/*
154 * Config the L3 Cache as L3 SRAM
155 */
156#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
157
158#define CONFIG_SYS_DCSRBAR 0xf0000000
159#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
160
161/* EEPROM */
162#define CONFIG_ID_EEPROM
163#define CONFIG_SYS_I2C_EEPROM_NXID
164#define CONFIG_SYS_EEPROM_BUS_NUM 0
165#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
166#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
167#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
168#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
169
170/*
171 * DDR Setup
172 */
173#define CONFIG_VERY_BIG_RAM
174#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
175#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
176
177/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
178#define CONFIG_DIMM_SLOTS_PER_CTLR 1
Priyanka Jain2eb3ac72014-01-03 11:24:55 +0530179#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530180
181#define CONFIG_DDR_SPD
York Sunc60dee02014-03-27 17:54:48 -0700182#ifndef CONFIG_SYS_FSL_DDR4
York Sun5614e712013-09-30 09:22:09 -0700183#define CONFIG_SYS_FSL_DDR3
York Sunc60dee02014-03-27 17:54:48 -0700184#endif
York Sun1b2af9b2014-10-27 11:45:11 -0700185#define CONFIG_FSL_DDR_INTERACTIVE
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530186
187#define CONFIG_SYS_SPD_BUS_NUM 0
188#define SPD_EEPROM_ADDRESS 0x51
189
190#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
191
192/*
193 * IFC Definitions
194 */
195#define CONFIG_SYS_FLASH_BASE 0xe0000000
196#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
197
198#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
199#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
200 + 0x8000000) | \
201 CSPR_PORT_SIZE_16 | \
202 CSPR_MSEL_NOR | \
203 CSPR_V)
204#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
205#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
206 CSPR_PORT_SIZE_16 | \
207 CSPR_MSEL_NOR | \
208 CSPR_V)
209#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
Sandeep Singh377ffcf2014-06-05 18:49:57 +0530210
211/*
212 * TDM Definition
213 */
214#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
215
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530216/* NOR Flash Timing Params */
217#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
218#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
219 FTIM0_NOR_TEADC(0x5) | \
220 FTIM0_NOR_TEAHC(0x5))
221#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
222 FTIM1_NOR_TRAD_NOR(0x1A) |\
223 FTIM1_NOR_TSEQRAD_NOR(0x13))
224#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
225 FTIM2_NOR_TCH(0x4) | \
226 FTIM2_NOR_TWPH(0x0E) | \
227 FTIM2_NOR_TWP(0x1c))
228#define CONFIG_SYS_NOR_FTIM3 0x0
229
230#define CONFIG_SYS_FLASH_QUIET_TEST
231#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
232
233#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
234#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
235#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
236#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
237
238#define CONFIG_SYS_FLASH_EMPTY_INFO
239#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
240 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
241#define CONFIG_FSL_QIXIS /* use common QIXIS code */
242#define QIXIS_BASE 0xffdf0000
243#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
244#define QIXIS_LBMAP_SWITCH 0x06
245#define QIXIS_LBMAP_MASK 0x0f
246#define QIXIS_LBMAP_SHIFT 0
247#define QIXIS_LBMAP_DFLTBANK 0x00
248#define QIXIS_LBMAP_ALTBANK 0x04
249#define QIXIS_RST_CTL_RESET 0x31
250#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
251#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
252#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
Prabhakar Kushwaha8c618dd2013-12-26 12:40:55 +0530253#define QIXIS_RST_FORCE_MEM 0x01
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530254
255#define CONFIG_SYS_CSPR3_EXT (0xf)
256#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
257 | CSPR_PORT_SIZE_8 \
258 | CSPR_MSEL_GPCM \
259 | CSPR_V)
260#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
261#define CONFIG_SYS_CSOR3 0x0
262/* QIXIS Timing parameters for IFC CS3 */
263#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
264 FTIM0_GPCM_TEADC(0x0e) | \
265 FTIM0_GPCM_TEAHC(0x0e))
266#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
267 FTIM1_GPCM_TRAD(0x3f))
268#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Prabhakar Kushwaha562de1d2013-12-12 12:09:01 +0530269 FTIM2_GPCM_TCH(0x8) | \
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530270 FTIM2_GPCM_TWP(0x1f))
271#define CONFIG_SYS_CS3_FTIM3 0x0
272
273#define CONFIG_NAND_FSL_IFC
274#define CONFIG_SYS_NAND_BASE 0xff800000
275#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
276
277#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
278#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
279 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
280 | CSPR_MSEL_NAND /* MSEL = NAND */ \
281 | CSPR_V)
282#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
283
284#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
285 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
286 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
287 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
288 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
289 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
290 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
291
292#define CONFIG_SYS_NAND_ONFI_DETECTION
293
294/* ONFI NAND Flash mode0 Timing Params */
295#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
296 FTIM0_NAND_TWP(0x18) | \
297 FTIM0_NAND_TWCHT(0x07) | \
298 FTIM0_NAND_TWH(0x0a))
299#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
300 FTIM1_NAND_TWBE(0x39) | \
301 FTIM1_NAND_TRR(0x0e) | \
302 FTIM1_NAND_TRP(0x18))
303#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
304 FTIM2_NAND_TREH(0x0a) | \
305 FTIM2_NAND_TWHRE(0x1e))
306#define CONFIG_SYS_NAND_FTIM3 0x0
307
308#define CONFIG_SYS_NAND_DDR_LAW 11
309#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
310#define CONFIG_SYS_MAX_NAND_DEVICE 1
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530311#define CONFIG_CMD_NAND
312
313#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
314
315#if defined(CONFIG_NAND)
316#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
317#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
318#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
319#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
320#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
321#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
322#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
323#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
324#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
325#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
326#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
327#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
328#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
329#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
330#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
331#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
332#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
333#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
334#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
335#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
336#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
337#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
338#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
339#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
340#else
341#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
342#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
343#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
344#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
345#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
346#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
347#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
348#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
349#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
350#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
351#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
352#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
353#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
354#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
355#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
356#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
357#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
358#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
359#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
360#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
361#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
362#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
363#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
364#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
365#endif
366
367#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
368
369#if defined(CONFIG_RAMBOOT_PBL)
370#define CONFIG_SYS_RAMBOOT
371#endif
372
373#define CONFIG_BOARD_EARLY_INIT_R
374#define CONFIG_MISC_INIT_R
375
376#define CONFIG_HWCONFIG
377
378/* define to use L1 as initial stack */
379#define CONFIG_L1_INIT_RAM
380#define CONFIG_SYS_INIT_RAM_LOCK
381#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
382#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
383#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
384/* The assembler doesn't like typecast */
385#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
386 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
387 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
388#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
389
390#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
391 GENERATED_GBL_DATA_SIZE)
392#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
393
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530394#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Priyanka Jain337b0c52014-02-26 16:11:53 +0530395#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530396
397/* Serial Port - controlled on board with jumper J8
398 * open - index 2
399 * shorted - index 1
400 */
401#define CONFIG_CONS_INDEX 1
402#define CONFIG_SYS_NS16550
403#define CONFIG_SYS_NS16550_SERIAL
404#define CONFIG_SYS_NS16550_REG_SIZE 1
405#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
406
407#define CONFIG_SYS_BAUDRATE_TABLE \
408 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
409
410#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
411#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
412#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
413#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
414#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
415#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
416
417/* Use the HUSH parser */
418#define CONFIG_SYS_HUSH_PARSER
419#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
420
Priyanka Jain337b0c52014-02-26 16:11:53 +0530421/* Video */
422#define CONFIG_FSL_DIU_FB
423#ifdef CONFIG_FSL_DIU_FB
Wang Dongshengc53711b2014-03-19 10:47:55 +0800424#define CONFIG_FSL_DIU_CH7301
Priyanka Jain337b0c52014-02-26 16:11:53 +0530425#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
426#define CONFIG_VIDEO
427#define CONFIG_CMD_BMP
428#define CONFIG_CFB_CONSOLE
429#define CONFIG_VIDEO_SW_CURSOR
430#define CONFIG_VGA_AS_SINGLE_DEVICE
431#define CONFIG_VIDEO_LOGO
432#define CONFIG_VIDEO_BMP_LOGO
433#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
434/*
435 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
436 * disable empty flash sector detection, which is I/O-intensive.
437 */
438#undef CONFIG_SYS_FLASH_EMPTY_INFO
439#endif
440
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530441/* pass open firmware flat tree */
442#define CONFIG_OF_LIBFDT
443#define CONFIG_OF_BOARD_SETUP
444#define CONFIG_OF_STDOUT_VIA_ALIAS
445
446/* new uImage format support */
447#define CONFIG_FIT
448#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
449
450/* I2C */
451#define CONFIG_SYS_I2C
452#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
Priyanka Jain2eb3ac72014-01-03 11:24:55 +0530453#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
Shengzhou Liub0d97cd2014-07-07 12:17:47 +0800454#define CONFIG_SYS_FSL_I2C2_SPEED 50000
455#define CONFIG_SYS_FSL_I2C3_SPEED 50000
456#define CONFIG_SYS_FSL_I2C4_SPEED 50000
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530457#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530458#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
Shengzhou Liub0d97cd2014-07-07 12:17:47 +0800459#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
460#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530461#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
Shengzhou Liub0d97cd2014-07-07 12:17:47 +0800462#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
463#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
464#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530465
466#define I2C_MUX_PCA_ADDR 0x77
467#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
468
469
470/* I2C bus multiplexer */
471#define I2C_MUX_CH_DEFAULT 0x8
Priyanka Jain337b0c52014-02-26 16:11:53 +0530472#define I2C_MUX_CH_DIU 0xC
473
474/* LDI/DVI Encoder for display */
475#define CONFIG_SYS_I2C_LDI_ADDR 0x38
476#define CONFIG_SYS_I2C_DVI_ADDR 0x75
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530477
478/*
479 * RTC configuration
480 */
481#define RTC
482#define CONFIG_RTC_DS3231 1
483#define CONFIG_SYS_I2C_RTC_ADDR 0x68
484
485/*
486 * eSPI - Enhanced SPI
487 */
488#define CONFIG_FSL_ESPI
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530489#define CONFIG_SPI_FLASH_STMICRO
490#define CONFIG_SPI_FLASH_SST
491#define CONFIG_SPI_FLASH_EON
492#define CONFIG_CMD_SF
493#define CONFIG_SF_DEFAULT_SPEED 10000000
494#define CONFIG_SF_DEFAULT_MODE 0
495
496/*
497 * General PCI
498 * Memory space is mapped 1-1, but I/O space must start from 0.
499 */
500
501#ifdef CONFIG_PCI
502/* controller 1, direct to uli, tgtid 3, Base address 20000 */
503#ifdef CONFIG_PCIE1
504#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
505#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
506#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
507#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
508#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
509#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
510#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
511#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
512#endif
513
514/* controller 2, Slot 2, tgtid 2, Base address 201000 */
515#ifdef CONFIG_PCIE2
516#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
517#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
518#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
519#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
520#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
521#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
522#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
523#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
524#endif
525
526/* controller 3, Slot 1, tgtid 1, Base address 202000 */
527#ifdef CONFIG_PCIE3
528#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
529#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
530#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
531#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
532#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
533#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
534#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
535#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
536#endif
537
538/* controller 4, Base address 203000 */
539#ifdef CONFIG_PCIE4
540#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
541#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
542#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
543#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
544#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
545#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
546#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
547#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
548#endif
549
550#define CONFIG_PCI_PNP /* do pci plug-and-play */
551#define CONFIG_E1000
552
553#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
554#define CONFIG_DOS_PARTITION
555#endif /* CONFIG_PCI */
556
557/* SATA */
558#define CONFIG_FSL_SATA_V2
559#ifdef CONFIG_FSL_SATA_V2
560#define CONFIG_LIBATA
561#define CONFIG_FSL_SATA
562
563#define CONFIG_SYS_SATA_MAX_DEVICE 2
564#define CONFIG_SATA1
565#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
566#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
567#define CONFIG_SATA2
568#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
569#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
570
571#define CONFIG_LBA48
572#define CONFIG_CMD_SATA
573#define CONFIG_DOS_PARTITION
574#define CONFIG_CMD_EXT2
575#endif
576
577/*
578* USB
579*/
580#define CONFIG_HAS_FSL_DR_USB
581
582#ifdef CONFIG_HAS_FSL_DR_USB
583#define CONFIG_USB_EHCI
584
585#ifdef CONFIG_USB_EHCI
586#define CONFIG_CMD_USB
587#define CONFIG_USB_STORAGE
588#define CONFIG_USB_EHCI_FSL
589#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
590#define CONFIG_CMD_EXT2
591#endif
592#endif
593
594#define CONFIG_MMC
595
596#ifdef CONFIG_MMC
597#define CONFIG_FSL_ESDHC
598#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
599#define CONFIG_CMD_MMC
600#define CONFIG_GENERIC_MMC
601#define CONFIG_CMD_EXT2
602#define CONFIG_CMD_FAT
603#define CONFIG_DOS_PARTITION
604#endif
605
606/* Qman/Bman */
607#ifndef CONFIG_NOBQFMAN
608#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
Jeffrey Ladouceur2a8b3422014-12-03 18:08:43 -0500609#define CONFIG_SYS_BMAN_NUM_PORTALS 10
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530610#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
611#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
612#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500613#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
614#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
615#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
616#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
617#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
618 CONFIG_SYS_BMAN_CENA_SIZE)
619#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
620#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Jeffrey Ladouceur2a8b3422014-12-03 18:08:43 -0500621#define CONFIG_SYS_QMAN_NUM_PORTALS 10
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530622#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
623#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
624#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500625#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
626#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
627#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
628#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
629#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
630 CONFIG_SYS_QMAN_CENA_SIZE)
631#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
632#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530633
634#define CONFIG_SYS_DPAA_FMAN
635#define CONFIG_SYS_DPAA_PME
636
Zhao Qiang6259e292014-03-21 16:21:46 +0800637#define CONFIG_QE
638#define CONFIG_U_QE
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530639/* Default address of microcode for the Linux Fman driver */
640#if defined(CONFIG_SPIFLASH)
641/*
642 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
643 * env, so we got 0x110000.
644 */
645#define CONFIG_SYS_QE_FW_IN_SPIFLASH
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800646#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530647#elif defined(CONFIG_SDCARD)
648/*
649 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530650 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
651 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530652 */
653#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800654#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530655#elif defined(CONFIG_NAND)
656#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800657#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530658#else
659#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800660#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
Zhao Qiang6259e292014-03-21 16:21:46 +0800661#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530662#endif
663#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
664#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
665#endif /* CONFIG_NOBQFMAN */
666
667#ifdef CONFIG_SYS_DPAA_FMAN
668#define CONFIG_FMAN_ENET
669#define CONFIG_PHYLIB_10G
670#define CONFIG_PHY_VITESSE
671#define CONFIG_PHY_REALTEK
672#define CONFIG_PHY_TERANETICS
673#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
674#define SGMII_CARD_PORT2_PHY_ADDR 0x10
675#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
676#define SGMII_CARD_PORT4_PHY_ADDR 0x11
677#endif
678
679#ifdef CONFIG_FMAN_ENET
Prabhakar Kushwaha5b7672f2014-01-27 15:55:20 +0530680#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01
681#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530682
683#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
684#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
685#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
686#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
687
688#define CONFIG_MII /* MII PHY management */
689#define CONFIG_ETHPRIME "FM1@DTSEC1"
690#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
691#endif
692
Codrin Ciubotariua83fccc2015-01-21 11:54:11 +0200693/* Enable VSC9953 L2 Switch driver */
694#define CONFIG_VSC9953
695#define CONFIG_VSC9953_CMD
696#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14
697#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18
698
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530699/*
Prabhakar Kushwaha68b74732014-04-02 17:26:23 +0530700 * Dynamic MTD Partition support with mtdparts
701 */
702#ifndef CONFIG_SYS_NO_FLASH
703#define CONFIG_MTD_DEVICE
704#define CONFIG_MTD_PARTITIONS
705#define CONFIG_CMD_MTDPARTS
706#define CONFIG_FLASH_CFI_MTD
707#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
708 "spi0=spife110000.0"
709#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
710 "128k(dtb),96m(fs),-(user);"\
711 "fff800000.flash:2m(uboot),9m(kernel),"\
712 "128k(dtb),96m(fs),-(user);spife110000.0:" \
713 "2m(uboot),9m(kernel),128k(dtb),-(user)"
714#endif
715
716/*
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530717 * Environment
718 */
719#define CONFIG_LOADS_ECHO /* echo on for serial download */
720#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
721
722/*
723 * Command line configuration.
724 */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530725#define CONFIG_CMD_DATE
726#define CONFIG_CMD_DHCP
727#define CONFIG_CMD_EEPROM
728#define CONFIG_CMD_ELF
729#define CONFIG_CMD_ERRATA
730#define CONFIG_CMD_GREPENV
731#define CONFIG_CMD_IRQ
732#define CONFIG_CMD_I2C
733#define CONFIG_CMD_MII
734#define CONFIG_CMD_PING
735#define CONFIG_CMD_REGINFO
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530736
737#ifdef CONFIG_PCI
738#define CONFIG_CMD_PCI
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530739#endif
740
Ruchika Gupta737537e2014-10-15 11:35:31 +0530741/* Hash command with SHA acceleration supported in hardware */
742#ifdef CONFIG_FSL_CAAM
743#define CONFIG_CMD_HASH
744#define CONFIG_SHA_HW_ACCEL
745#endif
746
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530747/*
748 * Miscellaneous configurable options
749 */
750#define CONFIG_SYS_LONGHELP /* undef to save memory */
751#define CONFIG_CMDLINE_EDITING /* Command-line editing */
752#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
753#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530754#ifdef CONFIG_CMD_KGDB
755#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
756#else
757#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
758#endif
759#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
760#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
761#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530762
763/*
764 * For booting Linux, the board info and command line data
765 * have to be in the first 64 MB of memory, since this is
766 * the maximum mapped by the Linux kernel during initialization.
767 */
768#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
769#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
770
771#ifdef CONFIG_CMD_KGDB
772#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530773#endif
774
775/*
776 * Environment Configuration
777 */
778#define CONFIG_ROOTPATH "/opt/nfsroot"
779#define CONFIG_BOOTFILE "uImage"
780#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
781
782/* default location for tftp and bootm */
783#define CONFIG_LOADADDR 1000000
784
785#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
786
787#define CONFIG_BAUDRATE 115200
788
789#define __USB_PHY_TYPE utmi
790
791#define CONFIG_EXTRA_ENV_SETTINGS \
York Sun1b2af9b2014-10-27 11:45:11 -0700792 "hwconfig=fsl_ddr:bank_intlv=auto;" \
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530793 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
794 "netdev=eth0\0" \
Priyanka Jain337b0c52014-02-26 16:11:53 +0530795 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530796 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
797 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
798 "tftpflash=tftpboot $loadaddr $uboot && " \
799 "protect off $ubootaddr +$filesize && " \
800 "erase $ubootaddr +$filesize && " \
801 "cp.b $loadaddr $ubootaddr $filesize && " \
802 "protect on $ubootaddr +$filesize && " \
803 "cmp.b $loadaddr $ubootaddr $filesize\0" \
804 "consoledev=ttyS0\0" \
805 "ramdiskaddr=2000000\0" \
806 "ramdiskfile=t1040qds/ramdisk.uboot\0" \
807 "fdtaddr=c00000\0" \
808 "fdtfile=t1040qds/t1040qds.dtb\0" \
Kim Phillips32465842014-05-14 19:33:45 -0500809 "bdev=sda3\0"
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530810
811#define CONFIG_LINUX \
812 "setenv bootargs root=/dev/ram rw " \
813 "console=$consoledev,$baudrate $othbootargs;" \
814 "setenv ramdiskaddr 0x02000000;" \
815 "setenv fdtaddr 0x00c00000;" \
816 "setenv loadaddr 0x1000000;" \
817 "bootm $loadaddr $ramdiskaddr $fdtaddr"
818
819#define CONFIG_HDBOOT \
820 "setenv bootargs root=/dev/$bdev rw " \
821 "console=$consoledev,$baudrate $othbootargs;" \
822 "tftp $loadaddr $bootfile;" \
823 "tftp $fdtaddr $fdtfile;" \
824 "bootm $loadaddr - $fdtaddr"
825
826#define CONFIG_NFSBOOTCOMMAND \
827 "setenv bootargs root=/dev/nfs rw " \
828 "nfsroot=$serverip:$rootpath " \
829 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
830 "console=$consoledev,$baudrate $othbootargs;" \
831 "tftp $loadaddr $bootfile;" \
832 "tftp $fdtaddr $fdtfile;" \
833 "bootm $loadaddr - $fdtaddr"
834
835#define CONFIG_RAMBOOTCOMMAND \
836 "setenv bootargs root=/dev/ram rw " \
837 "console=$consoledev,$baudrate $othbootargs;" \
838 "tftp $ramdiskaddr $ramdiskfile;" \
839 "tftp $loadaddr $bootfile;" \
840 "tftp $fdtaddr $fdtfile;" \
841 "bootm $loadaddr $ramdiskaddr $fdtaddr"
842
843#define CONFIG_BOOTCOMMAND CONFIG_LINUX
844
845#ifdef CONFIG_SECURE_BOOT
846#include <asm/fsl_secure_boot.h>
Ruchika Gupta789490b2014-10-07 15:48:46 +0530847#define CONFIG_CMD_BLOB
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530848#endif
849
850#endif /* __CONFIG_H */