Simon Glass | dde3b70 | 2012-02-23 03:28:41 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2004-2008 Texas Instruments |
| 3 | * |
| 4 | * (C) Copyright 2002 |
| 5 | * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> |
| 6 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 7 | * SPDX-License-Identifier: GPL-2.0+ |
Simon Glass | dde3b70 | 2012-02-23 03:28:41 +0000 | [diff] [blame] | 8 | */ |
| 9 | |
Marc Zyngier | bf433af | 2014-07-12 14:24:02 +0100 | [diff] [blame] | 10 | #include <config.h> |
| 11 | |
Simon Glass | dde3b70 | 2012-02-23 03:28:41 +0000 | [diff] [blame] | 12 | OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
| 13 | OUTPUT_ARCH(arm) |
| 14 | ENTRY(_start) |
| 15 | SECTIONS |
| 16 | { |
Wang Dongsheng | c5e954e | 2016-01-18 11:02:40 +0800 | [diff] [blame] | 17 | #if defined(CONFIG_ARMV7_SECURE_BASE) && defined(CONFIG_ARMV7_NONSEC) |
Peng Fan | d47cb0b | 2015-10-23 10:13:03 +0800 | [diff] [blame] | 18 | /* |
Wang Dongsheng | c5e954e | 2016-01-18 11:02:40 +0800 | [diff] [blame] | 19 | * If CONFIG_ARMV7_SECURE_BASE is true, secure code will not |
| 20 | * bundle with u-boot, and code offsets are fixed. Secure zone |
| 21 | * only needs to be copied from the loading address to |
| 22 | * CONFIG_ARMV7_SECURE_BASE, which is the linking and running |
| 23 | * address for secure code. |
Peng Fan | d47cb0b | 2015-10-23 10:13:03 +0800 | [diff] [blame] | 24 | * |
Wang Dongsheng | c5e954e | 2016-01-18 11:02:40 +0800 | [diff] [blame] | 25 | * If CONFIG_ARMV7_SECURE_BASE is undefined, the secure zone will |
| 26 | * be included in u-boot address space, and some absolute address |
| 27 | * were used in secure code. The absolute addresses of the secure |
| 28 | * code also needs to be relocated along with the accompanying u-boot |
| 29 | * code. |
| 30 | * |
| 31 | * So DISCARD is only for CONFIG_ARMV7_SECURE_BASE. |
Peng Fan | d47cb0b | 2015-10-23 10:13:03 +0800 | [diff] [blame] | 32 | */ |
| 33 | /DISCARD/ : { *(.rel._secure*) } |
Wang Dongsheng | c5e954e | 2016-01-18 11:02:40 +0800 | [diff] [blame] | 34 | #endif |
Simon Glass | dde3b70 | 2012-02-23 03:28:41 +0000 | [diff] [blame] | 35 | . = 0x00000000; |
| 36 | |
| 37 | . = ALIGN(4); |
| 38 | .text : |
| 39 | { |
Albert ARIBAUD | d026dec | 2013-06-11 14:17:33 +0200 | [diff] [blame] | 40 | *(.__image_copy_start) |
Albert ARIBAUD | 41623c9 | 2014-04-15 16:13:51 +0200 | [diff] [blame] | 41 | *(.vectors) |
Stephen Warren | b68d671 | 2012-10-22 06:19:32 +0000 | [diff] [blame] | 42 | CPUDIR/start.o (.text*) |
| 43 | *(.text*) |
Simon Glass | dde3b70 | 2012-02-23 03:28:41 +0000 | [diff] [blame] | 44 | } |
| 45 | |
Jan Kiszka | 104d6fb | 2015-04-21 07:18:24 +0200 | [diff] [blame] | 46 | #ifdef CONFIG_ARMV7_NONSEC |
Marc Zyngier | bf433af | 2014-07-12 14:24:02 +0100 | [diff] [blame] | 47 | |
| 48 | #ifndef CONFIG_ARMV7_SECURE_BASE |
| 49 | #define CONFIG_ARMV7_SECURE_BASE |
| 50 | #endif |
| 51 | |
| 52 | .__secure_start : { |
| 53 | . = ALIGN(0x1000); |
| 54 | *(.__secure_start) |
| 55 | } |
| 56 | |
| 57 | .secure_text CONFIG_ARMV7_SECURE_BASE : |
| 58 | AT(ADDR(.__secure_start) + SIZEOF(.__secure_start)) |
| 59 | { |
| 60 | *(._secure.text) |
| 61 | } |
| 62 | |
| 63 | . = LOADADDR(.__secure_start) + |
| 64 | SIZEOF(.__secure_start) + |
| 65 | SIZEOF(.secure_text); |
| 66 | |
| 67 | __secure_end_lma = .; |
| 68 | .__secure_end : AT(__secure_end_lma) { |
| 69 | *(.__secure_end) |
| 70 | LONG(0x1d1071c); /* Must output something to reset LMA */ |
| 71 | } |
| 72 | #endif |
| 73 | |
Simon Glass | dde3b70 | 2012-02-23 03:28:41 +0000 | [diff] [blame] | 74 | . = ALIGN(4); |
| 75 | .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } |
| 76 | |
| 77 | . = ALIGN(4); |
| 78 | .data : { |
Stephen Warren | b68d671 | 2012-10-22 06:19:32 +0000 | [diff] [blame] | 79 | *(.data*) |
Simon Glass | dde3b70 | 2012-02-23 03:28:41 +0000 | [diff] [blame] | 80 | } |
| 81 | |
| 82 | . = ALIGN(4); |
| 83 | |
| 84 | . = .; |
Simon Glass | dde3b70 | 2012-02-23 03:28:41 +0000 | [diff] [blame] | 85 | |
| 86 | . = ALIGN(4); |
Marek Vasut | 5567514 | 2012-10-12 10:27:03 +0000 | [diff] [blame] | 87 | .u_boot_list : { |
Albert ARIBAUD | ef123c5 | 2013-02-25 00:59:00 +0000 | [diff] [blame] | 88 | KEEP(*(SORT(.u_boot_list*))); |
Marek Vasut | 5567514 | 2012-10-12 10:27:03 +0000 | [diff] [blame] | 89 | } |
| 90 | |
| 91 | . = ALIGN(4); |
Simon Glass | dde3b70 | 2012-02-23 03:28:41 +0000 | [diff] [blame] | 92 | |
Albert ARIBAUD | d026dec | 2013-06-11 14:17:33 +0200 | [diff] [blame] | 93 | .image_copy_end : |
| 94 | { |
| 95 | *(.__image_copy_end) |
| 96 | } |
Simon Glass | dde3b70 | 2012-02-23 03:28:41 +0000 | [diff] [blame] | 97 | |
Albert ARIBAUD | 47bd65e | 2013-06-11 14:17:34 +0200 | [diff] [blame] | 98 | .rel_dyn_start : |
| 99 | { |
| 100 | *(.__rel_dyn_start) |
| 101 | } |
| 102 | |
Simon Glass | dde3b70 | 2012-02-23 03:28:41 +0000 | [diff] [blame] | 103 | .rel.dyn : { |
Simon Glass | dde3b70 | 2012-02-23 03:28:41 +0000 | [diff] [blame] | 104 | *(.rel*) |
Albert ARIBAUD | 47bd65e | 2013-06-11 14:17:34 +0200 | [diff] [blame] | 105 | } |
| 106 | |
| 107 | .rel_dyn_end : |
| 108 | { |
| 109 | *(.__rel_dyn_end) |
Simon Glass | dde3b70 | 2012-02-23 03:28:41 +0000 | [diff] [blame] | 110 | } |
| 111 | |
Albert ARIBAUD | d0b5d9d | 2014-02-22 17:53:42 +0100 | [diff] [blame] | 112 | .end : |
| 113 | { |
| 114 | *(.__end) |
| 115 | } |
| 116 | |
| 117 | _image_binary_end = .; |
Simon Glass | dde3b70 | 2012-02-23 03:28:41 +0000 | [diff] [blame] | 118 | |
| 119 | /* |
| 120 | * Deprecated: this MMU section is used by pxa at present but |
| 121 | * should not be used by new boards/CPUs. |
| 122 | */ |
| 123 | . = ALIGN(4096); |
| 124 | .mmutable : { |
| 125 | *(.mmutable) |
| 126 | } |
| 127 | |
Albert ARIBAUD | f84a7b8 | 2013-04-11 05:43:21 +0000 | [diff] [blame] | 128 | /* |
| 129 | * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c |
| 130 | * __bss_base and __bss_limit are for linker only (overlay ordering) |
| 131 | */ |
| 132 | |
Albert ARIBAUD | 3ebd1cb | 2013-02-25 00:58:59 +0000 | [diff] [blame] | 133 | .bss_start __rel_dyn_start (OVERLAY) : { |
| 134 | KEEP(*(.__bss_start)); |
Albert ARIBAUD | f84a7b8 | 2013-04-11 05:43:21 +0000 | [diff] [blame] | 135 | __bss_base = .; |
Albert ARIBAUD | 3ebd1cb | 2013-02-25 00:58:59 +0000 | [diff] [blame] | 136 | } |
| 137 | |
Albert ARIBAUD | f84a7b8 | 2013-04-11 05:43:21 +0000 | [diff] [blame] | 138 | .bss __bss_base (OVERLAY) : { |
Stephen Warren | b68d671 | 2012-10-22 06:19:32 +0000 | [diff] [blame] | 139 | *(.bss*) |
Simon Glass | dde3b70 | 2012-02-23 03:28:41 +0000 | [diff] [blame] | 140 | . = ALIGN(4); |
Albert ARIBAUD | f84a7b8 | 2013-04-11 05:43:21 +0000 | [diff] [blame] | 141 | __bss_limit = .; |
Albert ARIBAUD | 3ebd1cb | 2013-02-25 00:58:59 +0000 | [diff] [blame] | 142 | } |
Tom Rini | 0ce033d | 2013-03-18 12:31:00 -0400 | [diff] [blame] | 143 | |
Albert ARIBAUD | f84a7b8 | 2013-04-11 05:43:21 +0000 | [diff] [blame] | 144 | .bss_end __bss_limit (OVERLAY) : { |
| 145 | KEEP(*(.__bss_end)); |
Simon Glass | dde3b70 | 2012-02-23 03:28:41 +0000 | [diff] [blame] | 146 | } |
| 147 | |
Albert ARIBAUD | d0b5d9d | 2014-02-22 17:53:42 +0100 | [diff] [blame] | 148 | .dynsym _image_binary_end : { *(.dynsym) } |
Albert ARIBAUD | 47ed5dd | 2013-11-07 14:21:46 +0100 | [diff] [blame] | 149 | .dynbss : { *(.dynbss) } |
| 150 | .dynstr : { *(.dynstr*) } |
| 151 | .dynamic : { *(.dynamic*) } |
| 152 | .plt : { *(.plt*) } |
| 153 | .interp : { *(.interp*) } |
Andreas Färber | 2c67e0e | 2014-01-27 05:48:11 +0100 | [diff] [blame] | 154 | .gnu.hash : { *(.gnu.hash) } |
Albert ARIBAUD | 47ed5dd | 2013-11-07 14:21:46 +0100 | [diff] [blame] | 155 | .gnu : { *(.gnu*) } |
| 156 | .ARM.exidx : { *(.ARM.exidx*) } |
Albert ARIBAUD | b02bfc4 | 2014-01-13 14:57:05 +0100 | [diff] [blame] | 157 | .gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) } |
Simon Glass | dde3b70 | 2012-02-23 03:28:41 +0000 | [diff] [blame] | 158 | } |