blob: e148ab75137c1ed33f4879b09ac497a476bbb8ff [file] [log] [blame]
Simon Glassdde3b702012-02-23 03:28:41 +00001/*
2 * Copyright (c) 2004-2008 Texas Instruments
3 *
4 * (C) Copyright 2002
5 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Simon Glassdde3b702012-02-23 03:28:41 +00008 */
9
Marc Zyngierbf433af2014-07-12 14:24:02 +010010#include <config.h>
11
Simon Glassdde3b702012-02-23 03:28:41 +000012OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
13OUTPUT_ARCH(arm)
14ENTRY(_start)
15SECTIONS
16{
Wang Dongshengc5e954e2016-01-18 11:02:40 +080017#if defined(CONFIG_ARMV7_SECURE_BASE) && defined(CONFIG_ARMV7_NONSEC)
Peng Fand47cb0b2015-10-23 10:13:03 +080018 /*
Wang Dongshengc5e954e2016-01-18 11:02:40 +080019 * If CONFIG_ARMV7_SECURE_BASE is true, secure code will not
20 * bundle with u-boot, and code offsets are fixed. Secure zone
21 * only needs to be copied from the loading address to
22 * CONFIG_ARMV7_SECURE_BASE, which is the linking and running
23 * address for secure code.
Peng Fand47cb0b2015-10-23 10:13:03 +080024 *
Wang Dongshengc5e954e2016-01-18 11:02:40 +080025 * If CONFIG_ARMV7_SECURE_BASE is undefined, the secure zone will
26 * be included in u-boot address space, and some absolute address
27 * were used in secure code. The absolute addresses of the secure
28 * code also needs to be relocated along with the accompanying u-boot
29 * code.
30 *
31 * So DISCARD is only for CONFIG_ARMV7_SECURE_BASE.
Peng Fand47cb0b2015-10-23 10:13:03 +080032 */
33 /DISCARD/ : { *(.rel._secure*) }
Wang Dongshengc5e954e2016-01-18 11:02:40 +080034#endif
Simon Glassdde3b702012-02-23 03:28:41 +000035 . = 0x00000000;
36
37 . = ALIGN(4);
38 .text :
39 {
Albert ARIBAUDd026dec2013-06-11 14:17:33 +020040 *(.__image_copy_start)
Albert ARIBAUD41623c92014-04-15 16:13:51 +020041 *(.vectors)
Stephen Warrenb68d6712012-10-22 06:19:32 +000042 CPUDIR/start.o (.text*)
43 *(.text*)
Simon Glassdde3b702012-02-23 03:28:41 +000044 }
45
Jan Kiszka104d6fb2015-04-21 07:18:24 +020046#ifdef CONFIG_ARMV7_NONSEC
Marc Zyngierbf433af2014-07-12 14:24:02 +010047
48#ifndef CONFIG_ARMV7_SECURE_BASE
49#define CONFIG_ARMV7_SECURE_BASE
50#endif
51
52 .__secure_start : {
53 . = ALIGN(0x1000);
54 *(.__secure_start)
55 }
56
57 .secure_text CONFIG_ARMV7_SECURE_BASE :
58 AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
59 {
60 *(._secure.text)
61 }
62
63 . = LOADADDR(.__secure_start) +
64 SIZEOF(.__secure_start) +
65 SIZEOF(.secure_text);
66
67 __secure_end_lma = .;
68 .__secure_end : AT(__secure_end_lma) {
69 *(.__secure_end)
70 LONG(0x1d1071c); /* Must output something to reset LMA */
71 }
72#endif
73
Simon Glassdde3b702012-02-23 03:28:41 +000074 . = ALIGN(4);
75 .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
76
77 . = ALIGN(4);
78 .data : {
Stephen Warrenb68d6712012-10-22 06:19:32 +000079 *(.data*)
Simon Glassdde3b702012-02-23 03:28:41 +000080 }
81
82 . = ALIGN(4);
83
84 . = .;
Simon Glassdde3b702012-02-23 03:28:41 +000085
86 . = ALIGN(4);
Marek Vasut55675142012-10-12 10:27:03 +000087 .u_boot_list : {
Albert ARIBAUDef123c52013-02-25 00:59:00 +000088 KEEP(*(SORT(.u_boot_list*)));
Marek Vasut55675142012-10-12 10:27:03 +000089 }
90
91 . = ALIGN(4);
Simon Glassdde3b702012-02-23 03:28:41 +000092
Albert ARIBAUDd026dec2013-06-11 14:17:33 +020093 .image_copy_end :
94 {
95 *(.__image_copy_end)
96 }
Simon Glassdde3b702012-02-23 03:28:41 +000097
Albert ARIBAUD47bd65e2013-06-11 14:17:34 +020098 .rel_dyn_start :
99 {
100 *(.__rel_dyn_start)
101 }
102
Simon Glassdde3b702012-02-23 03:28:41 +0000103 .rel.dyn : {
Simon Glassdde3b702012-02-23 03:28:41 +0000104 *(.rel*)
Albert ARIBAUD47bd65e2013-06-11 14:17:34 +0200105 }
106
107 .rel_dyn_end :
108 {
109 *(.__rel_dyn_end)
Simon Glassdde3b702012-02-23 03:28:41 +0000110 }
111
Albert ARIBAUDd0b5d9d2014-02-22 17:53:42 +0100112 .end :
113 {
114 *(.__end)
115 }
116
117 _image_binary_end = .;
Simon Glassdde3b702012-02-23 03:28:41 +0000118
119 /*
120 * Deprecated: this MMU section is used by pxa at present but
121 * should not be used by new boards/CPUs.
122 */
123 . = ALIGN(4096);
124 .mmutable : {
125 *(.mmutable)
126 }
127
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +0000128/*
129 * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
130 * __bss_base and __bss_limit are for linker only (overlay ordering)
131 */
132
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +0000133 .bss_start __rel_dyn_start (OVERLAY) : {
134 KEEP(*(.__bss_start));
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +0000135 __bss_base = .;
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +0000136 }
137
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +0000138 .bss __bss_base (OVERLAY) : {
Stephen Warrenb68d6712012-10-22 06:19:32 +0000139 *(.bss*)
Simon Glassdde3b702012-02-23 03:28:41 +0000140 . = ALIGN(4);
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +0000141 __bss_limit = .;
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +0000142 }
Tom Rini0ce033d2013-03-18 12:31:00 -0400143
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +0000144 .bss_end __bss_limit (OVERLAY) : {
145 KEEP(*(.__bss_end));
Simon Glassdde3b702012-02-23 03:28:41 +0000146 }
147
Albert ARIBAUDd0b5d9d2014-02-22 17:53:42 +0100148 .dynsym _image_binary_end : { *(.dynsym) }
Albert ARIBAUD47ed5dd2013-11-07 14:21:46 +0100149 .dynbss : { *(.dynbss) }
150 .dynstr : { *(.dynstr*) }
151 .dynamic : { *(.dynamic*) }
152 .plt : { *(.plt*) }
153 .interp : { *(.interp*) }
Andreas Färber2c67e0e2014-01-27 05:48:11 +0100154 .gnu.hash : { *(.gnu.hash) }
Albert ARIBAUD47ed5dd2013-11-07 14:21:46 +0100155 .gnu : { *(.gnu*) }
156 .ARM.exidx : { *(.ARM.exidx*) }
Albert ARIBAUDb02bfc42014-01-13 14:57:05 +0100157 .gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) }
Simon Glassdde3b702012-02-23 03:28:41 +0000158}