Blame - arch/powerpc/include/asm/config.h - platform/external/u-boot

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Tom Rini	83d290c	2018-05-06 17:58:06 -0400	[diff] [blame]	1	/* SPDX-License-Identifier: GPL-2.0+ */
Kumar Gala	47d41cc	2009-02-05 20:40:57 -0600	[diff] [blame]	2	/*
Poonam Aggrwal	b8cdd01	2011-01-13 21:39:27 +0530	[diff] [blame]	3	* Copyright 2009-2011 Freescale Semiconductor, Inc.
Kumar Gala	47d41cc	2009-02-05 20:40:57 -0600	[diff] [blame]	4	*/
				5
				6	#ifndef _ASM_CONFIG_H_
				7	#define _ASM_CONFIG_H_
				8
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	9	#ifdef CONFIG_MPC85xx
				10	#include <asm/config_mpc85xx.h>
				11	#endif
				12
				13	#ifdef CONFIG_MPC86xx
				14	#include <asm/config_mpc86xx.h>
York Sun	5614e71	2013-09-30 09:22:09 -0700	[diff] [blame]	15	#endif
				16
				17	#ifdef CONFIG_MPC83xx
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	18	#endif
				19
York Sun	7ac3cc2	2012-08-17 09:00:54 +0000	[diff] [blame]	20	#ifndef HWCONFIG_BUFFER_SIZE
				21	#define HWCONFIG_BUFFER_SIZE 256
				22	#endif
				23
Mingkai Hu	273feaf	2011-04-26 16:31:16 +0800	[diff] [blame]	24	/* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */
				25	#if defined(CONFIG_MPC8XXX_SPI) \|\| defined(CONFIG_FSL_ESPI)
				26	# ifndef CONFIG_HARD_SPI
				27	# define CONFIG_HARD_SPI
				28	# endif
				29	#endif
				30
Mike Frysinger	a16028d	2009-11-03 11:35:59 -0500	[diff] [blame]	31	#define CONFIG_LMB
John Rigby	fca43cc	2010-10-13 13:57:35 -0600	[diff] [blame]	32	#define CONFIG_SYS_BOOT_RAMDISK_HIGH
Mike Frysinger	a16028d	2009-11-03 11:35:59 -0500	[diff] [blame]	33
Kumar Gala	87c9063	2009-02-05 20:40:58 -0600	[diff] [blame]	34	#ifndef CONFIG_MAX_MEM_MAPPED
Heiko Schocher	98f705c	2017-06-27 16:49:14 +0200	[diff] [blame]	35	#if defined(CONFIG_E500) \|\| \
York Sun	d29d17d	2011-08-26 11:32:44 -0700	[diff] [blame]	36	defined(CONFIG_MPC86xx) \|\| \
				37	defined(CONFIG_E300)
Kumar Gala	87c9063	2009-02-05 20:40:58 -0600	[diff] [blame]	38	#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
				39	#else
Stefan Roese	2ede879	2009-02-11 09:37:12 +0100	[diff] [blame]	40	#define CONFIG_MAX_MEM_MAPPED (256 << 20)
Kumar Gala	87c9063	2009-02-05 20:40:58 -0600	[diff] [blame]	41	#endif
				42	#endif
				43
Peter Tyser	f732a75	2009-07-15 00:01:08 -0500	[diff] [blame]	44	/* Check if boards need to enable FSL DMA engine for SDRAM init */
				45	#if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
				46	#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) \|\| \
				47	((defined(CONFIG_MPC85xx) \|\| defined(CONFIG_MPC86xx)) && \
				48	!defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
Peter Tyser	017f11f	2009-06-30 17:15:40 -0500	[diff] [blame]	49	#define CONFIG_FSL_DMA
Kumar Gala	47d41cc	2009-02-05 20:40:57 -0600	[diff] [blame]	50	#endif
Peter Tyser	017f11f	2009-06-30 17:15:40 -0500	[diff] [blame]	51	#endif
				52
Peter Tyser	5ccd29c	2009-10-23 15:55:47 -0500	[diff] [blame]	53	/*
				54	* Provide a default boot page translation virtual address that lines up with
				55	* Freescale's default e500 reset page.
				56	*/
				57	#if (defined(CONFIG_E500) && defined(CONFIG_MP))
				58	#ifndef CONFIG_BPTR_VIRT_ADDR
				59	#define CONFIG_BPTR_VIRT_ADDR 0xfffff000
				60	#endif
				61	#endif
				62
Becky Bruce	f51cdaf	2010-06-17 11:37:20 -0500	[diff] [blame]	63	/* Since so many PPC SOCs have a semi-common LBC, define this here */
				64	#if defined(CONFIG_MPC85xx) \|\| defined(CONFIG_MPC86xx) \|\| \
				65	defined(CONFIG_MPC83xx)
Dipen Dudhat	d789b5f	2011-01-20 16:29:35 +0530	[diff] [blame]	66	#if !defined(CONFIG_FSL_IFC)
Becky Bruce	f51cdaf	2010-06-17 11:37:20 -0500	[diff] [blame]	67	#define CONFIG_FSL_LBC
				68	#endif
Dipen Dudhat	d789b5f	2011-01-20 16:29:35 +0530	[diff] [blame]	69	#endif
Becky Bruce	f51cdaf	2010-06-17 11:37:20 -0500	[diff] [blame]	70
Andy Fleming	063c126	2011-04-08 02:10:54 -0500	[diff] [blame]	71	/* The TSEC driver uses the PHYLIB infrastructure */
Zhao Qiang	990d06b	2018-02-07 10:01:56 +0800	[diff] [blame]	72	#if defined(CONFIG_TSEC_ENET) && defined(CONFIG_PHYLIB)
Andy Fleming	063c126	2011-04-08 02:10:54 -0500	[diff] [blame]	73	#include <config_phylib_all_drivers.h>
				74	#endif /* TSEC_ENET */
Andy Fleming	063c126	2011-04-08 02:10:54 -0500	[diff] [blame]	75
Kumar Gala	c916d7c	2011-04-13 08:37:44 -0500	[diff] [blame]	76	/* The FMAN driver uses the PHYLIB infrastructure */
Kumar Gala	c916d7c	2011-04-13 08:37:44 -0500	[diff] [blame]	77
Albert Aribaud	f2a37fc	2010-08-08 05:17:05 +0530	[diff] [blame]	78	/* All PPC boards must swap IDE bytes */
				79	#define CONFIG_IDE_SWAP_IO
				80
Thomas Chou	f27445c	2015-11-19 21:48:07 +0800	[diff] [blame]	81	#if defined(CONFIG_DM_SERIAL)
				82	/*
				83	* TODO: Convert this to a clock driver exists that can give us the UART
				84	* clock here.
				85	*/
				86	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
				87	#endif
				88
Peter Tyser	017f11f	2009-06-30 17:15:40 -0500	[diff] [blame]	89	#endif /* _ASM_CONFIG_H_ */