blob: 275124830f511e66c76676fb659782a2a6d2212f [file] [log] [blame]
wdenk7aa78612003-05-03 15:50:43 +00001/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
37#define CONFIG_ATC 1 /* ...on a ATC board */
38
39/*
40 * select serial console configuration
41 *
42 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
43 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
44 * for SCC).
45 *
46 * if CONFIG_CONS_NONE is defined, then the serial console routines must
47 * defined elsewhere (for example, on the cogent platform, there are serial
48 * ports on the motherboard which are used for the serial console - see
49 * cogent/cma101/serial.[ch]).
50 */
51#define CONFIG_CONS_ON_SMC /* define if console on SMC */
52#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
53#undef CONFIG_CONS_NONE /* define if console on something else*/
54#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
55
56#define CONFIG_BAUDRATE 115200
57
58/*
59 * select ethernet configuration
60 *
61 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
62 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
63 * for FCC)
64 *
65 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
66 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
67 * from CONFIG_COMMANDS to remove support for networking.
68 *
69 */
70#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
71#undef CONFIG_ETHER_NONE /* define if ether on something else */
72#define CONFIG_ETHER_ON_FCC
73
74#define CONFIG_NET_MULTI
75#define CONFIG_ETHER_ON_FCC2
76
77/*
78 * - Rx-CLK is CLK13
79 * - Tx-CLK is CLK14
80 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
81 * - Enable Full Duplex in FSMR
82 */
83# define CFG_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
84# define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
85# define CFG_CPMFCR_RAMTYPE 0
86# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
87
88#define CONFIG_ETHER_ON_FCC3
89
90/*
91 * - Rx-CLK is CLK15
92 * - Tx-CLK is CLK16
93 * - RAM for BD/Buffers is on the local Bus (see 28-13)
94 * - Enable Half Duplex in FSMR
95 */
96# define CFG_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
97# define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
98
99/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
100#define CONFIG_8260_CLKIN 64000000 /* in Hz */
101
102#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
103
104#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in Hz */
105
106#define CONFIG_PREBOOT \
107 "echo;" \
108 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;"\
109 "echo"
110
111#undef CONFIG_BOOTARGS
112#define CONFIG_BOOTCOMMAND \
113 "bootp;" \
114 "setenv bootargs root=/dev/nfs rw " \
115 "nfsroot=$(serverip):$(rootpath) " \
116 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"\
117 "bootm"
118
119/*-----------------------------------------------------------------------
120 * Miscellaneous configuration options
121 */
122
123#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
124#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
125
126#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
127
wdenk66fd3d12003-05-18 11:30:09 +0000128#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
129 CFG_CMD_EEPROM | \
130 CFG_CMD_PCI | \
131 CFG_CMD_PCMCIA | \
wdenk15ef8a52003-06-18 20:22:24 +0000132 CFG_CMD_DATE | \
wdenk66fd3d12003-05-18 11:30:09 +0000133 CFG_CMD_IDE)
wdenk15ef8a52003-06-18 20:22:24 +0000134
135
wdenk66fd3d12003-05-18 11:30:09 +0000136#define CONFIG_DOS_PARTITION
wdenk7aa78612003-05-03 15:50:43 +0000137
138/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
139#include <cmd_confdefs.h>
140
141/*
142 * Miscellaneous configurable options
143 */
144#define CFG_LONGHELP /* undef to save memory */
145#define CFG_PROMPT "=> " /* Monitor Command Prompt */
146#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
147#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
148#else
149#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
150#endif
151#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
152#define CFG_MAXARGS 16 /* max number of command args */
153#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
154
155#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
156#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
157
158#define CFG_LOAD_ADDR 0x100000 /* default load address */
159
wdenk66fd3d12003-05-18 11:30:09 +0000160#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
161
wdenk7aa78612003-05-03 15:50:43 +0000162#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
163
164#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
165
166#define CFG_RESET_ADDRESS 0xFFF00100 /* "bad" address */
167
168#define CFG_ALLOC_DPRAM
169
170#undef CONFIG_WATCHDOG /* watchdog disabled */
171
172#define CONFIG_SPI
173
wdenk15ef8a52003-06-18 20:22:24 +0000174#define CONFIG_RTC_DS12887
175
wdenk9a0e21a2003-06-22 10:30:54 +0000176#define RTC_BASE_ADDR 0xF5000000
wdenk15ef8a52003-06-18 20:22:24 +0000177#define RTC_PORT_ADDR RTC_BASE_ADDR + 0x800
178#define RTC_PORT_DATA RTC_BASE_ADDR + 0x808
179
180#define CONFIG_MISC_INIT_R
181
wdenk7aa78612003-05-03 15:50:43 +0000182/*
183 * For booting Linux, the board info and command line data
184 * have to be in the first 8 MB of memory, since this is
185 * the maximum mapped by the Linux kernel during initialization.
186 */
187#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
188
189/*-----------------------------------------------------------------------
190 * Flash configuration
191 */
192
wdenk7aa78612003-05-03 15:50:43 +0000193#define CFG_FLASH_BASE 0xFF000000
194#define CFG_FLASH_SIZE 0x00800000
195
196/*-----------------------------------------------------------------------
197 * FLASH organization
198 */
199#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
200#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
201
202#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
203#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
204
205#define CONFIG_FLASH_16BIT
206
207/*-----------------------------------------------------------------------
208 * Hard Reset Configuration Words
209 *
210 * if you change bits in the HRCW, you must also change the CFG_*
211 * defines for the various registers affected by the HRCW e.g. changing
212 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
213 */
214#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
wdenk9a0e21a2003-06-22 10:30:54 +0000215 HRCW_BPS10 |\
wdenk7aa78612003-05-03 15:50:43 +0000216 HRCW_APPC10)
217
218/* no slaves so just fill with zeros */
219#define CFG_HRCW_SLAVE1 0
220#define CFG_HRCW_SLAVE2 0
221#define CFG_HRCW_SLAVE3 0
222#define CFG_HRCW_SLAVE4 0
223#define CFG_HRCW_SLAVE5 0
224#define CFG_HRCW_SLAVE6 0
225#define CFG_HRCW_SLAVE7 0
226
227/*-----------------------------------------------------------------------
228 * Internal Memory Mapped Register
229 */
230#define CFG_IMMR 0xF0000000
231
232/*-----------------------------------------------------------------------
233 * Definitions for initial stack pointer and data area (in DPRAM)
234 */
235#define CFG_INIT_RAM_ADDR CFG_IMMR
236#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
237#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
238#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
239#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
240
241/*-----------------------------------------------------------------------
242 * Start addresses for the final memory configuration
243 * (Set up by the startup code)
244 * Please note that CFG_SDRAM_BASE _must_ start at 0
245 *
246 * 60x SDRAM is mapped at CFG_SDRAM_BASE.
247 */
248#define CFG_SDRAM_BASE 0x00000000
249#define CFG_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
250#define CFG_MONITOR_BASE TEXT_BASE
wdenke6009622003-05-05 17:09:41 +0000251#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
wdenk7aa78612003-05-03 15:50:43 +0000252#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
253
254#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
255# define CFG_RAMBOOT
256#endif
257
wdenk66fd3d12003-05-18 11:30:09 +0000258#define CONFIG_PCI
259#define CONFIG_PCI_PNP
wdenk5d232d02003-05-22 22:52:13 +0000260#define CFG_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
wdenk66fd3d12003-05-18 11:30:09 +0000261
wdenk7aa78612003-05-03 15:50:43 +0000262#if 1
263/* environment is in Flash */
264#define CFG_ENV_IS_IN_FLASH 1
wdenke6009622003-05-05 17:09:41 +0000265# define CFG_ENV_ADDR (CFG_FLASH_BASE+0x30000)
wdenk7aa78612003-05-03 15:50:43 +0000266# define CFG_ENV_SIZE 0x10000
267# define CFG_ENV_SECT_SIZE 0x10000
268#else
269#define CFG_ENV_IS_IN_EEPROM 1
270#define CFG_ENV_OFFSET 0
271#define CFG_ENV_SIZE 2048
272#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
273#endif
274/*
275 * Internal Definitions
276 *
277 * Boot Flags
278 */
279#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
280#define BOOTFLAG_WARM 0x02 /* Software reboot */
281
282
283/*-----------------------------------------------------------------------
284 * Cache Configuration
285 */
286#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
287#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
288# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
289#endif
290
291/*-----------------------------------------------------------------------
292 * HIDx - Hardware Implementation-dependent Registers 2-11
293 *-----------------------------------------------------------------------
294 * HID0 also contains cache control - initially enable both caches and
295 * invalidate contents, then the final state leaves only the instruction
296 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
297 * but Soft reset does not.
298 *
299 * HID1 has only read-only information - nothing to set.
300 */
301#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\
wdenk8bde7f72003-06-27 21:31:46 +0000302 HID0_DCI|HID0_IFEM|HID0_ABE)
wdenk7aa78612003-05-03 15:50:43 +0000303#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
304#define CFG_HID2 0
305
306/*-----------------------------------------------------------------------
307 * RMR - Reset Mode Register 5-5
308 *-----------------------------------------------------------------------
309 * turn on Checkstop Reset Enable
310 */
311#define CFG_RMR RMR_CSRE
312
313/*-----------------------------------------------------------------------
314 * BCR - Bus Configuration 4-25
315 *-----------------------------------------------------------------------
316 */
317#define BCR_APD01 0x10000000
318#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
319
320/*-----------------------------------------------------------------------
321 * SIUMCR - SIU Module Configuration 4-31
322 *-----------------------------------------------------------------------
323 */
wdenk9a0e21a2003-06-22 10:30:54 +0000324#define CFG_SIUMCR (SIUMCR_BBD|SIUMCR_APPC10|\
wdenk7aa78612003-05-03 15:50:43 +0000325 SIUMCR_CS10PC00|SIUMCR_BCTLC10)
326
327/*-----------------------------------------------------------------------
328 * SYPCR - System Protection Control 4-35
329 * SYPCR can only be written once after reset!
330 *-----------------------------------------------------------------------
331 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
332 */
333#if defined(CONFIG_WATCHDOG)
334#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk8bde7f72003-06-27 21:31:46 +0000335 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
wdenk7aa78612003-05-03 15:50:43 +0000336#else
337#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk8bde7f72003-06-27 21:31:46 +0000338 SYPCR_SWRI|SYPCR_SWP)
wdenk7aa78612003-05-03 15:50:43 +0000339#endif /* CONFIG_WATCHDOG */
340
341/*-----------------------------------------------------------------------
342 * TMCNTSC - Time Counter Status and Control 4-40
343 *-----------------------------------------------------------------------
344 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
345 * and enable Time Counter
346 */
347#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
348
349/*-----------------------------------------------------------------------
350 * PISCR - Periodic Interrupt Status and Control 4-42
351 *-----------------------------------------------------------------------
352 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
353 * Periodic timer
354 */
355#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
356
357/*-----------------------------------------------------------------------
358 * SCCR - System Clock Control 9-8
359 *-----------------------------------------------------------------------
360 * Ensure DFBRG is Divide by 16
361 */
362#define CFG_SCCR SCCR_DFBRG01
363
364/*-----------------------------------------------------------------------
365 * RCCR - RISC Controller Configuration 13-7
366 *-----------------------------------------------------------------------
367 */
368#define CFG_RCCR 0
369
370#define CFG_MIN_AM_MASK 0xC0000000
371/*-----------------------------------------------------------------------
372 * MPTPR - Memory Refresh Timer Prescaler Register 10-18
373 *-----------------------------------------------------------------------
374 */
375#define CFG_MPTPR 0x1F00
376
377/*-----------------------------------------------------------------------
378 * PSRT - Refresh Timer Register 10-16
379 *-----------------------------------------------------------------------
380 */
381#define CFG_PSRT 0x0f
382
383/*-----------------------------------------------------------------------
384 * PSRT - SDRAM Mode Register 10-10
385 *-----------------------------------------------------------------------
386 */
387
388 /* SDRAM initialization values for 8-column chips
389 */
390#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\
391 ORxS_BPD_4 |\
wdenkf7de16a2003-05-12 09:51:52 +0000392 ORxS_ROWST_PBI1_A7 |\
393 ORxS_NUMR_12)
wdenk7aa78612003-05-03 15:50:43 +0000394
wdenkf7de16a2003-05-12 09:51:52 +0000395#define CFG_PSDMR_8COL (PSDMR_PBI |\
396 PSDMR_SDAM_A15_IS_A5 |\
397 PSDMR_BSMA_A15_A17 |\
398 PSDMR_SDA10_PBI1_A7 |\
wdenk7aa78612003-05-03 15:50:43 +0000399 PSDMR_RFRC_7_CLK |\
wdenkf7de16a2003-05-12 09:51:52 +0000400 PSDMR_PRETOACT_3W |\
401 PSDMR_ACTTORW_2W |\
wdenk7aa78612003-05-03 15:50:43 +0000402 PSDMR_LDOTOPRE_1C |\
403 PSDMR_WRC_1C |\
404 PSDMR_CL_2)
405
406 /* SDRAM initialization values for 9-column chips
407 */
408#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\
409 ORxS_BPD_4 |\
wdenkf7de16a2003-05-12 09:51:52 +0000410 ORxS_ROWST_PBI1_A6 |\
411 ORxS_NUMR_12)
wdenk7aa78612003-05-03 15:50:43 +0000412
wdenkf7de16a2003-05-12 09:51:52 +0000413#define CFG_PSDMR_9COL (PSDMR_PBI |\
414 PSDMR_SDAM_A16_IS_A5 |\
415 PSDMR_BSMA_A15_A17 |\
416 PSDMR_SDA10_PBI1_A6 |\
wdenk7aa78612003-05-03 15:50:43 +0000417 PSDMR_RFRC_7_CLK |\
wdenkf7de16a2003-05-12 09:51:52 +0000418 PSDMR_PRETOACT_3W |\
419 PSDMR_ACTTORW_2W |\
wdenk7aa78612003-05-03 15:50:43 +0000420 PSDMR_LDOTOPRE_1C |\
421 PSDMR_WRC_1C |\
422 PSDMR_CL_2)
423
424/*
425 * Init Memory Controller:
426 *
427 * Bank Bus Machine PortSz Device
428 * ---- --- ------- ------ ------
429 * 0 60x GPCM 8 bit Boot ROM
430 * 1 60x GPCM 64 bit FLASH
431 * 2 60x SDRAM 64 bit SDRAM
432 *
433 */
434
435#define CFG_MRS_OFFS 0x00000000
436
437/* Bank 0 - FLASH
438 */
439#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000440 BRx_PS_16 |\
441 BRx_MS_GPCM_P |\
442 BRx_V)
wdenk7aa78612003-05-03 15:50:43 +0000443
444#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000445 ORxG_CSNT |\
446 ORxG_ACS_DIV1 |\
447 ORxG_SCY_3_CLK |\
448 ORxU_EHTR_8IDLE)
wdenk7aa78612003-05-03 15:50:43 +0000449
450
451/* Bank 2 - 60x bus SDRAM
452 */
453#ifndef CFG_RAMBOOT
454#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000455 BRx_PS_64 |\
456 BRx_MS_SDRAM_P |\
457 BRx_V)
wdenk7aa78612003-05-03 15:50:43 +0000458
459#define CFG_OR2_PRELIM CFG_OR2_8COL
460
461#define CFG_PSDMR CFG_PSDMR_8COL
462#endif /* CFG_RAMBOOT */
463
wdenk15ef8a52003-06-18 20:22:24 +0000464#define CFG_BR4_PRELIM ((RTC_BASE_ADDR & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000465 BRx_PS_8 |\
466 BRx_MS_UPMA |\
467 BRx_V)
wdenk15ef8a52003-06-18 20:22:24 +0000468
469#define CFG_OR4_PRELIM (ORxU_AM_MSK | ORxU_BI)
wdenk8bde7f72003-06-27 21:31:46 +0000470
wdenk66fd3d12003-05-18 11:30:09 +0000471/*-----------------------------------------------------------------------
472 * PCMCIA stuff
473 *-----------------------------------------------------------------------
474 *
475 */
476#define CONFIG_I82365
477
478#define CFG_PCMCIA_MEM_ADDR 0x81000000
479#define CFG_PCMCIA_MEM_SIZE 0x1000
480
481/*-----------------------------------------------------------------------
482 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
483 *-----------------------------------------------------------------------
484 */
485
486#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
487
488#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
489#undef CONFIG_IDE_LED /* LED for ide not supported */
490#undef CONFIG_IDE_RESET /* reset for ide not supported */
491
492#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
493#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
494
495#define CFG_ATA_IDE0_OFFSET 0x0000
496
497#define CFG_ATA_BASE_ADDR 0xa0000000
498
499/* Offset for data I/O */
500#define CFG_ATA_DATA_OFFSET 0x100
501
502/* Offset for normal register accesses */
503#define CFG_ATA_REG_OFFSET 0x100
504
505/* Offset for alternate registers */
506#define CFG_ATA_ALT_OFFSET 0x108
507
wdenk7aa78612003-05-03 15:50:43 +0000508#endif /* __CONFIG_H */