Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / c163668a4abaeef3eaab22b4a5ac13d2d74f1306 / . / configs / tinker-rk3288_defconfig
blob: 00e2d819543403c97d500ed9374d034e2ce91e95 [file] [log] [blame]
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_ROCKCHIP=y
3CONFIG_SYS_MALLOC_F_LEN=0x2000
4CONFIG_ROCKCHIP_RK3288=y
Philipp Tomsichee14d292017-06-29 11:21:15 +0200[diff] [blame]5CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
Eddie Cai6f279762017-01-18 11:03:54 +0800[diff] [blame]6CONFIG_TARGET_TINKER_RK3288=y
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]7CONFIG_SPL_STACK_R_ADDR=0x80000
Eddie Cai6f279762017-01-18 11:03:54 +0800[diff] [blame]8CONFIG_DEFAULT_DEVICE_TREE="rk3288-tinker"
Tom Rinifb82fe32017-06-19 09:47:40 -0400[diff] [blame]9CONFIG_DEBUG_UART=y
Tom Rini48f62322017-08-25 17:50:27 -0400[diff] [blame]10# CONFIG_ANDROID_BOOT_IMAGE is not set
Simon Glass98af8792016-10-17 20:12:35 -0600[diff] [blame]11CONFIG_SILENT_CONSOLE=y
Simon Glassef26d602016-10-17 20:12:37 -0600[diff] [blame]12CONFIG_CONSOLE_MUX=y
13# CONFIG_DISPLAY_CPUINFO is not set
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]14CONFIG_SPL_STACK_R=y
15CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Jonas Karlmanecc3bd72017-04-22 08:57:54 +0000[diff] [blame]16CONFIG_SPL_I2C_SUPPORT=y
Tom Rini48f62322017-08-25 17:50:27 -0400[diff] [blame]17CONFIG_FASTBOOT_FLASH=y
18CONFIG_FASTBOOT_FLASH_MMC_DEV=0
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]19# CONFIG_CMD_IMLS is not set
Tom Rini88663122017-08-14 19:58:53 -0400[diff] [blame]20CONFIG_CMD_GPIO=y
Patrick Delaunayb331cd62017-01-27 11:00:42 +0100[diff] [blame]21CONFIG_CMD_GPT=y
Tom Rini88663122017-08-14 19:58:53 -0400[diff] [blame]22CONFIG_CMD_I2C=y
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]23CONFIG_CMD_MMC=y
24CONFIG_CMD_SF=y
25CONFIG_CMD_SPI=y
Eddie Caic00d1652017-03-07 12:47:07 +0800[diff] [blame]26CONFIG_CMD_USB=y
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]27# CONFIG_CMD_SETEXPR is not set
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]28CONFIG_CMD_CACHE=y
29CONFIG_CMD_TIME=y
30CONFIG_CMD_PMIC=y
31CONFIG_CMD_REGULATOR=y
Patrick Delaunayb0cf7332017-01-27 11:00:37 +0100[diff] [blame]32# CONFIG_SPL_DOS_PARTITION is not set
Patrick Delaunay1acc0082017-01-27 11:00:38 +0100[diff] [blame]33# CONFIG_SPL_ISO_PARTITION is not set
Patrick Delaunaybd42a942017-01-27 11:00:41 +0100[diff] [blame]34# CONFIG_SPL_EFI_PARTITION is not set
Patrick Delaunayb331cd62017-01-27 11:00:42 +0100[diff] [blame]35CONFIG_SPL_PARTITION_UUIDS=y
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]36CONFIG_SPL_OF_CONTROL=y
37CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Tom Rini5dc4dfd2017-08-28 07:16:32 -0400[diff] [blame]38CONFIG_ENV_IS_IN_MMC=y
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]39CONFIG_REGMAP=y
40CONFIG_SPL_REGMAP=y
41CONFIG_SYSCON=y
42CONFIG_SPL_SYSCON=y
43# CONFIG_SPL_SIMPLE_BUS is not set
44CONFIG_CLK=y
45CONFIG_SPL_CLK=y
46CONFIG_ROCKCHIP_GPIO=y
47CONFIG_SYS_I2C_ROCKCHIP=y
Jonas Karlmanecc3bd72017-04-22 08:57:54 +0000[diff] [blame]48CONFIG_MISC=y
49CONFIG_I2C_EEPROM=y
Masahiro Yamada55ed3b42017-01-10 13:32:04 +0900[diff] [blame]50CONFIG_MMC_DW=y
Masahiro Yamadafed44082017-01-10 13:32:03 +0900[diff] [blame]51CONFIG_MMC_DW_ROCKCHIP=y
Jacob Chen5c0206c2017-02-23 14:20:17 +0800[diff] [blame]52CONFIG_DM_ETH=y
Jacob Chen5c0206c2017-02-23 14:20:17 +0800[diff] [blame]53CONFIG_ETH_DESIGNWARE=y
54CONFIG_GMAC_ROCKCHIP=y
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]55CONFIG_PINCTRL=y
56CONFIG_SPL_PINCTRL=y
57# CONFIG_SPL_PINCTRL_FULL is not set
Philipp Tomsich51c7f342017-04-19 16:46:37 +0200[diff] [blame]58CONFIG_PINCTRL_ROCKCHIP_RK3288=y
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]59CONFIG_DM_PMIC=y
Jacob Chen453c5a92017-05-02 14:54:52 +0800[diff] [blame]60CONFIG_PMIC_RK8XX=y
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]61CONFIG_DM_REGULATOR_FIXED=y
Jacob Chen453c5a92017-05-02 14:54:52 +0800[diff] [blame]62CONFIG_REGULATOR_RK8XX=y
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]63CONFIG_PWM_ROCKCHIP=y
64CONFIG_RAM=y
65CONFIG_SPL_RAM=y
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]66CONFIG_DEBUG_UART_BASE=0xff690000
67CONFIG_DEBUG_UART_CLOCK=24000000
68CONFIG_DEBUG_UART_SHIFT=2
69CONFIG_SYS_NS16550=y
Tom Riniaca5cd22016-09-08 16:11:59 -0400[diff] [blame]70CONFIG_SYSRESET=y
Eddie Caic00d1652017-03-07 12:47:07 +0800[diff] [blame]71CONFIG_USB=y
Philipp Tomsich4ac72f52017-07-03 18:30:06 +0200[diff] [blame]72CONFIG_USB_DWC2=y
Eddie Caic00d1652017-03-07 12:47:07 +0800[diff] [blame]73CONFIG_USB_STORAGE=y
Tom Riniecad7052017-08-25 17:50:26 -0400[diff] [blame]74CONFIG_USB_GADGET=y
75CONFIG_USB_GADGET_DWC2_OTG=y
76CONFIG_USB_GADGET_DOWNLOAD=y
77CONFIG_G_DNL_MANUFACTURER="Rockchip"
78CONFIG_G_DNL_VENDOR_NUM=0x2207
79CONFIG_G_DNL_PRODUCT_NUM=0x320a
Chris Packhamae358442017-08-28 20:50:45 +1200[diff] [blame]80CONFIG_USB_HOST_ETHER=y
Chris Packhamf58ad982017-08-28 20:50:46 +1200[diff] [blame]81CONFIG_USB_ETHER_ASIX=y
82CONFIG_USB_ETHER_SMSC95XX=y
Xu Ziyuan1c62d992016-08-01 08:46:19 +0800[diff] [blame]83CONFIG_USE_TINY_PRINTF=y
84CONFIG_CMD_DHRYSTONE=y
85CONFIG_ERRNO_STR=y