blob: b60a9ade15a130e9975cb1b957327a358779fbac [file] [log] [blame]
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +02001/*
2 * (C) Copyright 2007-2008
Stelian Popc9e798d2011-11-01 00:00:39 +01003 * Stelian Pop <stelian@popies.net>
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +02004 * Lead Tech Design <www.leadtechdesign.com>
5 * Ilko Iliev <www.ronetix.at>
6 *
7 * Configuation settings for the RONETIX PM9263 board.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
Asen Dimov684a5672011-06-08 22:01:16 +000031/*
32 * SoC must be defined first, before hardware.h is included.
33 * In this case SoC is defined in boards.cfg.
34 */
35#include <asm/hardware.h>
36
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020037/* ARM asynchronous clock */
Jean-Christophe PLAGNIOL-VILLARDb2403582009-05-31 14:53:18 +020038#define CONFIG_DISPLAY_CPUINFO
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020039#define CONFIG_DISPLAY_BOARDINFO
40
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020041#define MASTER_PLL_DIV 6
42#define MASTER_PLL_MUL 65
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020043#define MAIN_PLL_DIV 2 /* 2 or 4 */
Achim Ehrlich7c966a82010-02-24 10:29:16 +010044#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
Asen Dimov684a5672011-06-08 22:01:16 +000045#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020046
Jean-Christophe PLAGNIOL-VILLARD6ebff362009-04-16 21:30:48 +020047#define CONFIG_SYS_HZ 1000
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020048
Asen Dimov684a5672011-06-08 22:01:16 +000049#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263"
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020050#define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */
51#define CONFIG_ARCH_CPU_INIT
Asen Dimov9a2a05a2010-12-12 12:41:59 +020052#define CONFIG_SYS_TEXT_BASE 0
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020053
Asen Dimova3e09cc2011-10-31 08:54:20 +000054#define MACH_TYPE_PM9263 1475
55#define CONFIG_MACH_TYPE MACH_TYPE_PM9263
56
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020057/* clocks */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020058#define CONFIG_SYS_MOR_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +030059 (AT91_PMC_MOR_MOSCEN | \
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020060 (255 << 8)) /* Main Oscillator Start-up Time */
61#define CONFIG_SYS_PLLAR_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +030062 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
63 AT91_PMC_PLLXR_OUT(3) | \
64 AT91_PMC_PLLXR_PLLCOUNT(0x3f) | /* PLL Counter */\
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020065 (2 << 28) | /* PLL Clock Frequency Range */ \
66 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020067
68#if (MAIN_PLL_DIV == 2)
69/* PCK/2 = MCK Master Clock from PLLA */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020070#define CONFIG_SYS_MCKR1_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +030071 (AT91_PMC_MCKR_CSS_SLOW | \
72 AT91_PMC_MCKR_PRES_1 | \
73 AT91_PMC_MCKR_MDIV_2)
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020074/* PCK/2 = MCK Master Clock from PLLA */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020075#define CONFIG_SYS_MCKR2_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +030076 (AT91_PMC_MCKR_CSS_PLLA | \
77 AT91_PMC_MCKR_PRES_1 | \
78 AT91_PMC_MCKR_MDIV_2)
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020079#else
80/* PCK/4 = MCK Master Clock from PLLA */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020081#define CONFIG_SYS_MCKR1_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +030082 (AT91_PMC_MCKR_CSS_SLOW | \
83 AT91_PMC_MCKR_PRES_1 | \
84 AT91_PMC_MCKR_MDIV_4)
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020085/* PCK/4 = MCK Master Clock from PLLA */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020086#define CONFIG_SYS_MCKR2_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +030087 (AT91_PMC_MCKR_CSS_PLLA | \
88 AT91_PMC_MCKR_PRES_1 | \
89 AT91_PMC_MCKR_MDIV_4)
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020090#endif
91/* define PDC[31:16] as DATA[31:16] */
92#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
93/* no pull-up for D[31:16] */
94#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
95/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020096#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +030097 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
98 AT91_MATRIX_CSA_EBI_CS1A)
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020099
100/* SDRAM */
101/* SDRAMC_MR Mode register */
102#define CONFIG_SYS_SDRC_MR_VAL1 0
103/* SDRAMC_TR - Refresh Timer register */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200104#define CONFIG_SYS_SDRC_TR_VAL1 0x3AA
105/* SDRAMC_CR - Configuration register*/
106#define CONFIG_SYS_SDRC_CR_VAL \
107 (AT91_SDRAMC_NC_9 | \
108 AT91_SDRAMC_NR_13 | \
109 AT91_SDRAMC_NB_4 | \
110 AT91_SDRAMC_CAS_2 | \
111 AT91_SDRAMC_DBW_32 | \
112 (2 << 8) | /* tWR - Write Recovery Delay */ \
113 (7 << 12) | /* tRC - Row Cycle Delay */ \
114 (2 << 16) | /* tRP - Row Precharge Delay */ \
115 (2 << 20) | /* tRCD - Row to Column Delay */ \
116 (5 << 24) | /* tRAS - Active to Precharge Delay */ \
117 (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */
118
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200119/* Memory Device Register -> SDRAM */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200120#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
121#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200122#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200123#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200124#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
125#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
126#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
127#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
128#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
129#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
130#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
131#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200132#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200133#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200134#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200135#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
136#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
137#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
138
139/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200140#define CONFIG_SYS_SMC0_SETUP0_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +0300141 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
142 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200143#define CONFIG_SYS_SMC0_PULSE0_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +0300144 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
145 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200146#define CONFIG_SYS_SMC0_CYCLE0_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +0300147 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200148#define CONFIG_SYS_SMC0_MODE0_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +0300149 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
150 AT91_SMC_MODE_DBW_16 | \
151 AT91_SMC_MODE_TDF | \
152 AT91_SMC_MODE_TDF_CYCLE(6))
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200153
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200154/* user reset enable */
155#define CONFIG_SYS_RSTC_RMR_VAL \
156 (AT91_RSTC_KEY | \
Asen Dimov20d98c22010-04-19 14:18:43 +0300157 AT91_RSTC_CR_PROCRST | \
158 AT91_RSTC_MR_ERSTL(1) | \
159 AT91_RSTC_MR_ERSTL(2))
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200160
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200161/* Disable Watchdog */
162#define CONFIG_SYS_WDTC_WDMR_VAL \
Asen Dimov20d98c22010-04-19 14:18:43 +0300163 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
164 AT91_WDT_MR_WDV(0xfff) | \
165 AT91_WDT_MR_WDDIS | \
166 AT91_WDT_MR_WDD(0xfff))
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200167
168#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
169#define CONFIG_SETUP_MEMORY_TAGS 1
170#define CONFIG_INITRD_TAG 1
171
172#undef CONFIG_SKIP_LOWLEVEL_INIT
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200173#define CONFIG_USER_LOWLEVEL_INIT 1
Asen Dimov52b26012011-12-09 10:56:55 +0000174#define CONFIG_BOARD_EARLY_INIT_F
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200175
176/*
177 * Hardware drivers
178 */
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100179#define CONFIG_AT91_GPIO 1
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200180#define CONFIG_ATMEL_USART 1
Asen Dimov684a5672011-06-08 22:01:16 +0000181#define CONFIG_USART_BASE ATMEL_BASE_DBGU
182#define CONFIG_USART_ID ATMEL_ID_SYS
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200183
184/* LCD */
185#define CONFIG_LCD 1
186#define LCD_BPP LCD_COLOR8
187#define CONFIG_LCD_LOGO 1
188#undef LCD_TEST_PATTERN
189#define CONFIG_LCD_INFO 1
190#define CONFIG_LCD_INFO_BELOW_LOGO 1
191#define CONFIG_SYS_WHITE_ON_BLACK 1
192#define CONFIG_ATMEL_LCD 1
193#define CONFIG_ATMEL_LCD_BGR555 1
194#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
195
196#define CONFIG_LCD_IN_PSRAM 1
197
198/* LED */
199#define CONFIG_AT91_LED
Asen Dimov20d98c22010-04-19 14:18:43 +0300200#define CONFIG_RED_LED AT91_PIO_PORTB, 7 /* this is the power led */
201#define CONFIG_GREEN_LED AT91_PIO_PORTB, 8 /* this is the user1 led */
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200202
203#define CONFIG_BOOTDELAY 3
204
205/*
206 * BOOTP options
207 */
208#define CONFIG_BOOTP_BOOTFILESIZE 1
209#define CONFIG_BOOTP_BOOTPATH 1
210#define CONFIG_BOOTP_GATEWAY 1
211#define CONFIG_BOOTP_HOSTNAME 1
212
213/*
214 * Command line configuration.
215 */
216#include <config_cmd_default.h>
217#undef CONFIG_CMD_BDI
218#undef CONFIG_CMD_IMI
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200219#undef CONFIG_CMD_FPGA
220#undef CONFIG_CMD_LOADS
221#undef CONFIG_CMD_IMLS
222
Asen Dimov6e110d22010-12-12 12:42:09 +0200223#define CONFIG_CMD_CACHE
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200224#define CONFIG_CMD_PING 1
225#define CONFIG_CMD_DHCP 1
226#define CONFIG_CMD_NAND 1
227#define CONFIG_CMD_USB 1
228
229/* SDRAM */
230#define CONFIG_NR_DRAM_BANKS 1
231#define PHYS_SDRAM 0x20000000
232#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
233
234/* DataFlash */
235#define CONFIG_ATMEL_DATAFLASH_SPI
236#define CONFIG_HAS_DATAFLASH 1
237#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
238#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
239#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
240#define AT91_SPI_CLK 15000000
241#define DATAFLASH_TCSS (0x1a << 16)
242#define DATAFLASH_TCHS (0x1 << 24)
243
244/* NOR flash, if populated */
245#define CONFIG_SYS_FLASH_CFI 1
246#define CONFIG_FLASH_CFI_DRIVER 1
247#define PHYS_FLASH_1 0x10000000
248#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
249#define CONFIG_SYS_MAX_FLASH_SECT 256
250#define CONFIG_SYS_MAX_FLASH_BANKS 1
251
252/* NAND flash */
253#ifdef CONFIG_CMD_NAND
254#define CONFIG_NAND_ATMEL
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200255#define CONFIG_SYS_MAX_NAND_DEVICE 1
256#define CONFIG_SYS_NAND_BASE 0x40000000
257#define CONFIG_SYS_NAND_DBW_8 1
258/* our ALE is AD21 */
259#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
260/* our CLE is AD22 */
261#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Asen Dimov20d98c22010-04-19 14:18:43 +0300262#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15
263#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTB, 30
Wolfgang Denk2eb99ca2009-07-18 21:52:24 +0200264
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200265#endif
266
267#define CONFIG_CMD_JFFS2 1
268#define CONFIG_JFFS2_CMDLINE 1
269#define CONFIG_JFFS2_NAND 1
270#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
271#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
272#define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/
273
274/* PSRAM */
275#define PHYS_PSRAM 0x70000000
276#define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */
Asen Dimov20d98c22010-04-19 14:18:43 +0300277/* Slave EBI1, PSRAM connected */
278#define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY | \
279 AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) | \
280 AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED | \
281 AT91_MATRIX_SCFG_SLOT_CYCLE(255))
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200282
283/* Ethernet */
284#define CONFIG_MACB 1
285#define CONFIG_RMII 1
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200286#define CONFIG_NET_RETRY_COUNT 20
287#define CONFIG_RESET_PHY_R 1
288
289/* USB */
290#define CONFIG_USB_ATMEL
291#define CONFIG_USB_OHCI_NEW 1
292#define CONFIG_DOS_PARTITION 1
293#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
294#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
295#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
296#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
297#define CONFIG_USB_STORAGE 1
298
299#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
300
301#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
302#define CONFIG_SYS_MEMTEST_END 0x23e00000
303
304#define CONFIG_SYS_USE_FLASH 1
305#undef CONFIG_SYS_USE_DATAFLASH
306#undef CONFIG_SYS_USE_NANDFLASH
307
308#ifdef CONFIG_SYS_USE_DATAFLASH
309
310/* bootstrap + u-boot + env + linux in dataflash on CS0 */
311#define CONFIG_ENV_IS_IN_DATAFLASH
312#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
313#define CONFIG_ENV_OFFSET 0x4200
314#define CONFIG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
315#define CONFIG_ENV_SIZE 0x4200
316#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
317#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
318 "root=/dev/mtdblock0 " \
Albin Tonnerre918319c2009-07-22 18:30:03 +0200319 "mtdparts=atmel_nand:-(root) "\
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200320 "rw rootfstype=jffs2"
321
322#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */
323
324/* bootstrap + u-boot + env + linux in nandflash */
325#define CONFIG_ENV_IS_IN_NAND
326#define CONFIG_ENV_OFFSET 0x60000
327#define CONFIG_ENV_OFFSET_REDUND 0x80000
328#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
329#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
330#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
331 "root=/dev/mtdblock5 " \
Albin Tonnerre918319c2009-07-22 18:30:03 +0200332 "mtdparts=atmel_nand:" \
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200333 "128k(bootstrap)ro," \
334 "256k(uboot)ro," \
335 "128k(env1)ro," \
336 "128k(env2)ro," \
337 "2M(linux)," \
338 "-(root) " \
339 "rw rootfstype=jffs2"
340
341#elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */
342
343#define CONFIG_ENV_IS_IN_FLASH 1
344#define CONFIG_ENV_OFFSET 0x40000
345#define CONFIG_ENV_SECT_SIZE 0x10000
346#define CONFIG_ENV_SIZE 0x10000
347#define CONFIG_ENV_OVERWRITE 1
348
349/* JFFS Partition offset set */
350#define CONFIG_SYS_JFFS2_FIRST_BANK 0
351#define CONFIG_SYS_JFFS2_NUM_BANKS 1
352
353/* 512k reserved for u-boot */
354#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
355
356#define CONFIG_BOOTCOMMAND "run flashboot"
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000357#define CONFIG_ROOTPATH "/ronetix/rootfs"
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200358#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
359
360#define CONFIG_CON_ROT "fbcon=rotate:3 "
361#define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 "\
362 CONFIG_CON_ROT
363
364#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand"
365#define MTDPARTS_DEFAULT \
366 "mtdparts=physmap-flash.0:" \
367 "256k(u-boot)ro," \
368 "64k(u-boot-env)ro," \
369 "1408k(kernel)," \
370 "-(rootfs);" \
371 "nand:-(nand)"
372
373#define CONFIG_EXTRA_ENV_SETTINGS \
374 "mtdids=" MTDIDS_DEFAULT "\0" \
375 "mtdparts=" MTDPARTS_DEFAULT "\0" \
376 "partition=nand0,0\0" \
377 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
378 "nfsargs=setenv bootargs root=/dev/nfs rw " \
379 CONFIG_CON_ROT \
380 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
381 "addip=setenv bootargs $(bootargs) " \
382 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
383 ":$(hostname):eth0:off\0" \
384 "ramboot=tftpboot 0x22000000 vmImage;" \
385 "run ramargs;run addip;bootm 22000000\0" \
386 "nfsboot=tftpboot 0x22000000 vmImage;" \
387 "run nfsargs;run addip;bootm 22000000\0" \
388 "flashboot=run ramargs;run addip;bootm 0x10050000\0" \
389 ""
390
391#else
392#error "Undefined memory device"
393#endif
394
395#define CONFIG_BAUDRATE 115200
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200396
397#define CONFIG_SYS_PROMPT "u-boot-pm9263> "
398#define CONFIG_SYS_CBSIZE 256
399#define CONFIG_SYS_MAXARGS 16
400#define CONFIG_SYS_PBSIZE \
401 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
402#define CONFIG_SYS_LONGHELP 1
403#define CONFIG_CMDLINE_EDITING 1
404
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200405/*
406 * Size of malloc() pool
407 */
408#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200409
Asen Dimov9a2a05a2010-12-12 12:41:59 +0200410#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
411#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
412 GENERATED_GBL_DATA_SIZE)
413
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200414#endif