Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / c1a2afa4082b4dd84ceb1754f1452c9529d6f390 / . / include / configs / UCP1020.h
blob: 14d786804c418190b1d99420a4c04610f143600a [file] [log] [blame]
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]1/*
2 * Copyright 2013-2015 Arcturus Networks, Inc.
3 * http://www.arcturusnetworks.com/products/ucp1020/
4 * based on include/configs/p1_p2_rdb_pc.h
5 * original copyright follows:
6 * Copyright 2009-2011 Freescale Semiconductor, Inc.
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11/*
12 * QorIQ uCP1020-xx boards configuration file
13 */
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]17#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
18#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
19#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
20#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
21#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
22#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
23
24#if defined(CONFIG_TARTGET_UCP1020T1)
25
26#define CONFIG_UCP1020_REV_1_3
27
28#define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]29
30#define CONFIG_TSEC_ENET
31#define CONFIG_TSEC1
32#define CONFIG_TSEC3
33#define CONFIG_HAS_ETH0
34#define CONFIG_HAS_ETH1
35#define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
36#define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
37#define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
38#define CONFIG_IPADDR 10.80.41.229
39#define CONFIG_SERVERIP 10.80.41.227
40#define CONFIG_NETMASK 255.255.252.0
41#define CONFIG_ETHPRIME "eTSEC3"
42
43#ifndef CONFIG_SPI_FLASH
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]44#endif
45#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
46
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]47#define CONFIG_SYS_L2_SIZE (256 << 10)
48
49#define CONFIG_LAST_STAGE_INIT
50
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]51#endif
52
53#if defined(CONFIG_TARGET_UCP1020)
54
55#define CONFIG_UCP1020
56#define CONFIG_UCP1020_REV_1_3
57
58#define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]59
60#define CONFIG_TSEC_ENET
61#define CONFIG_TSEC1
62#define CONFIG_TSEC2
63#define CONFIG_TSEC3
64#define CONFIG_HAS_ETH0
65#define CONFIG_HAS_ETH1
66#define CONFIG_HAS_ETH2
67#define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
68#define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
69#define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
70#define CONFIG_IPADDR 192.168.1.81
71#define CONFIG_IPADDR1 192.168.1.82
72#define CONFIG_IPADDR2 192.168.1.83
73#define CONFIG_SERVERIP 192.168.1.80
74#define CONFIG_GATEWAYIP 102.168.1.1
75#define CONFIG_NETMASK 255.255.255.0
76#define CONFIG_ETHPRIME "eTSEC1"
77
78#ifndef CONFIG_SPI_FLASH
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]79#endif
80#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
81
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]82#define CONFIG_SYS_L2_SIZE (256 << 10)
83
84#define CONFIG_LAST_STAGE_INIT
85
86#endif
87
88#ifdef CONFIG_SDCARD
89#define CONFIG_RAMBOOT_SDCARD
90#define CONFIG_SYS_RAMBOOT
91#define CONFIG_SYS_EXTRA_ENV_RELOC
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]92#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
93#endif
94
95#ifdef CONFIG_SPIFLASH
96#define CONFIG_RAMBOOT_SPIFLASH
97#define CONFIG_SYS_RAMBOOT
98#define CONFIG_SYS_EXTRA_ENV_RELOC
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]99#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
100#endif
101
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]102#define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
103
104#ifndef CONFIG_RESET_VECTOR_ADDRESS
105#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
106#endif
107
108#ifndef CONFIG_SYS_MONITOR_BASE
109#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
110#endif
111
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]112#define CONFIG_MP
113
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]114#define CONFIG_ENV_OVERWRITE
115
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]116#define CONFIG_SYS_SATA_MAX_DEVICE 2
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]117#define CONFIG_LBA48
118
119#define CONFIG_SYS_CLK_FREQ 66666666
120#define CONFIG_DDR_CLK_FREQ 66666666
121
122#define CONFIG_HWCONFIG
123
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]124/*
125 * These can be toggled for performance analysis, otherwise use default.
126 */
127#define CONFIG_L2_CACHE
128#define CONFIG_BTB
129
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]130#define CONFIG_ENABLE_36BIT_PHYS
131
132#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
133#define CONFIG_SYS_MEMTEST_END 0x1fffffff
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]134
135#define CONFIG_SYS_CCSRBAR 0xffe00000
136#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
137
138/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
139 SPL code*/
140#ifdef CONFIG_SPL_BUILD
141#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
142#endif
143
144/* DDR Setup */
145#define CONFIG_DDR_ECC_ENABLE
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]146#ifndef CONFIG_DDR_ECC_ENABLE
147#define CONFIG_SYS_DDR_RAW_TIMING
148#define CONFIG_DDR_SPD
149#endif
150#define CONFIG_SYS_SPD_BUS_NUM 1
151#undef CONFIG_FSL_DDR_INTERACTIVE
152
153#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
154#define CONFIG_CHIP_SELECTS_PER_CTRL 1
155#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
156#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
157#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
158
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]159#define CONFIG_DIMM_SLOTS_PER_CTLR 1
160
161/* Default settings for DDR3 */
162#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
163#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
164#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
165#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
166#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
167#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
168
169#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
170#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
171#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
172#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
173
174#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
175#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
176#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
177#define CONFIG_SYS_DDR_RCW_1 0x00000000
178#define CONFIG_SYS_DDR_RCW_2 0x00000000
179#ifdef CONFIG_DDR_ECC_ENABLE
180#define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
181#else
182#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
183#endif
184#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
185#define CONFIG_SYS_DDR_TIMING_4 0x00220001
186#define CONFIG_SYS_DDR_TIMING_5 0x03402400
187
188#define CONFIG_SYS_DDR_TIMING_3 0x00020000
189#define CONFIG_SYS_DDR_TIMING_0 0x00330004
190#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
191#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
192#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
193#define CONFIG_SYS_DDR_MODE_1 0x40461520
194#define CONFIG_SYS_DDR_MODE_2 0x8000c000
195#define CONFIG_SYS_DDR_INTERVAL 0x0C300000
196
197#undef CONFIG_CLOCKS_IN_MHZ
198
199/*
200 * Memory map
201 *
202 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
203 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
204 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
205 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
206 * (early boot only)
207 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
208 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
209 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
210 */
211
212/*
213 * Local Bus Definitions
214 */
215#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
216#define CONFIG_SYS_FLASH_BASE 0xec000000
217
218#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
219
220#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
221 | BR_PS_16 | BR_V)
222
223#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
224
225#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
226#define CONFIG_SYS_FLASH_QUIET_TEST
227#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
228
229#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
230
231#undef CONFIG_SYS_FLASH_CHECKSUM
232#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
233#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
234
235#define CONFIG_FLASH_CFI_DRIVER
236#define CONFIG_SYS_FLASH_CFI
237#define CONFIG_SYS_FLASH_EMPTY_INFO
238#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
239
240#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
241
242#define CONFIG_SYS_INIT_RAM_LOCK
243#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
244/* Initial L1 address */
245#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
246#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
247#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
248/* Size of used area in RAM */
249#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
250
251#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
252 GENERATED_GBL_DATA_SIZE)
253#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
254
255#define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
256#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
257
258#define CONFIG_SYS_PMC_BASE 0xff980000
259#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
260#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
261 BR_PS_8 | BR_V)
262#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
263 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
264 OR_GPCM_EAD)
265
266#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
267#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
268#ifdef CONFIG_NAND_FSL_ELBC
269#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
270#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
271#endif
272
273/* Serial Port - controlled on board with jumper J8
274 * open - index 2
275 * shorted - index 1
276 */
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]277#undef CONFIG_SERIAL_SOFTWARE_FIFO
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]278#define CONFIG_SYS_NS16550_SERIAL
279#define CONFIG_SYS_NS16550_REG_SIZE 1
280#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
281#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
282#define CONFIG_NS16550_MIN_FUNCTIONS
283#endif
284
285#define CONFIG_SYS_BAUDRATE_TABLE \
286 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
287
288#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
289#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
290
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]291/* I2C */
292#define CONFIG_SYS_I2C
293#define CONFIG_SYS_I2C_FSL
294#define CONFIG_SYS_FSL_I2C_SPEED 400000
295#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
296#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
297#define CONFIG_SYS_FSL_I2C2_SPEED 400000
298#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
299#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
300#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
301#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
302
303#define CONFIG_RTC_DS1337
Chris Packham2bd3cab2017-05-30 12:03:33 +1200[diff] [blame]304#define CONFIG_RTC_DS1337_NOOSC
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]305#define CONFIG_SYS_I2C_RTC_ADDR 0x68
306#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
307#define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
308#define CONFIG_SYS_I2C_IDT6V49205B 0x69
309
310/*
311 * eSPI - Enhanced SPI
312 */
313#define CONFIG_HARD_SPI
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]314
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]315#define CONFIG_SF_DEFAULT_SPEED 10000000
316#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
317
318#if defined(CONFIG_PCI)
319/*
320 * General PCI
321 * Memory space is mapped 1-1, but I/O space must start from 0.
322 */
323
324/* controller 2, direct to uli, tgtid 2, Base address 9000 */
325#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
326#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
327#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
328#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
329#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
330#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
331#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
332#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
333#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
334
335/* controller 1, Slot 2, tgtid 1, Base address a000 */
336#define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
337#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
338#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
339#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
340#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
341#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
342#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
343#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
344#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
345
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]346#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]347#endif /* CONFIG_PCI */
348
349/*
350 * Environment
351 */
352#ifdef CONFIG_ENV_FIT_UCBOOT
353
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]354#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000)
355#define CONFIG_ENV_SIZE 0x20000
356#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
357
358#else
359
360#define CONFIG_ENV_SPI_BUS 0
361#define CONFIG_ENV_SPI_CS 0
362#define CONFIG_ENV_SPI_MAX_HZ 10000000
363#define CONFIG_ENV_SPI_MODE 0
364
365#ifdef CONFIG_RAMBOOT_SPIFLASH
366
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]367#define CONFIG_ENV_SIZE 0x3000 /* 12KB */
368#define CONFIG_ENV_OFFSET 0x2000 /* 8KB */
369#define CONFIG_ENV_SECT_SIZE 0x1000
370
371#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
372/* Address and size of Redundant Environment Sector */
373#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
374#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
375#endif
376
377#elif defined(CONFIG_RAMBOOT_SDCARD)
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]378#define CONFIG_FSL_FIXED_MMC_LOCATION
379#define CONFIG_ENV_SIZE 0x2000
380#define CONFIG_SYS_MMC_ENV_DEV 0
381
382#elif defined(CONFIG_SYS_RAMBOOT)
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]383#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
384#define CONFIG_ENV_SIZE 0x2000
385
386#else
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]387#define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE)
388#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
389#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
390#define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000)
391#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
392/* Address and size of Redundant Environment Sector */
393#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
394#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
395#endif
396
397#endif
398
399#endif /* CONFIG_ENV_FIT_UCBOOT */
400
401#define CONFIG_LOADS_ECHO /* echo on for serial download */
402#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
403
404/*
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]405 * USB
406 */
407#define CONFIG_HAS_FSL_DR_USB
408
409#if defined(CONFIG_HAS_FSL_DR_USB)
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]410#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
411
Tom Rini8850c5d2017-05-12 22:33:27 -0400[diff] [blame]412#ifdef CONFIG_USB_EHCI_HCD
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]413#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
414#define CONFIG_USB_EHCI_FSL
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]415#endif
416#endif
417
418#undef CONFIG_WATCHDOG /* watchdog disabled */
419
420#ifdef CONFIG_MMC
421#define CONFIG_FSL_ESDHC
422#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]423#define CONFIG_MMC_SPI
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]424#endif
425
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]426/* Misc Extra Settings */
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]427#undef CONFIG_WATCHDOG /* watchdog disabled */
428
429/*
430 * Miscellaneous configurable options
431 */
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]432#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]433#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
434
435/*
436 * For booting Linux, the board info and command line data
437 * have to be in the first 64 MB of memory, since this is
438 * the maximum mapped by the Linux kernel during initialization.
439 */
440#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
441#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
442
443#if defined(CONFIG_CMD_KGDB)
444#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
445#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
446#endif
447
448/*
449 * Environment Configuration
450 */
451
452#if defined(CONFIG_TSEC_ENET)
453
Alexandru Gagniucfb92bc82017-07-07 11:36:58 -0700[diff] [blame]454#if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3)
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]455#else
456#error "UCP1020 module revision is not defined !!!"
457#endif
458
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]459#define CONFIG_BOOTP_SERVERIP
460
461#define CONFIG_MII /* MII PHY management */
462#define CONFIG_TSEC1_NAME "eTSEC1"
463#define CONFIG_TSEC2_NAME "eTSEC2"
464#define CONFIG_TSEC3_NAME "eTSEC3"
465
466#define TSEC1_PHY_ADDR 4
467#define TSEC2_PHY_ADDR 0
468#define TSEC2_PHY_ADDR_SGMII 0x00
469#define TSEC3_PHY_ADDR 6
470
471#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
472#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
473#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
474
475#define TSEC1_PHYIDX 0
476#define TSEC2_PHYIDX 0
477#define TSEC3_PHYIDX 0
478
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]479#endif
480
481#define CONFIG_HOSTNAME UCP1020
482#define CONFIG_ROOTPATH "/opt/nfsroot"
483#define CONFIG_BOOTFILE "uImage"
484#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
485
486/* default location for tftp and bootm */
487#define CONFIG_LOADADDR 1000000
488
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]489#if defined(CONFIG_DONGLE)
490
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]491#define CONFIG_EXTRA_ENV_SETTINGS \
492"bootcmd=run prog_spi_mbrbootcramfs\0" \
493"bootfile=uImage\0" \
494"consoledev=ttyS0\0" \
495"cramfsfile=image.cramfs\0" \
496"dtbaddr=0x00c00000\0" \
497"dtbfile=image.dtb\0" \
498"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
499"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
500"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
501"fileaddr=0x01000000\0" \
502"filesize=0x00080000\0" \
503"flashmbr=sf probe 0; " \
504 "tftp $loadaddr $mbr; " \
505 "sf erase $mbr_offset +$filesize; " \
506 "sf write $loadaddr $mbr_offset $filesize\0" \
507"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
508 "protect off $nor_recoveryaddr +$filesize; " \
509 "erase $nor_recoveryaddr +$filesize; " \
510 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
511 "protect on $nor_recoveryaddr +$filesize\0 " \
512"flashuboot=tftp $ubootaddr $ubootfile; " \
513 "protect off $nor_ubootaddr +$filesize; " \
514 "erase $nor_ubootaddr +$filesize; " \
515 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
516 "protect on $nor_ubootaddr +$filesize\0 " \
517"flashworking=tftp $workingaddr $cramfsfile; " \
518 "protect off $nor_workingaddr +$filesize; " \
519 "erase $nor_workingaddr +$filesize; " \
520 "cp.b $workingaddr $nor_workingaddr $filesize; " \
521 "protect on $nor_workingaddr +$filesize\0 " \
522"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
523"kerneladdr=0x01100000\0" \
524"kernelfile=uImage\0" \
525"loadaddr=0x01000000\0" \
526"mbr=uCP1020d.mbr\0" \
527"mbr_offset=0x00000000\0" \
528"mmbr=uCP1020Quiet.mbr\0" \
529"mmcpart=0:2\0" \
530"mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
531 "mmc erase 1 1; " \
532 "mmc write $loadaddr 1 1\0" \
533"mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
534 "mmc erase 0x40 0x400; " \
535 "mmc write $loadaddr 0x40 0x400\0" \
536"netdev=eth0\0" \
537"nor_recoveryaddr=0xEC0A0000\0" \
538"nor_ubootaddr=0xEFF80000\0" \
539"nor_workingaddr=0xECFA0000\0" \
540"norbootrecovery=setenv bootargs $recoverybootargs" \
541 " console=$consoledev,$baudrate $othbootargs; " \
542 "run norloadrecovery; " \
543 "bootm $kerneladdr - $dtbaddr\0" \
544"norbootworking=setenv bootargs $workingbootargs" \
545 " console=$consoledev,$baudrate $othbootargs; " \
546 "run norloadworking; " \
547 "bootm $kerneladdr - $dtbaddr\0" \
548"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
549 "setenv cramfsaddr $nor_recoveryaddr; " \
550 "cramfsload $dtbaddr $dtbfile; " \
551 "cramfsload $kerneladdr $kernelfile\0" \
552"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
553 "setenv cramfsaddr $nor_workingaddr; " \
554 "cramfsload $dtbaddr $dtbfile; " \
555 "cramfsload $kerneladdr $kernelfile\0" \
556"prog_spi_mbr=run spi__mbr\0" \
557"prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
558"prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
559 "run spi__cramfs\0" \
560"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
561 " console=$consoledev,$baudrate $othbootargs; " \
562 "tftp $rootfsaddr $rootfsfile; " \
563 "tftp $loadaddr $kernelfile; " \
564 "tftp $dtbaddr $dtbfile; " \
565 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
566"ramdisk_size=120000\0" \
567"ramdiskfile=rootfs.ext2.gz.uboot\0" \
568"recoveryaddr=0x02F00000\0" \
569"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
570"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
571 "mw.l 0xffe0f008 0x00400000\0" \
572"rootfsaddr=0x02F00000\0" \
573"rootfsfile=rootfs.ext2.gz.uboot\0" \
574"rootpath=/opt/nfsroot\0" \
575"spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
576 "protect off 0xeC000000 +$filesize; " \
577 "erase 0xEC000000 +$filesize; " \
578 "cp.b $loadaddr 0xEC000000 $filesize; " \
579 "cmp.b $loadaddr 0xEC000000 $filesize; " \
580 "protect on 0xeC000000 +$filesize\0" \
581"spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
582 "protect off 0xeFF80000 +$filesize; " \
583 "erase 0xEFF80000 +$filesize; " \
584 "cp.b $loadaddr 0xEFF80000 $filesize; " \
585 "cmp.b $loadaddr 0xEFF80000 $filesize; " \
586 "protect on 0xeFF80000 +$filesize\0" \
587"spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
588 "sf probe 0; sf erase 0x8000 +$filesize; " \
589 "sf write $loadaddr 0x8000 $filesize\0" \
590"spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
591 "protect off 0xec0a0000 +$filesize; " \
592 "erase 0xeC0A0000 +$filesize; " \
593 "cp.b $loadaddr 0xeC0A0000 $filesize; " \
594 "protect on 0xec0a0000 +$filesize\0" \
595"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
596 "sf probe 1; sf erase 0 +$filesize; " \
597 "sf write $loadaddr 0 $filesize\0" \
598"spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
599 "sf probe 0; sf erase 0 +$filesize; " \
600 "sf write $loadaddr 0 $filesize\0" \
601"tftpflash=tftpboot $loadaddr $uboot; " \
602 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
603 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
604 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
605 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
606 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
607"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
608"ubootaddr=0x01000000\0" \
609"ubootfile=u-boot.bin\0" \
610"ubootd=u-boot4dongle.bin\0" \
611"upgrade=run flashworking\0" \
612"usb_phy_type=ulpi\0 " \
613"workingaddr=0x02F00000\0" \
614"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
615
616#else
617
618#if defined(CONFIG_UCP1020T1)
619
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]620#define CONFIG_EXTRA_ENV_SETTINGS \
621"bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
622"bootfile=uImage\0" \
623"consoledev=ttyS0\0" \
624"cramfsfile=image.cramfs\0" \
625"dtbaddr=0x00c00000\0" \
626"dtbfile=image.dtb\0" \
627"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
628"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
629"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
630"fileaddr=0x01000000\0" \
631"filesize=0x00080000\0" \
632"flashmbr=sf probe 0; " \
633 "tftp $loadaddr $mbr; " \
634 "sf erase $mbr_offset +$filesize; " \
635 "sf write $loadaddr $mbr_offset $filesize\0" \
636"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
637 "protect off $nor_recoveryaddr +$filesize; " \
638 "erase $nor_recoveryaddr +$filesize; " \
639 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
640 "protect on $nor_recoveryaddr +$filesize\0 " \
641"flashuboot=tftp $ubootaddr $ubootfile; " \
642 "protect off $nor_ubootaddr +$filesize; " \
643 "erase $nor_ubootaddr +$filesize; " \
644 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
645 "protect on $nor_ubootaddr +$filesize\0 " \
646"flashworking=tftp $workingaddr $cramfsfile; " \
647 "protect off $nor_workingaddr +$filesize; " \
648 "erase $nor_workingaddr +$filesize; " \
649 "cp.b $workingaddr $nor_workingaddr $filesize; " \
650 "protect on $nor_workingaddr +$filesize\0 " \
651"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
652"kerneladdr=0x01100000\0" \
653"kernelfile=uImage\0" \
654"loadaddr=0x01000000\0" \
655"mbr=uCP1020.mbr\0" \
656"mbr_offset=0x00000000\0" \
657"netdev=eth0\0" \
658"nor_recoveryaddr=0xEC0A0000\0" \
659"nor_ubootaddr=0xEFF80000\0" \
660"nor_workingaddr=0xECFA0000\0" \
661"norbootrecovery=setenv bootargs $recoverybootargs" \
662 " console=$consoledev,$baudrate $othbootargs; " \
663 "run norloadrecovery; " \
664 "bootm $kerneladdr - $dtbaddr\0" \
665"norbootworking=setenv bootargs $workingbootargs" \
666 " console=$consoledev,$baudrate $othbootargs; " \
667 "run norloadworking; " \
668 "bootm $kerneladdr - $dtbaddr\0" \
669"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
670 "setenv cramfsaddr $nor_recoveryaddr; " \
671 "cramfsload $dtbaddr $dtbfile; " \
672 "cramfsload $kerneladdr $kernelfile\0" \
673"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
674 "setenv cramfsaddr $nor_workingaddr; " \
675 "cramfsload $dtbaddr $dtbfile; " \
676 "cramfsload $kerneladdr $kernelfile\0" \
677"othbootargs=quiet\0" \
678"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
679 " console=$consoledev,$baudrate $othbootargs; " \
680 "tftp $rootfsaddr $rootfsfile; " \
681 "tftp $loadaddr $kernelfile; " \
682 "tftp $dtbaddr $dtbfile; " \
683 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
684"ramdisk_size=120000\0" \
685"ramdiskfile=rootfs.ext2.gz.uboot\0" \
686"recoveryaddr=0x02F00000\0" \
687"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
688"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
689 "mw.l 0xffe0f008 0x00400000\0" \
690"rootfsaddr=0x02F00000\0" \
691"rootfsfile=rootfs.ext2.gz.uboot\0" \
692"rootpath=/opt/nfsroot\0" \
693"silent=1\0" \
694"tftpflash=tftpboot $loadaddr $uboot; " \
695 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
696 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
697 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
698 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
699 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
700"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
701"ubootaddr=0x01000000\0" \
702"ubootfile=u-boot.bin\0" \
703"upgrade=run flashworking\0" \
704"workingaddr=0x02F00000\0" \
705"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
706
707#else /* For Arcturus Modules */
708
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400[diff] [blame]709#define CONFIG_EXTRA_ENV_SETTINGS \
710"bootcmd=run norkernel\0" \
711"bootfile=uImage\0" \
712"consoledev=ttyS0\0" \
713"dtbaddr=0x00c00000\0" \
714"dtbfile=image.dtb\0" \
715"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
716"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
717"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
718"fileaddr=0x01000000\0" \
719"filesize=0x00080000\0" \
720"flashmbr=sf probe 0; " \
721 "tftp $loadaddr $mbr; " \
722 "sf erase $mbr_offset +$filesize; " \
723 "sf write $loadaddr $mbr_offset $filesize\0" \
724"flashuboot=tftp $loadaddr $ubootfile; " \
725 "protect off $nor_ubootaddr0 +$filesize; " \
726 "erase $nor_ubootaddr0 +$filesize; " \
727 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
728 "protect on $nor_ubootaddr0 +$filesize; " \
729 "protect off $nor_ubootaddr1 +$filesize; " \
730 "erase $nor_ubootaddr1 +$filesize; " \
731 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
732 "protect on $nor_ubootaddr1 +$filesize\0 " \
733"format0=protect off $part0base +$part0size; " \
734 "erase $part0base +$part0size\0" \
735"format1=protect off $part1base +$part1size; " \
736 "erase $part1base +$part1size\0" \
737"format2=protect off $part2base +$part2size; " \
738 "erase $part2base +$part2size\0" \
739"format3=protect off $part3base +$part3size; " \
740 "erase $part3base +$part3size\0" \
741"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
742"kerneladdr=0x01100000\0" \
743"kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
744"kernelfile=uImage\0" \
745"loadaddr=0x01000000\0" \
746"mbr=uCP1020.mbr\0" \
747"mbr_offset=0x00000000\0" \
748"netdev=eth0\0" \
749"nor_ubootaddr0=0xEC000000\0" \
750"nor_ubootaddr1=0xEFF80000\0" \
751"norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
752 "run norkernelload; " \
753 "bootm $kerneladdr - $dtbaddr\0" \
754"norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
755 "setenv cramfsaddr $part0base; " \
756 "cramfsload $dtbaddr $dtbfile; " \
757 "cramfsload $kerneladdr $kernelfile\0" \
758"part0base=0xEC100000\0" \
759"part0size=0x00700000\0" \
760"part1base=0xEC800000\0" \
761"part1size=0x02000000\0" \
762"part2base=0xEE800000\0" \
763"part2size=0x00800000\0" \
764"part3base=0xEF000000\0" \
765"part3size=0x00F80000\0" \
766"partENVbase=0xEC080000\0" \
767"partENVsize=0x00080000\0" \
768"program0=tftp part0-000000.bin; " \
769 "protect off $part0base +$filesize; " \
770 "erase $part0base +$filesize; " \
771 "cp.b $loadaddr $part0base $filesize; " \
772 "echo Verifying...; " \
773 "cmp.b $loadaddr $part0base $filesize\0" \
774"program1=tftp part1-000000.bin; " \
775 "protect off $part1base +$filesize; " \
776 "erase $part1base +$filesize; " \
777 "cp.b $loadaddr $part1base $filesize; " \
778 "echo Verifying...; " \
779 "cmp.b $loadaddr $part1base $filesize\0" \
780"program2=tftp part2-000000.bin; " \
781 "protect off $part2base +$filesize; " \
782 "erase $part2base +$filesize; " \
783 "cp.b $loadaddr $part2base $filesize; " \
784 "echo Verifying...; " \
785 "cmp.b $loadaddr $part2base $filesize\0" \
786"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
787 " console=$consoledev,$baudrate $othbootargs; " \
788 "tftp $rootfsaddr $rootfsfile; " \
789 "tftp $loadaddr $kernelfile; " \
790 "tftp $dtbaddr $dtbfile; " \
791 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
792"ramdisk_size=120000\0" \
793"ramdiskfile=rootfs.ext2.gz.uboot\0" \
794"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
795 "mw.l 0xffe0f008 0x00400000\0" \
796"rootfsaddr=0x02F00000\0" \
797"rootfsfile=rootfs.ext2.gz.uboot\0" \
798"rootpath=/opt/nfsroot\0" \
799"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
800 "sf probe 0; sf erase 0 +$filesize; " \
801 "sf write $loadaddr 0 $filesize\0" \
802"spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
803 "protect off 0xeC000000 +$filesize; " \
804 "erase 0xEC000000 +$filesize; " \
805 "cp.b $loadaddr 0xEC000000 $filesize; " \
806 "cmp.b $loadaddr 0xEC000000 $filesize; " \
807 "protect on 0xeC000000 +$filesize\0" \
808"tftpflash=tftpboot $loadaddr $uboot; " \
809 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
810 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
811 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
812 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
813 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
814"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
815"ubootfile=u-boot.bin\0" \
816"upgrade=run flashuboot\0" \
817"usb_phy_type=ulpi\0 " \
818"boot_nfs= " \
819 "setenv bootargs root=/dev/nfs rw " \
820 "nfsroot=$serverip:$rootpath " \
821 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
822 "console=$consoledev,$baudrate $othbootargs;" \
823 "tftp $loadaddr $bootfile;" \
824 "tftp $fdtaddr $fdtfile;" \
825 "bootm $loadaddr - $fdtaddr\0" \
826"boot_hd = " \
827 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
828 "console=$consoledev,$baudrate $othbootargs;" \
829 "usb start;" \
830 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
831 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
832 "bootm $loadaddr - $fdtaddr\0" \
833"boot_usb_fat = " \
834 "setenv bootargs root=/dev/ram rw " \
835 "console=$consoledev,$baudrate $othbootargs " \
836 "ramdisk_size=$ramdisk_size;" \
837 "usb start;" \
838 "fatload usb 0:2 $loadaddr $bootfile;" \
839 "fatload usb 0:2 $fdtaddr $fdtfile;" \
840 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
841 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
842"boot_usb_ext2 = " \
843 "setenv bootargs root=/dev/ram rw " \
844 "console=$consoledev,$baudrate $othbootargs " \
845 "ramdisk_size=$ramdisk_size;" \
846 "usb start;" \
847 "ext2load usb 0:4 $loadaddr $bootfile;" \
848 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
849 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
850 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
851"boot_nor = " \
852 "setenv bootargs root=/dev/$jffs2nor rw " \
853 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
854 "bootm $norbootaddr - $norfdtaddr\0 " \
855"boot_ram = " \
856 "setenv bootargs root=/dev/ram rw " \
857 "console=$consoledev,$baudrate $othbootargs " \
858 "ramdisk_size=$ramdisk_size;" \
859 "tftp $ramdiskaddr $ramdiskfile;" \
860 "tftp $loadaddr $bootfile;" \
861 "tftp $fdtaddr $fdtfile;" \
862 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
863
864#endif
865#endif
866
867#endif /* __CONFIG_H */