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wdenkc6097192002-11-03 00:24:07 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2001-2005
wdenkc6097192002-11-03 00:24:07 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/* ------------------------------------------------------------------------- */
25
26/*
27 * board/config.h - configuration options, board specific
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
38#define CONFIG_MPC824X 1
39#define CONFIG_MPC8245 1
40#define CONFIG_SANDPOINT 1
41
42#if 0
43#define USE_DINK32 1
44#else
45#undef USE_DINK32
46#endif
47
48#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */
49#define CONFIG_BAUDRATE 9600
50#define CONFIG_DRAM_SPEED 100 /* MHz */
51
wdenk414eec32005-04-02 22:37:54 +000052#define CONFIG_TIMESTAMP /* Print image info with timestamp */
53
54#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
55 CFG_CMD_DHCP | \
56 CFG_CMD_ELF | \
57 CFG_CMD_I2C | \
58 CFG_CMD_EEPROM | \
59 CFG_CMD_NFS | \
60 CFG_CMD_PCI | \
61 CFG_CMD_SNTP )
wdenkc6097192002-11-03 00:24:07 +000062
63/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
64#include <cmd_confdefs.h>
65
66
67/*
68 * Miscellaneous configurable options
69 */
70#define CFG_LONGHELP 1 /* undef to save memory */
71#define CFG_PROMPT "=> " /* Monitor Command Prompt */
72#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
73#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
74#define CFG_MAXARGS 16 /* max number of command args */
75#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
76#define CFG_LOAD_ADDR 0x00100000 /* default load address */
77#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
78
79/*-----------------------------------------------------------------------
80 * PCI stuff
81 *-----------------------------------------------------------------------
82 */
83#define CONFIG_PCI /* include pci support */
84#undef CONFIG_PCI_PNP
85
86#define CONFIG_NET_MULTI /* Multi ethernet cards support */
87
88#define CONFIG_EEPRO100
stroese53cf9432003-06-05 15:39:44 +000089#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenkc6097192002-11-03 00:24:07 +000090#define CONFIG_NATSEMI
91#define CONFIG_NS8382X
92
93#define PCI_ENET0_IOADDR 0x80000000
94#define PCI_ENET0_MEMADDR 0x80000000
95#define PCI_ENET1_IOADDR 0x81000000
96#define PCI_ENET1_MEMADDR 0x81000000
97
98
99/*-----------------------------------------------------------------------
100 * Start addresses for the final memory configuration
101 * (Set up by the startup code)
102 * Please note that CFG_SDRAM_BASE _must_ start at 0
103 */
104#define CFG_SDRAM_BASE 0x00000000
105#define CFG_MAX_RAM_SIZE 0x10000000
106
107#define CFG_RESET_ADDRESS 0xFFF00100
108
109#if defined (USE_DINK32)
110#define CFG_MONITOR_LEN 0x00030000
111#define CFG_MONITOR_BASE 0x00090000
112#define CFG_RAMBOOT 1
113#define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
114#define CFG_INIT_RAM_END 0x10000
115#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
116#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
117#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
118#else
119#undef CFG_RAMBOOT
120#define CFG_MONITOR_LEN 0x00030000
121#define CFG_MONITOR_BASE TEXT_BASE
122
123/*#define CFG_GBL_DATA_SIZE 256*/
124#define CFG_GBL_DATA_SIZE 128
125
126#define CFG_INIT_RAM_ADDR 0x40000000
127#define CFG_INIT_RAM_END 0x1000
128#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
129
130#endif
131
132#define CFG_FLASH_BASE 0xFFF00000
133#if 0
134#define CFG_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */
135#else
136#define CFG_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */
137#endif
138#define CFG_ENV_IS_IN_FLASH 1
139#define CFG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
140#define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
141
142#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
143
144#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
145#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
146
147#define CFG_EUMB_ADDR 0xFC000000
148
149#define CFG_ISA_MEM 0xFD000000
150#define CFG_ISA_IO 0xFE000000
151
152#define CFG_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */
153#define CFG_FLASH_RANGE_SIZE 0x01000000
154#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */
155#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */
156
157/*
158 * select i2c support configuration
159 *
160 * Supported configurations are {none, software, hardware} drivers.
161 * If the software driver is chosen, there are some additional
162 * configuration items that the driver uses to drive the port pins.
163 */
164#define CONFIG_HARD_I2C 1 /* To enable I2C support */
165#undef CONFIG_SOFT_I2C /* I2C bit-banged */
166#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
167#define CFG_I2C_SLAVE 0x7F
168
169#ifdef CONFIG_SOFT_I2C
170#error "Soft I2C is not configured properly. Please review!"
171#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
172#define I2C_ACTIVE (iop->pdir |= 0x00010000)
173#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
174#define I2C_READ ((iop->pdat & 0x00010000) != 0)
175#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
176 else iop->pdat &= ~0x00010000
177#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
178 else iop->pdat &= ~0x00020000
179#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
180#endif /* CONFIG_SOFT_I2C */
181
182#define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
183#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
184#define CFG_EEPROM_PAGE_WRITE_BITS 3
185#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
186
187#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
188#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
189
190/*-----------------------------------------------------------------------
191 * Definitions for initial stack pointer and data area (in DPRAM)
192 */
193
194
195#define CFG_WINBOND_83C553 1 /*has a winbond bridge */
196#define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */
197#define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
198#define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
199
200#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
201#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
202
203/*
204 * NS87308 Configuration
205 */
206#define CFG_NS87308 /* Nat Semi super-io controller on ISA bus */
207
208#define CFG_NS87308_BADDR_10 1
209
210#define CFG_NS87308_DEVS ( CFG_NS87308_UART1 | \
211 CFG_NS87308_UART2 | \
212 CFG_NS87308_POWRMAN | \
213 CFG_NS87308_RTC_APC )
214
215#undef CFG_NS87308_PS2MOD
216
217#define CFG_NS87308_CS0_BASE 0x0076
218#define CFG_NS87308_CS0_CONF 0x30
219#define CFG_NS87308_CS1_BASE 0x0075
220#define CFG_NS87308_CS1_CONF 0x30
221#define CFG_NS87308_CS2_BASE 0x0074
222#define CFG_NS87308_CS2_CONF 0x30
223
224/*
225 * NS16550 Configuration
226 */
227#define CFG_NS16550
228#define CFG_NS16550_SERIAL
229
230#define CFG_NS16550_REG_SIZE 1
231
wdenkf832d8a2004-06-10 21:55:33 +0000232#if (CONFIG_CONS_INDEX > 2)
233#define CFG_NS16550_CLK CONFIG_DRAM_SPEED*1000000
234#else
235#define CFG_NS16550_CLK 1843200
236#endif
wdenk49822e22004-06-19 21:19:10 +0000237
wdenkc6097192002-11-03 00:24:07 +0000238#define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE)
239#define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE)
240#define CFG_NS16550_COM3 (CFG_EUMB_ADDR + 0x4500)
241#define CFG_NS16550_COM4 (CFG_EUMB_ADDR + 0x4600)
242
243/*
244 * Low Level Configuration Settings
245 * (address mappings, register initial values, etc.)
246 * You should know what you are doing if you make changes here.
247 */
248
249#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
250
251#define CFG_ROMNAL 7 /*rom/flash next access time */
252#define CFG_ROMFAL 11 /*rom/flash access time */
253
254#define CFG_REFINT 430 /* no of clock cycles between CBR refresh cycles */
255
256/* the following are for SDRAM only*/
257#define CFG_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
258#define CFG_REFREC 8 /* Refresh to activate interval */
259#define CFG_RDLAT 4 /* data latency from read command */
260#define CFG_PRETOACT 3 /* Precharge to activate interval */
261#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
262#define CFG_ACTORW 3 /* Activate to R/W */
263#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
264#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
265#if 0
266#define CFG_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */
267#endif
268
269#define CFG_REGISTERD_TYPE_BUFFER 1
270#define CFG_EXTROM 1
271#define CFG_REGDIMM 0
272
273
274/* memory bank settings*/
275/*
276 * only bits 20-29 are actually used from these vales to set the
277 * start/end address the upper two bits will be 0, and the lower 20
278 * bits will be set to 0x00000 for a start address, or 0xfffff for an
279 * end address
280 */
281#define CFG_BANK0_START 0x00000000
282#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
283#define CFG_BANK0_ENABLE 1
284#define CFG_BANK1_START 0x3ff00000
285#define CFG_BANK1_END 0x3fffffff
286#define CFG_BANK1_ENABLE 0
287#define CFG_BANK2_START 0x3ff00000
288#define CFG_BANK2_END 0x3fffffff
289#define CFG_BANK2_ENABLE 0
290#define CFG_BANK3_START 0x3ff00000
291#define CFG_BANK3_END 0x3fffffff
292#define CFG_BANK3_ENABLE 0
293#define CFG_BANK4_START 0x00000000
294#define CFG_BANK4_END 0x00000000
295#define CFG_BANK4_ENABLE 0
296#define CFG_BANK5_START 0x00000000
297#define CFG_BANK5_END 0x00000000
298#define CFG_BANK5_ENABLE 0
299#define CFG_BANK6_START 0x00000000
300#define CFG_BANK6_END 0x00000000
301#define CFG_BANK6_ENABLE 0
302#define CFG_BANK7_START 0x00000000
303#define CFG_BANK7_END 0x00000000
304#define CFG_BANK7_ENABLE 0
305/*
306 * Memory bank enable bitmask, specifying which of the banks defined above
307 are actually present. MSB is for bank #7, LSB is for bank #0.
308 */
309#define CFG_BANK_ENABLE 0x01
310
311#define CFG_ODCR 0xff /* configures line driver impedances, */
312 /* see 8240 book for bit definitions */
313#define CFG_PGMAX 0x32 /* how long the 8240 retains the */
314 /* currently accessed page in memory */
315 /* see 8240 book for details */
316
317/* SDRAM 0 - 256MB */
318#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
319#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
320
321/* stack in DCACHE @ 1GB (no backing mem) */
322#if defined(USE_DINK32)
323#define CFG_IBAT1L (0x40000000 | BATL_PP_00 )
324#define CFG_IBAT1U (0x40000000 | BATU_BL_128K )
325#else
326#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
327#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
328#endif
329
330/* PCI memory */
331#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
332#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
333
334/* Flash, config addrs, etc */
335#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
336#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
337
338#define CFG_DBAT0L CFG_IBAT0L
339#define CFG_DBAT0U CFG_IBAT0U
340#define CFG_DBAT1L CFG_IBAT1L
341#define CFG_DBAT1U CFG_IBAT1U
342#define CFG_DBAT2L CFG_IBAT2L
343#define CFG_DBAT2U CFG_IBAT2U
344#define CFG_DBAT3L CFG_IBAT3L
345#define CFG_DBAT3U CFG_IBAT3U
346
347/*
348 * For booting Linux, the board info and command line data
349 * have to be in the first 8 MB of memory, since this is
350 * the maximum mapped by the Linux kernel during initialization.
351 */
352#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
353/*-----------------------------------------------------------------------
354 * FLASH organization
355 */
356#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
357#define CFG_MAX_FLASH_SECT 20 /* max number of sectors on one chip */
358
359#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
360#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
361
362/*-----------------------------------------------------------------------
363 * Cache Configuration
364 */
365#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
366#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
367# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
368#endif
369
370
371/*
372 * Internal Definitions
373 *
374 * Boot Flags
375 */
376#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
377#define BOOTFLAG_WARM 0x02 /* Software reboot */
378
379
380/* values according to the manual */
381
382#define CONFIG_DRAM_50MHZ 1
383#define CONFIG_SDRAM_50MHZ
384
385#undef NR_8259_INTS
386#define NR_8259_INTS 1
387
388
389#define CONFIG_DISK_SPINUP_TIME 1000000
390
391
392#endif /* __CONFIG_H */