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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Wenyou Yang2c62c562015-11-04 14:25:13 +08002/*
3 * Atmel PIO4 device driver
4 *
5 * Copyright (C) 2015 Atmel Corporation
6 * Wenyou.Yang <wenyou.yang@atmel.com>
Wenyou Yang2c62c562015-11-04 14:25:13 +08007 */
8#include <common.h>
Wenyou Yangee3311d2016-07-20 17:16:26 +08009#include <clk.h>
Wenyou Yang2c62c562015-11-04 14:25:13 +080010#include <dm.h>
Wenyou Yangee3311d2016-07-20 17:16:26 +080011#include <fdtdec.h>
Simon Glass336d4612020-02-03 07:36:16 -070012#include <malloc.h>
Wenyou Yang2c62c562015-11-04 14:25:13 +080013#include <asm/arch/hardware.h>
Simon Glass401d1c42020-10-30 21:38:53 -060014#include <asm/global_data.h>
Wenyou Yangee3311d2016-07-20 17:16:26 +080015#include <asm/gpio.h>
Simon Glasscd93d622020-05-10 11:40:13 -060016#include <linux/bitops.h>
Wenyou Yang2c62c562015-11-04 14:25:13 +080017#include <mach/gpio.h>
18#include <mach/atmel_pio4.h>
19
Wenyou Yangee3311d2016-07-20 17:16:26 +080020DECLARE_GLOBAL_DATA_PTR;
21
Wenyou Yang2c62c562015-11-04 14:25:13 +080022static struct atmel_pio4_port *atmel_pio4_port_base(u32 port)
23{
24 struct atmel_pio4_port *base = NULL;
25
26 switch (port) {
27 case AT91_PIO_PORTA:
28 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOA;
29 break;
30 case AT91_PIO_PORTB:
31 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOB;
32 break;
33 case AT91_PIO_PORTC:
34 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOC;
35 break;
36 case AT91_PIO_PORTD:
37 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOD;
38 break;
Mihai Sainc1cadac2022-05-25 13:32:08 +030039#if (ATMEL_PIO_PORTS > 4)
40 case AT91_PIO_PORTE:
41 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOE;
42 break;
43#endif
Wenyou Yang2c62c562015-11-04 14:25:13 +080044 default:
45 printf("Error: Atmel PIO4: Failed to get PIO base of port#%d!\n",
46 port);
47 break;
48 }
49
50 return base;
51}
52
53static int atmel_pio4_config_io_func(u32 port, u32 pin,
Ludovic Desroches8ee54672018-04-24 10:16:01 +030054 u32 func, u32 config)
Wenyou Yang2c62c562015-11-04 14:25:13 +080055{
56 struct atmel_pio4_port *port_base;
57 u32 reg, mask;
58
Wenyou Yang46ed9382016-07-20 17:16:25 +080059 if (pin >= ATMEL_PIO_NPINS_PER_BANK)
Simon Glass7c843192017-09-17 16:54:53 -060060 return -EINVAL;
Wenyou Yang2c62c562015-11-04 14:25:13 +080061
62 port_base = atmel_pio4_port_base(port);
63 if (!port_base)
Simon Glass7c843192017-09-17 16:54:53 -060064 return -EINVAL;
Wenyou Yang2c62c562015-11-04 14:25:13 +080065
66 mask = 1 << pin;
67 reg = func;
Ludovic Desroches8ee54672018-04-24 10:16:01 +030068 reg |= config;
Wenyou Yang2c62c562015-11-04 14:25:13 +080069
70 writel(mask, &port_base->mskr);
71 writel(reg, &port_base->cfgr);
72
73 return 0;
74}
75
Ludovic Desroches8ee54672018-04-24 10:16:01 +030076int atmel_pio4_set_gpio(u32 port, u32 pin, u32 config)
Wenyou Yang2c62c562015-11-04 14:25:13 +080077{
78 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +080079 ATMEL_PIO_CFGR_FUNC_GPIO,
Ludovic Desroches8ee54672018-04-24 10:16:01 +030080 config);
Wenyou Yang2c62c562015-11-04 14:25:13 +080081}
82
Ludovic Desroches8ee54672018-04-24 10:16:01 +030083int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 config)
Wenyou Yang2c62c562015-11-04 14:25:13 +080084{
85 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +080086 ATMEL_PIO_CFGR_FUNC_PERIPH_A,
Ludovic Desroches8ee54672018-04-24 10:16:01 +030087 config);
Wenyou Yang2c62c562015-11-04 14:25:13 +080088}
89
Ludovic Desroches8ee54672018-04-24 10:16:01 +030090int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 config)
Wenyou Yang2c62c562015-11-04 14:25:13 +080091{
92 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +080093 ATMEL_PIO_CFGR_FUNC_PERIPH_B,
Ludovic Desroches8ee54672018-04-24 10:16:01 +030094 config);
Wenyou Yang2c62c562015-11-04 14:25:13 +080095}
96
Ludovic Desroches8ee54672018-04-24 10:16:01 +030097int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 config)
Wenyou Yang2c62c562015-11-04 14:25:13 +080098{
99 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +0800100 ATMEL_PIO_CFGR_FUNC_PERIPH_C,
Ludovic Desroches8ee54672018-04-24 10:16:01 +0300101 config);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800102}
103
Ludovic Desroches8ee54672018-04-24 10:16:01 +0300104int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 config)
Wenyou Yang2c62c562015-11-04 14:25:13 +0800105{
106 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +0800107 ATMEL_PIO_CFGR_FUNC_PERIPH_D,
Ludovic Desroches8ee54672018-04-24 10:16:01 +0300108 config);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800109}
110
Ludovic Desroches8ee54672018-04-24 10:16:01 +0300111int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 config)
Wenyou Yang2c62c562015-11-04 14:25:13 +0800112{
113 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +0800114 ATMEL_PIO_CFGR_FUNC_PERIPH_E,
Ludovic Desroches8ee54672018-04-24 10:16:01 +0300115 config);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800116}
117
Ludovic Desroches8ee54672018-04-24 10:16:01 +0300118int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 config)
Wenyou Yang2c62c562015-11-04 14:25:13 +0800119{
120 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +0800121 ATMEL_PIO_CFGR_FUNC_PERIPH_F,
Ludovic Desroches8ee54672018-04-24 10:16:01 +0300122 config);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800123}
124
Ludovic Desroches8ee54672018-04-24 10:16:01 +0300125int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 config)
Wenyou Yang2c62c562015-11-04 14:25:13 +0800126{
127 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +0800128 ATMEL_PIO_CFGR_FUNC_PERIPH_G,
Ludovic Desroches8ee54672018-04-24 10:16:01 +0300129 config);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800130}
131
132int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value)
133{
134 struct atmel_pio4_port *port_base;
135 u32 reg, mask;
136
Wenyou Yang46ed9382016-07-20 17:16:25 +0800137 if (pin >= ATMEL_PIO_NPINS_PER_BANK)
Simon Glass7c843192017-09-17 16:54:53 -0600138 return -EINVAL;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800139
140 port_base = atmel_pio4_port_base(port);
141 if (!port_base)
Simon Glass7c843192017-09-17 16:54:53 -0600142 return -EINVAL;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800143
144 mask = 0x01 << pin;
Wenyou Yang46ed9382016-07-20 17:16:25 +0800145 reg = ATMEL_PIO_CFGR_FUNC_GPIO | ATMEL_PIO_DIR_MASK;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800146
147 writel(mask, &port_base->mskr);
148 writel(reg, &port_base->cfgr);
149
150 if (value)
151 writel(mask, &port_base->sodr);
152 else
153 writel(mask, &port_base->codr);
154
155 return 0;
156}
157
158int atmel_pio4_get_pio_input(u32 port, u32 pin)
159{
160 struct atmel_pio4_port *port_base;
161 u32 reg, mask;
162
Wenyou Yang46ed9382016-07-20 17:16:25 +0800163 if (pin >= ATMEL_PIO_NPINS_PER_BANK)
Simon Glass7c843192017-09-17 16:54:53 -0600164 return -EINVAL;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800165
166 port_base = atmel_pio4_port_base(port);
167 if (!port_base)
Simon Glass7c843192017-09-17 16:54:53 -0600168 return -EINVAL;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800169
170 mask = 0x01 << pin;
Wenyou Yang46ed9382016-07-20 17:16:25 +0800171 reg = ATMEL_PIO_CFGR_FUNC_GPIO;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800172
173 writel(mask, &port_base->mskr);
174 writel(reg, &port_base->cfgr);
175
176 return (readl(&port_base->pdsr) & mask) ? 1 : 0;
177}
178
Simon Glassbcee8d62019-12-06 21:41:35 -0700179#if CONFIG_IS_ENABLED(DM_GPIO)
Wenyou Yangee3311d2016-07-20 17:16:26 +0800180
Eugen Hristeve1038ac2021-04-07 11:39:28 +0300181/**
182 * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct
183 * @nbanks: number of PIO banks
184 * @last_bank_count: number of lines in the last bank (can be less than
185 * the rest of the banks).
186 */
Wenyou Yangee3311d2016-07-20 17:16:26 +0800187struct atmel_pioctrl_data {
188 u32 nbanks;
Eugen Hristeve1038ac2021-04-07 11:39:28 +0300189 u32 last_bank_count;
Wenyou Yangee3311d2016-07-20 17:16:26 +0800190};
191
Simon Glass8a8d24b2020-12-03 16:55:23 -0700192struct atmel_pio4_plat {
Wenyou Yangee3311d2016-07-20 17:16:26 +0800193 struct atmel_pio4_port *reg_base;
194};
195
196static struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev,
197 u32 bank)
198{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700199 struct atmel_pio4_plat *plat = dev_get_plat(dev);
Wenyou Yangee3311d2016-07-20 17:16:26 +0800200 struct atmel_pio4_port *port_base =
201 (struct atmel_pio4_port *)((u32)plat->reg_base +
202 ATMEL_PIO_BANK_OFFSET * bank);
203
204 return port_base;
205}
206
Wenyou Yang2c62c562015-11-04 14:25:13 +0800207static int atmel_pio4_direction_input(struct udevice *dev, unsigned offset)
208{
Wenyou Yangee3311d2016-07-20 17:16:26 +0800209 u32 bank = ATMEL_PIO_BANK(offset);
210 u32 line = ATMEL_PIO_LINE(offset);
211 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
212 u32 mask = BIT(line);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800213
214 writel(mask, &port_base->mskr);
Wenyou Yangee3311d2016-07-20 17:16:26 +0800215
216 clrbits_le32(&port_base->cfgr,
217 ATMEL_PIO_CFGR_FUNC_MASK | ATMEL_PIO_DIR_MASK);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800218
219 return 0;
220}
221
222static int atmel_pio4_direction_output(struct udevice *dev,
223 unsigned offset, int value)
224{
Wenyou Yangee3311d2016-07-20 17:16:26 +0800225 u32 bank = ATMEL_PIO_BANK(offset);
226 u32 line = ATMEL_PIO_LINE(offset);
227 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
228 u32 mask = BIT(line);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800229
230 writel(mask, &port_base->mskr);
Wenyou Yangee3311d2016-07-20 17:16:26 +0800231
232 clrsetbits_le32(&port_base->cfgr,
233 ATMEL_PIO_CFGR_FUNC_MASK, ATMEL_PIO_DIR_MASK);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800234
235 if (value)
236 writel(mask, &port_base->sodr);
237 else
238 writel(mask, &port_base->codr);
239
240 return 0;
241}
242
243static int atmel_pio4_get_value(struct udevice *dev, unsigned offset)
244{
Wenyou Yangee3311d2016-07-20 17:16:26 +0800245 u32 bank = ATMEL_PIO_BANK(offset);
246 u32 line = ATMEL_PIO_LINE(offset);
247 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
248 u32 mask = BIT(line);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800249
250 return (readl(&port_base->pdsr) & mask) ? 1 : 0;
251}
252
253static int atmel_pio4_set_value(struct udevice *dev,
254 unsigned offset, int value)
255{
Wenyou Yangee3311d2016-07-20 17:16:26 +0800256 u32 bank = ATMEL_PIO_BANK(offset);
257 u32 line = ATMEL_PIO_LINE(offset);
258 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
259 u32 mask = BIT(line);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800260
261 if (value)
262 writel(mask, &port_base->sodr);
263 else
264 writel(mask, &port_base->codr);
265
266 return 0;
267}
268
269static int atmel_pio4_get_function(struct udevice *dev, unsigned offset)
270{
Wenyou Yangee3311d2016-07-20 17:16:26 +0800271 u32 bank = ATMEL_PIO_BANK(offset);
272 u32 line = ATMEL_PIO_LINE(offset);
273 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
274 u32 mask = BIT(line);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800275
276 writel(mask, &port_base->mskr);
277
278 return (readl(&port_base->cfgr) &
Wenyou Yang46ed9382016-07-20 17:16:25 +0800279 ATMEL_PIO_DIR_MASK) ? GPIOF_OUTPUT : GPIOF_INPUT;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800280}
281
282static const struct dm_gpio_ops atmel_pio4_ops = {
283 .direction_input = atmel_pio4_direction_input,
284 .direction_output = atmel_pio4_direction_output,
285 .get_value = atmel_pio4_get_value,
286 .set_value = atmel_pio4_set_value,
287 .get_function = atmel_pio4_get_function,
288};
289
Wenyou Yangee3311d2016-07-20 17:16:26 +0800290static int atmel_pio4_bind(struct udevice *dev)
291{
Simon Glass79fc0c72017-05-17 17:18:06 -0600292 return dm_scan_fdt_dev(dev);
Wenyou Yangee3311d2016-07-20 17:16:26 +0800293}
294
Wenyou Yang2c62c562015-11-04 14:25:13 +0800295static int atmel_pio4_probe(struct udevice *dev)
296{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700297 struct atmel_pio4_plat *plat = dev_get_plat(dev);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800298 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
Wenyou Yangee3311d2016-07-20 17:16:26 +0800299 struct atmel_pioctrl_data *pioctrl_data;
Wenyou Yangee3311d2016-07-20 17:16:26 +0800300 struct clk clk;
301 fdt_addr_t addr_base;
302 u32 nbanks;
Wenyou Yangee3311d2016-07-20 17:16:26 +0800303 int ret;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800304
Wenyou Yangee3311d2016-07-20 17:16:26 +0800305 ret = clk_get_by_index(dev, 0, &clk);
306 if (ret)
307 return ret;
308
Wenyou Yangee3311d2016-07-20 17:16:26 +0800309 ret = clk_enable(&clk);
310 if (ret)
311 return ret;
312
313 clk_free(&clk);
314
Masahiro Yamada25484932020-07-17 14:36:48 +0900315 addr_base = dev_read_addr(dev);
Wenyou Yangee3311d2016-07-20 17:16:26 +0800316 if (addr_base == FDT_ADDR_T_NONE)
317 return -EINVAL;
318
319 plat->reg_base = (struct atmel_pio4_port *)addr_base;
320
321 pioctrl_data = (struct atmel_pioctrl_data *)dev_get_driver_data(dev);
322 nbanks = pioctrl_data->nbanks;
323
Simon Glasse160f7d2017-01-17 16:52:55 -0700324 uc_priv->bank_name = fdt_get_name(gd->fdt_blob, dev_of_offset(dev),
325 NULL);
Wenyou Yangee3311d2016-07-20 17:16:26 +0800326 uc_priv->gpio_count = nbanks * ATMEL_PIO_NPINS_PER_BANK;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800327
Eugen Hristeve1038ac2021-04-07 11:39:28 +0300328 /* if last bank has limited number of pins, adjust accordingly */
329 if (pioctrl_data->last_bank_count != ATMEL_PIO_NPINS_PER_BANK) {
330 uc_priv->gpio_count -= ATMEL_PIO_NPINS_PER_BANK;
331 uc_priv->gpio_count += pioctrl_data->last_bank_count;
332 }
333
Wenyou Yang2c62c562015-11-04 14:25:13 +0800334 return 0;
335}
336
Wenyou Yangee3311d2016-07-20 17:16:26 +0800337/*
338 * The number of banks can be different from a SoC to another one.
339 * We can have up to 16 banks.
340 */
341static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
342 .nbanks = 4,
Eugen Hristeve1038ac2021-04-07 11:39:28 +0300343 .last_bank_count = ATMEL_PIO_NPINS_PER_BANK,
344};
345
346static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {
347 .nbanks = 5,
348 .last_bank_count = 8, /* 5th bank has only 8 lines on sama7g5 */
Wenyou Yangee3311d2016-07-20 17:16:26 +0800349};
350
351static const struct udevice_id atmel_pio4_ids[] = {
352 {
353 .compatible = "atmel,sama5d2-gpio",
354 .data = (ulong)&atmel_sama5d2_pioctrl_data,
Eugen Hristeve1038ac2021-04-07 11:39:28 +0300355 }, {
356 .compatible = "microchip,sama7g5-gpio",
357 .data = (ulong)&microchip_sama7g5_pioctrl_data,
Wenyou Yangee3311d2016-07-20 17:16:26 +0800358 },
359 {}
360};
361
Wenyou Yang2c62c562015-11-04 14:25:13 +0800362U_BOOT_DRIVER(gpio_atmel_pio4) = {
363 .name = "gpio_atmel_pio4",
364 .id = UCLASS_GPIO,
365 .ops = &atmel_pio4_ops,
366 .probe = atmel_pio4_probe,
Wenyou Yangee3311d2016-07-20 17:16:26 +0800367 .bind = atmel_pio4_bind,
368 .of_match = atmel_pio4_ids,
Simon Glass8a8d24b2020-12-03 16:55:23 -0700369 .plat_auto = sizeof(struct atmel_pio4_plat),
Wenyou Yang2c62c562015-11-04 14:25:13 +0800370};
Wenyou Yangee3311d2016-07-20 17:16:26 +0800371
Wenyou Yang2c62c562015-11-04 14:25:13 +0800372#endif