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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / c1e1dbb8f3e8e278c61d7bfc3a41973c7e87377c / . / arch / powerpc / dts / p3041ds.dts
blob: b984ddea9856fbd6a32e0c671585477de1aa87c1 [file] [log] [blame]
Hou Zhiqiangbebc0722019-08-20 09:35:31 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * P3041DS Device Tree Source
4 *
5 * Copyright 2010 - 2015 Freescale Semiconductor Inc.
Madalin Bucurfb1b2e12020-04-30 16:00:09 +0300[diff] [blame]6 * Copyright 2019-2020 NXP
Hou Zhiqiangbebc0722019-08-20 09:35:31 +0000[diff] [blame]7 */
8
9/include/ "p3041.dtsi"
10
11/ {
12 model = "fsl,P3041DS";
13 compatible = "fsl,P3041DS";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&mpic>;
17
Madalin Bucurfb1b2e12020-04-30 16:00:09 +0300[diff] [blame]18 aliases{
19 phy_rgmii_0 = &phy_rgmii_0;
20 phy_rgmii_1 = &phy_rgmii_1;
21 phy_sgmii_1c = &phy_sgmii_1c;
22 phy_sgmii_1d = &phy_sgmii_1d;
23 phy_sgmii_1e = &phy_sgmii_1e;
24 phy_sgmii_1f = &phy_sgmii_1f;
25 phy_xgmii_1 = &phy_xgmii_1;
26 phy_xgmii_2 = &phy_xgmii_2;
27 emi1_rgmii = &hydra_mdio_rgmii;
28 emi1_sgmii = &hydra_mdio_sgmii;
29 emi2_xgmii = &hydra_mdio_xgmii;
30 };
31
32 soc: soc@ffe000000 {
33 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
34 reg = <0xf 0xfe000000 0 0x00001000>;
35 fman@400000{
36 ethernet@e0000 {
37 phy-handle = <&phy_sgmii_1c>;
38 phy-connection-type = "sgmii";
39 };
40
41 ethernet@e2000 {
42 phy-handle = <&phy_sgmii_1d>;
43 phy-connection-type = "sgmii";
44 };
45
46 ethernet@e4000 {
47 phy-handle = <&phy_sgmii_1e>;
48 phy-connection-type = "sgmii";
49 };
50
51 ethernet@e6000 {
52 phy-handle = <&phy_sgmii_1f>;
53 phy-connection-type = "sgmii";
54 };
55
56 ethernet@e8000 {
57 phy-handle = <&phy_rgmii_1>;
58 phy-connection-type = "rgmii";
59 };
60
61 ethernet@f0000 {
62 phy-handle = <&phy_xgmii_1>;
63 phy-connection-type = "xgmii";
64 };
65
66 hydra_mdio_xgmii: mdio@f1000 {
67 status = "disabled";
68
69 phy_xgmii_1: ethernet-phy@4 {
70 compatible = "ethernet-phy-ieee802.3-c45";
71 reg = <0x4>;
72 };
73
74 phy_xgmii_2: ethernet-phy@0 {
75 compatible = "ethernet-phy-ieee802.3-c45";
76 reg = <0x0>;
77 };
78 };
79 };
80 };
81
82 lbc: localbus@ffe124000 {
83 reg = <0xf 0xfe124000 0 0x1000>;
84 ranges = <0 0 0xf 0xe8000000 0x08000000
85 2 0 0xf 0xffa00000 0x00040000
86 3 0 0xf 0xffdf0000 0x00008000>;
87
88 board-control@3,0 {
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis";
92 reg = <3 0 0x30>;
93 ranges = <0 3 0 0x30>;
94
95 mdio-mux-emi1 {
96 #address-cells = <1>;
97 #size-cells = <0>;
98 compatible = "mdio-mux-mmioreg", "mdio-mux";
99 mdio-parent-bus = <&mdio0>;
100 reg = <9 1>;
101 mux-mask = <0x78>;
102
103 hydra_mdio_rgmii: rgmii-mdio@8 {
104 #address-cells = <1>;
105 #size-cells = <0>;
106 reg = <8>;
107 status = "disabled";
108
109 phy_rgmii_0: ethernet-phy@0 {
110 reg = <0x0>;
111 };
112
113 phy_rgmii_1: ethernet-phy@1 {
114 reg = <0x1>;
115 };
116 };
117
118 hydra_mdio_sgmii: sgmii-mdio@28 {
119 #address-cells = <1>;
120 #size-cells = <0>;
121 reg = <0x28>;
122 status = "disabled";
123
124 phy_sgmii_1c: ethernet-phy@1c {
125 reg = <0x1c>;
126 };
127
128 phy_sgmii_1d: ethernet-phy@1d {
129 reg = <0x1d>;
130 };
131
132 phy_sgmii_1e: ethernet-phy@1e {
133 reg = <0x1e>;
134 };
135
136 phy_sgmii_1f: ethernet-phy@1f {
137 reg = <0x1f>;
138 };
139 };
140 };
141 };
142 };
Hou Zhiqiangbebc0722019-08-20 09:35:31 +0000[diff] [blame]143};
Madalin Bucurfb1b2e12020-04-30 16:00:09 +0300[diff] [blame]144
145/include/ "p3041si-post.dtsi"