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wdenkb6e4c402004-01-02 16:05:07 +00001/*
2 * (C) Copyright 2003
3 * Denis Peter d.peter@mpl.ch
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation,
21 */
22
23/*
24 * File: PATI.h
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*
31 * High Level Configuration Options
32 */
33
34#define CONFIG_MPC555 1 /* This is an MPC555 CPU */
35#define CONFIG_PATI 1 /* ...On a PATI board */
36/* Serial Console Configuration */
37#define CONFIG_5xx_CONS_SCI1
38#undef CONFIG_5xx_CONS_SCI2
39
40#define CONFIG_BAUDRATE 9600
41
wdenkb6e4c402004-01-02 16:05:07 +000042
Jon Loeligeracf02692007-07-08 14:49:44 -050043/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050044 * BOOTP options
45 */
46#define CONFIG_BOOTP_BOOTFILESIZE
47#define CONFIG_BOOTP_BOOTPATH
48#define CONFIG_BOOTP_GATEWAY
49#define CONFIG_BOOTP_HOSTNAME
50
51
52/*
Jon Loeligeracf02692007-07-08 14:49:44 -050053 * Command line configuration.
54 */
55#define CONFIG_CMD_MEMORY
56#define CONFIG_CMD_LOADB
57#define CONFIG_CMD_REGINFO
58#define CONFIG_CMD_FLASH
59#define CONFIG_CMD_LOADS
60#define CONFIG_CMD_ENV
61#define CONFIG_CMD_REGINFO
62#define CONFIG_CMD_BDI
63#define CONFIG_CMD_CONSOLE
64#define CONFIG_CMD_RUN
65#define CONFIG_CMD_BSP
66#define CONFIG_CMD_IMI
67#define CONFIG_CMD_EEPROM
68#define CONFIG_CMD_IRQ
69#define CONFIG_CMD_MISC
70
wdenkb6e4c402004-01-02 16:05:07 +000071
72#if 0
73#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
74#else
75#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
76#endif
77#define CONFIG_BOOTCOMMAND "" /* autoboot command */
78
79#define CONFIG_BOOTARGS "" /* */
80
81#define CONFIG_WATCHDOG /* turn on platform specific watchdog */
82
wdenk3a473b22004-01-03 00:43:19 +000083/*#define CONFIG_STATUS_LED 1 */ /* Enable status led */
wdenkb6e4c402004-01-02 16:05:07 +000084
85#define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */
86
87/*
88 * Miscellaneous configurable options
89 */
90#define CFG_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
91#define CONFIG_PREBOOT
92
93#define CFG_LONGHELP /* undef to save memory */
94#define CFG_PROMPT "pati=> " /* Monitor Command Prompt */
Jon Loeligeracf02692007-07-08 14:49:44 -050095#if defined(CONFIG_CMD_KGDB)
wdenkb6e4c402004-01-02 16:05:07 +000096#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
97#else
98#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
99#endif
100#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
101#define CFG_MAXARGS 16 /* max number of command args */
102#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
103
104#define CFG_MEMTEST_START 0x00010000 /* memtest works on */
105#define CFG_MEMTEST_END 0x00A00000 /* 10 MB in SRAM */
106
107#define CFG_LOAD_ADDR 0x100000 /* default load address */
108
109#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */
110
111#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 }
112
113
114/***********************************************************************
115 * Last Stage Init
116 ***********************************************************************/
117#define CONFIG_LAST_STAGE_INIT
118
119/*
120 * Low Level Configuration Settings
121 */
122
123/*
124 * Internal Memory Mapped (This is not the IMMR content)
125 */
126#define CFG_IMMR 0x01C00000 /* Physical start adress of internal memory map */
127
128/*
129 * Definitions for initial stack pointer and data area
130 */
131#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */
132#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */
133#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial global data */
134#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */
135#define CFG_INIT_SP_ADDR (CFG_IMMR + 0x03fa000) /* Physical start adress of inital stack */
136/*
137 * Start addresses for the final memory configuration
138 * Please note that CFG_SDRAM_BASE _must_ start at 0
139 */
140#define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */
141#define CFG_FLASH_BASE 0xffC00000 /* External flash */
142#define PCI_BASE 0x03000000 /* PCI Base (CS2) */
143#define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */
144#define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */
145
146#define CFG_MONITOR_BASE 0xFFF00000
147/* CFG_FLASH_BASE */ /* TEXT_BASE is defined in the board config.mk file. */
148 /* This adress is given to the linker with -Ttext to */
149 /* locate the text section at this adress. */
150#define CFG_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */
151#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
152
wdenkb6e4c402004-01-02 16:05:07 +0000153#define CFG_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */
154
155/*
156 * For booting Linux, the board info and command line data
157 * have to be in the first 8 MB of memory, since this is
158 * the maximum mapped by the Linux kernel during initialization.
159 */
160#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
161
162
163/*-----------------------------------------------------------------------
164 * FLASH organization
165 *-----------------------------------------------------------------------
166 *
167 */
168
169#define CFG_MAX_FLASH_BANKS 1 /* Max number of memory banks */
170#define CFG_MAX_FLASH_SECT 128 /* Max number of sectors on one chip */
171#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
172#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */
173
174
175#define CFG_ENV_IS_IN_EEPROM
176#ifdef CFG_ENV_IS_IN_EEPROM
177#define CFG_ENV_OFFSET 0
178#define CFG_ENV_SIZE 2048
179#endif
180
181#undef CFG_ENV_IS_IN_FLASH
182#ifdef CFG_ENV_IS_IN_FLASH
183#define CFG_ENV_SIZE 0x00002000 /* Set whole sector as env */
184#define CFG_ENV_OFFSET ((0 - CFG_FLASH_BASE) - CFG_ENV_SIZE) /* Environment starts at this adress */
185#endif
186
187
188#define CONFIG_SPI 1
189#define CFG_SPI_CS_USED 0x09 /* CS0 and CS3 are used */
190#define CFG_SPI_CS_BASE 0x08 /* CS3 is active low */
191#define CFG_SPI_CS_ACT 0x00 /* CS3 is active low */
192/*-----------------------------------------------------------------------
193 * SYPCR - System Protection Control
194 * SYPCR can only be written once after reset!
195 *-----------------------------------------------------------------------
196 * SW Watchdog freeze
197 */
198#undef CONFIG_WATCHDOG
199#if defined(CONFIG_WATCHDOG)
200#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
201 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
202#else
203#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
204 SYPCR_SWP)
205#endif /* CONFIG_WATCHDOG */
206
wdenkb6e4c402004-01-02 16:05:07 +0000207/*-----------------------------------------------------------------------
208 * TBSCR - Time Base Status and Control
209 *-----------------------------------------------------------------------
210 * Clear Reference Interrupt Status, Timebase freezing enabled
211 */
212#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
213
214/*-----------------------------------------------------------------------
215 * PISCR - Periodic Interrupt Status and Control
216 *-----------------------------------------------------------------------
217 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
218 */
219#define CFG_PISCR (PISCR_PS | PISCR_PITF)
220
221/*-----------------------------------------------------------------------
222 * SCCR - System Clock and reset Control Register
223 *-----------------------------------------------------------------------
224 * Set clock output, timebase and RTC source and divider,
225 * power management and some other internal clocks
226 */
227#define SCCR_MASK SCCR_EBDF00
228#define CFG_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \
229 SCCR_COM01 | SCCR_DFNL000 | SCCR_DFNH000)
230
231/*-----------------------------------------------------------------------
232 * SIUMCR - SIU Module Configuration
233 *-----------------------------------------------------------------------
234 * Data show cycle
235 */
236#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */
237
238/*-----------------------------------------------------------------------
239 * PLPRCR - PLL, Low-Power, and Reset Control Register
240 *-----------------------------------------------------------------------
241 * Set all bits to 40 Mhz
242 *
243 */
244#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */
245
246
247#define CFG_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0)
248
249/*-----------------------------------------------------------------------
250 * UMCR - UIMB Module Configuration Register
251 *-----------------------------------------------------------------------
252 *
253 */
254#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */
255
256/*-----------------------------------------------------------------------
257 * ICTRL - I-Bus Support Control Register
258 */
259#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */
260
261/*-----------------------------------------------------------------------
262 * USIU - Memory Controller Register
263 *-----------------------------------------------------------------------
264 */
265#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA)
266#define CFG_OR0_PRELIM (0xffc00000) /* SCY is not used if external TA is set */
267/* SDRAM */
268#define CFG_BR1_PRELIM (CFG_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
269#define CFG_OR1_PRELIM (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */
270/* PCI */
271#define CFG_BR2_PRELIM (PCI_BASE | BR_V | BR_PS_32 | BR_SETA)
272#define CFG_OR2_PRELIM (OR_ADDR_MK_FF)
273/* config registers: */
274#define CFG_BR3_PRELIM (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
275#define CFG_OR3_PRELIM (0xffff0000)
276
277#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* We don't realign the flash */
278
279/*-----------------------------------------------------------------------
280 * DER - Timer Decrementer
281 *-----------------------------------------------------------------------
282 * Initialise to zero
283 */
284#define CFG_DER 0x00000000
285
286
287/*
288 * Internal Definitions
289 *
290 * Boot Flags
291 */
292#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
293#define BOOTFLAG_WARM 0x02 /* Software reboot */
294
295
296#define VERSION_TAG "released"
297#define CONFIG_ISO_STRING "MEV-10084-001"
298
299#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
300
301#endif /* __CONFIG_H */