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Masahiro Yamada10ee0a62015-08-28 22:33:14 +09001/*
Masahiro Yamada52159d22016-10-07 16:43:00 +09002 * Device Tree Source for UniPhier Pro5 SoC
Masahiro Yamada10ee0a62015-08-28 22:33:14 +09003 *
Masahiro Yamada52159d22016-10-07 16:43:00 +09004 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada10ee0a62015-08-28 22:33:14 +09006 *
7 * SPDX-License-Identifier: GPL-2.0+ X11
8 */
9
Masahiro Yamadacd622142016-12-05 18:31:39 +090010/include/ "skeleton.dtsi"
Masahiro Yamada10ee0a62015-08-28 22:33:14 +090011
12/ {
Masahiro Yamada52159d22016-10-07 16:43:00 +090013 compatible = "socionext,uniphier-pro5";
Masahiro Yamada10ee0a62015-08-28 22:33:14 +090014
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
Masahiro Yamada10ee0a62015-08-28 22:33:14 +090018
19 cpu@0 {
20 device_type = "cpu";
21 compatible = "arm,cortex-a9";
22 reg = <0>;
Masahiro Yamadacd622142016-12-05 18:31:39 +090023 clocks = <&sys_clk 32>;
Masahiro Yamada52159d22016-10-07 16:43:00 +090024 enable-method = "psci";
Masahiro Yamada4e1f81d2015-12-16 10:54:08 +090025 next-level-cache = <&l2>;
Masahiro Yamadacd622142016-12-05 18:31:39 +090026 operating-points-v2 = <&cpu_opp>;
Masahiro Yamada10ee0a62015-08-28 22:33:14 +090027 };
28
29 cpu@1 {
30 device_type = "cpu";
31 compatible = "arm,cortex-a9";
32 reg = <1>;
Masahiro Yamadacd622142016-12-05 18:31:39 +090033 clocks = <&sys_clk 32>;
Masahiro Yamada52159d22016-10-07 16:43:00 +090034 enable-method = "psci";
Masahiro Yamada4e1f81d2015-12-16 10:54:08 +090035 next-level-cache = <&l2>;
Masahiro Yamadacd622142016-12-05 18:31:39 +090036 operating-points-v2 = <&cpu_opp>;
Masahiro Yamada10ee0a62015-08-28 22:33:14 +090037 };
38 };
39
Masahiro Yamadacd622142016-12-05 18:31:39 +090040 cpu_opp: opp_table {
41 compatible = "operating-points-v2";
42 opp-shared;
43
44 opp@100000000 {
45 opp-hz = /bits/ 64 <100000000>;
46 clock-latency-ns = <300>;
47 };
48 opp@116667000 {
49 opp-hz = /bits/ 64 <116667000>;
50 clock-latency-ns = <300>;
51 };
52 opp@150000000 {
53 opp-hz = /bits/ 64 <150000000>;
54 clock-latency-ns = <300>;
55 };
56 opp@175000000 {
57 opp-hz = /bits/ 64 <175000000>;
58 clock-latency-ns = <300>;
59 };
60 opp@200000000 {
61 opp-hz = /bits/ 64 <200000000>;
62 clock-latency-ns = <300>;
63 };
64 opp@233334000 {
65 opp-hz = /bits/ 64 <233334000>;
66 clock-latency-ns = <300>;
67 };
68 opp@300000000 {
69 opp-hz = /bits/ 64 <300000000>;
70 clock-latency-ns = <300>;
71 };
72 opp@350000000 {
73 opp-hz = /bits/ 64 <350000000>;
74 clock-latency-ns = <300>;
75 };
76 opp@400000000 {
77 opp-hz = /bits/ 64 <400000000>;
78 clock-latency-ns = <300>;
79 };
80 opp@466667000 {
81 opp-hz = /bits/ 64 <466667000>;
82 clock-latency-ns = <300>;
83 };
84 opp@600000000 {
85 opp-hz = /bits/ 64 <600000000>;
86 clock-latency-ns = <300>;
87 };
88 opp@700000000 {
89 opp-hz = /bits/ 64 <700000000>;
90 clock-latency-ns = <300>;
91 };
92 opp@800000000 {
93 opp-hz = /bits/ 64 <800000000>;
94 clock-latency-ns = <300>;
95 };
96 opp@933334000 {
97 opp-hz = /bits/ 64 <933334000>;
98 clock-latency-ns = <300>;
99 };
100 opp@1200000000 {
101 opp-hz = /bits/ 64 <1200000000>;
102 clock-latency-ns = <300>;
103 };
104 opp@1400000000 {
105 opp-hz = /bits/ 64 <1400000000>;
106 clock-latency-ns = <300>;
107 };
108 };
109
110 psci {
111 compatible = "arm,psci-0.2";
112 method = "smc";
113 };
114
Masahiro Yamada10ee0a62015-08-28 22:33:14 +0900115 clocks {
Masahiro Yamadacd622142016-12-05 18:31:39 +0900116 refclk: ref {
117 compatible = "fixed-clock";
118 #clock-cells = <0>;
119 clock-frequency = <20000000>;
120 };
121
Masahiro Yamada10ee0a62015-08-28 22:33:14 +0900122 arm_timer_clk: arm_timer_clk {
123 #clock-cells = <0>;
124 compatible = "fixed-clock";
125 clock-frequency = <50000000>;
126 };
Masahiro Yamadacd622142016-12-05 18:31:39 +0900127 };
Masahiro Yamada10ee0a62015-08-28 22:33:14 +0900128
Masahiro Yamadacd622142016-12-05 18:31:39 +0900129 soc {
130 compatible = "simple-bus";
131 #address-cells = <1>;
132 #size-cells = <1>;
133 ranges;
134 interrupt-parent = <&intc>;
135 u-boot,dm-pre-reloc;
136
137 l2: l2-cache@500c0000 {
138 compatible = "socionext,uniphier-system-cache";
139 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
140 <0x506c0000 0x400>;
141 interrupts = <0 190 4>, <0 191 4>;
142 cache-unified;
143 cache-size = <(2 * 1024 * 1024)>;
144 cache-sets = <512>;
145 cache-line-size = <128>;
146 cache-level = <2>;
147 next-level-cache = <&l3>;
148 };
149
150 l3: l3-cache@500c8000 {
151 compatible = "socionext,uniphier-system-cache";
152 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
153 <0x506c8000 0x400>;
154 interrupts = <0 174 4>, <0 175 4>;
155 cache-unified;
156 cache-size = <(2 * 1024 * 1024)>;
157 cache-sets = <512>;
158 cache-line-size = <256>;
159 cache-level = <3>;
160 };
161
162 serial0: serial@54006800 {
163 compatible = "socionext,uniphier-uart";
164 status = "disabled";
165 reg = <0x54006800 0x40>;
166 interrupts = <0 33 4>;
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_uart0>;
169 clocks = <&peri_clk 0>;
170 clock-frequency = <73728000>;
171 };
172
173 serial1: serial@54006900 {
174 compatible = "socionext,uniphier-uart";
175 status = "disabled";
176 reg = <0x54006900 0x40>;
177 interrupts = <0 35 4>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_uart1>;
180 clocks = <&peri_clk 1>;
181 clock-frequency = <73728000>;
182 };
183
184 serial2: serial@54006a00 {
185 compatible = "socionext,uniphier-uart";
186 status = "disabled";
187 reg = <0x54006a00 0x40>;
188 interrupts = <0 37 4>;
189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_uart2>;
191 clocks = <&peri_clk 2>;
192 clock-frequency = <73728000>;
193 };
194
195 serial3: serial@54006b00 {
196 compatible = "socionext,uniphier-uart";
197 status = "disabled";
198 reg = <0x54006b00 0x40>;
199 interrupts = <0 177 4>;
200 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_uart3>;
202 clocks = <&peri_clk 3>;
203 clock-frequency = <73728000>;
204 };
205
206 port0x: gpio@55000008 {
207 compatible = "socionext,uniphier-gpio";
208 reg = <0x55000008 0x8>;
209 gpio-controller;
210 #gpio-cells = <2>;
211 };
212
213 port1x: gpio@55000010 {
214 compatible = "socionext,uniphier-gpio";
215 reg = <0x55000010 0x8>;
216 gpio-controller;
217 #gpio-cells = <2>;
218 };
219
220 port2x: gpio@55000018 {
221 compatible = "socionext,uniphier-gpio";
222 reg = <0x55000018 0x8>;
223 gpio-controller;
224 #gpio-cells = <2>;
225 };
226
227 port3x: gpio@55000020 {
228 compatible = "socionext,uniphier-gpio";
229 reg = <0x55000020 0x8>;
230 gpio-controller;
231 #gpio-cells = <2>;
232 };
233
234 port4: gpio@55000028 {
235 compatible = "socionext,uniphier-gpio";
236 reg = <0x55000028 0x8>;
237 gpio-controller;
238 #gpio-cells = <2>;
239 };
240
241 port5x: gpio@55000030 {
242 compatible = "socionext,uniphier-gpio";
243 reg = <0x55000030 0x8>;
244 gpio-controller;
245 #gpio-cells = <2>;
246 };
247
248 port6x: gpio@55000038 {
249 compatible = "socionext,uniphier-gpio";
250 reg = <0x55000038 0x8>;
251 gpio-controller;
252 #gpio-cells = <2>;
253 };
254
255 port7x: gpio@55000040 {
256 compatible = "socionext,uniphier-gpio";
257 reg = <0x55000040 0x8>;
258 gpio-controller;
259 #gpio-cells = <2>;
260 };
261
262 port8x: gpio@55000048 {
263 compatible = "socionext,uniphier-gpio";
264 reg = <0x55000048 0x8>;
265 gpio-controller;
266 #gpio-cells = <2>;
267 };
268
269 port9x: gpio@55000050 {
270 compatible = "socionext,uniphier-gpio";
271 reg = <0x55000050 0x8>;
272 gpio-controller;
273 #gpio-cells = <2>;
274 };
275
276 port10x: gpio@55000058 {
277 compatible = "socionext,uniphier-gpio";
278 reg = <0x55000058 0x8>;
279 gpio-controller;
280 #gpio-cells = <2>;
281 };
282
283 port11x: gpio@55000060 {
284 compatible = "socionext,uniphier-gpio";
285 reg = <0x55000060 0x8>;
286 gpio-controller;
287 #gpio-cells = <2>;
288 };
289
290 port12x: gpio@55000068 {
291 compatible = "socionext,uniphier-gpio";
292 reg = <0x55000068 0x8>;
293 gpio-controller;
294 #gpio-cells = <2>;
295 };
296
297 port13x: gpio@55000070 {
298 compatible = "socionext,uniphier-gpio";
299 reg = <0x55000070 0x8>;
300 gpio-controller;
301 #gpio-cells = <2>;
302 };
303
304 port14x: gpio@55000078 {
305 compatible = "socionext,uniphier-gpio";
306 reg = <0x55000078 0x8>;
307 gpio-controller;
308 #gpio-cells = <2>;
309 };
310
311 port17x: gpio@550000a0 {
312 compatible = "socionext,uniphier-gpio";
313 reg = <0x550000a0 0x8>;
314 gpio-controller;
315 #gpio-cells = <2>;
316 };
317
318 port18x: gpio@550000a8 {
319 compatible = "socionext,uniphier-gpio";
320 reg = <0x550000a8 0x8>;
321 gpio-controller;
322 #gpio-cells = <2>;
323 };
324
325 port19x: gpio@550000b0 {
326 compatible = "socionext,uniphier-gpio";
327 reg = <0x550000b0 0x8>;
328 gpio-controller;
329 #gpio-cells = <2>;
330 };
331
332 port20x: gpio@550000b8 {
333 compatible = "socionext,uniphier-gpio";
334 reg = <0x550000b8 0x8>;
335 gpio-controller;
336 #gpio-cells = <2>;
337 };
338
339 port21x: gpio@550000c0 {
340 compatible = "socionext,uniphier-gpio";
341 reg = <0x550000c0 0x8>;
342 gpio-controller;
343 #gpio-cells = <2>;
344 };
345
346 port22x: gpio@550000c8 {
347 compatible = "socionext,uniphier-gpio";
348 reg = <0x550000c8 0x8>;
349 gpio-controller;
350 #gpio-cells = <2>;
351 };
352
353 port23x: gpio@550000d0 {
354 compatible = "socionext,uniphier-gpio";
355 reg = <0x550000d0 0x8>;
356 gpio-controller;
357 #gpio-cells = <2>;
358 };
359
360 port24x: gpio@550000d8 {
361 compatible = "socionext,uniphier-gpio";
362 reg = <0x550000d8 0x8>;
363 gpio-controller;
364 #gpio-cells = <2>;
365 };
366
367 port25x: gpio@550000e0 {
368 compatible = "socionext,uniphier-gpio";
369 reg = <0x550000e0 0x8>;
370 gpio-controller;
371 #gpio-cells = <2>;
372 };
373
374 port26x: gpio@550000e8 {
375 compatible = "socionext,uniphier-gpio";
376 reg = <0x550000e8 0x8>;
377 gpio-controller;
378 #gpio-cells = <2>;
379 };
380
381 port27x: gpio@550000f0 {
382 compatible = "socionext,uniphier-gpio";
383 reg = <0x550000f0 0x8>;
384 gpio-controller;
385 #gpio-cells = <2>;
386 };
387
388 port28x: gpio@550000f8 {
389 compatible = "socionext,uniphier-gpio";
390 reg = <0x550000f8 0x8>;
391 gpio-controller;
392 #gpio-cells = <2>;
393 };
394
395 port29x: gpio@55000100 {
396 compatible = "socionext,uniphier-gpio";
397 reg = <0x55000100 0x8>;
398 gpio-controller;
399 #gpio-cells = <2>;
400 };
401
402 port30x: gpio@55000108 {
403 compatible = "socionext,uniphier-gpio";
404 reg = <0x55000108 0x8>;
405 gpio-controller;
406 #gpio-cells = <2>;
407 };
408
409 i2c0: i2c@58780000 {
410 compatible = "socionext,uniphier-fi2c";
411 status = "disabled";
412 reg = <0x58780000 0x80>;
413 #address-cells = <1>;
414 #size-cells = <0>;
415 interrupts = <0 41 4>;
416 pinctrl-names = "default";
417 pinctrl-0 = <&pinctrl_i2c0>;
418 clocks = <&peri_clk 4>;
419 clock-frequency = <100000>;
420 };
421
422 i2c1: i2c@58781000 {
423 compatible = "socionext,uniphier-fi2c";
424 status = "disabled";
425 reg = <0x58781000 0x80>;
426 #address-cells = <1>;
427 #size-cells = <0>;
428 interrupts = <0 42 4>;
429 pinctrl-names = "default";
430 pinctrl-0 = <&pinctrl_i2c1>;
431 clocks = <&peri_clk 5>;
432 clock-frequency = <100000>;
433 };
434
435 i2c2: i2c@58782000 {
436 compatible = "socionext,uniphier-fi2c";
437 status = "disabled";
438 reg = <0x58782000 0x80>;
439 #address-cells = <1>;
440 #size-cells = <0>;
441 interrupts = <0 43 4>;
442 pinctrl-names = "default";
443 pinctrl-0 = <&pinctrl_i2c2>;
444 clocks = <&peri_clk 6>;
445 clock-frequency = <100000>;
446 };
447
448 i2c3: i2c@58783000 {
449 compatible = "socionext,uniphier-fi2c";
450 status = "disabled";
451 reg = <0x58783000 0x80>;
452 #address-cells = <1>;
453 #size-cells = <0>;
454 interrupts = <0 44 4>;
455 pinctrl-names = "default";
456 pinctrl-0 = <&pinctrl_i2c3>;
457 clocks = <&peri_clk 7>;
458 clock-frequency = <100000>;
459 };
460
461 /* i2c4 does not exist */
462
463 /* chip-internal connection for DMD */
464 i2c5: i2c@58785000 {
465 compatible = "socionext,uniphier-fi2c";
466 reg = <0x58785000 0x80>;
467 #address-cells = <1>;
468 #size-cells = <0>;
469 interrupts = <0 25 4>;
470 clocks = <&peri_clk 9>;
471 clock-frequency = <400000>;
472 };
473
474 /* chip-internal connection for HDMI */
475 i2c6: i2c@58786000 {
476 compatible = "socionext,uniphier-fi2c";
477 reg = <0x58786000 0x80>;
478 #address-cells = <1>;
479 #size-cells = <0>;
480 interrupts = <0 26 4>;
481 clocks = <&peri_clk 10>;
482 clock-frequency = <400000>;
483 };
484
485 system_bus: system-bus@58c00000 {
486 compatible = "socionext,uniphier-system-bus";
487 status = "disabled";
488 reg = <0x58c00000 0x400>;
489 #address-cells = <2>;
490 #size-cells = <1>;
491 pinctrl-names = "default";
492 pinctrl-0 = <&pinctrl_system_bus>;
493 };
494
495 smpctrl@59800000 {
496 compatible = "socionext,uniphier-smpctrl";
497 reg = <0x59801000 0x400>;
498 };
499
500 sdctrl@59810000 {
501 compatible = "socionext,uniphier-pro5-sdctrl",
502 "simple-mfd", "syscon";
503 reg = <0x59810000 0x800>;
504 u-boot,dm-pre-reloc;
505
506 sd_clk: clock {
507 compatible = "socionext,uniphier-pro5-sd-clock";
508 #clock-cells = <1>;
509 };
510
511 sd_rst: reset {
512 compatible = "socionext,uniphier-pro5-sd-reset";
513 #reset-cells = <1>;
514 };
515 };
516
517 perictrl@59820000 {
518 compatible = "socionext,uniphier-pro5-perictrl",
519 "simple-mfd", "syscon";
520 reg = <0x59820000 0x200>;
521
522 peri_clk: clock {
523 compatible = "socionext,uniphier-pro5-peri-clock";
524 #clock-cells = <1>;
525 };
526
527 peri_rst: reset {
528 compatible = "socionext,uniphier-pro5-peri-reset";
529 #reset-cells = <1>;
530 };
531 };
532
533 soc-glue@5f800000 {
534 compatible = "socionext,uniphier-pro5-soc-glue",
535 "simple-mfd", "syscon";
536 reg = <0x5f800000 0x2000>;
537 u-boot,dm-pre-reloc;
538
539 pinctrl: pinctrl {
540 compatible = "socionext,uniphier-pro5-pinctrl";
541 u-boot,dm-pre-reloc;
542 };
543 };
544
545 aidet@5fc20000 {
546 compatible = "simple-mfd", "syscon";
547 reg = <0x5fc20000 0x200>;
548 };
549
550 timer@60000200 {
551 compatible = "arm,cortex-a9-global-timer";
552 reg = <0x60000200 0x20>;
553 interrupts = <1 11 0x304>;
554 clocks = <&arm_timer_clk>;
555 };
556
557 timer@60000600 {
558 compatible = "arm,cortex-a9-twd-timer";
559 reg = <0x60000600 0x20>;
560 interrupts = <1 13 0x304>;
561 clocks = <&arm_timer_clk>;
562 };
563
564 intc: interrupt-controller@60001000 {
565 compatible = "arm,cortex-a9-gic";
566 reg = <0x60001000 0x1000>,
567 <0x60000100 0x100>;
568 #interrupt-cells = <3>;
569 interrupt-controller;
570 };
571
572 sysctrl@61840000 {
573 compatible = "socionext,uniphier-pro5-sysctrl",
574 "simple-mfd", "syscon";
575 reg = <0x61840000 0x10000>;
576
577 sys_clk: clock {
578 compatible = "socionext,uniphier-pro5-clock";
579 #clock-cells = <1>;
580 };
581
582 sys_rst: reset {
583 compatible = "socionext,uniphier-pro5-reset";
584 #reset-cells = <1>;
585 };
586 };
587
588 usb0: usb@65b00000 {
589 compatible = "socionext,uniphier-pro5-dwc3";
590 status = "disabled";
591 reg = <0x65b00000 0x1000>;
592 #address-cells = <1>;
593 #size-cells = <1>;
594 ranges;
595 pinctrl-names = "default";
596 pinctrl-0 = <&pinctrl_usb0>;
597 dwc3@65a00000 {
598 compatible = "snps,dwc3";
599 reg = <0x65a00000 0x10000>;
600 interrupts = <0 134 4>;
601 tx-fifo-resize;
602 };
603 };
604
605 usb1: usb@65d00000 {
606 compatible = "socionext,uniphier-pro5-dwc3";
607 status = "disabled";
608 reg = <0x65d00000 0x1000>;
609 #address-cells = <1>;
610 #size-cells = <1>;
611 ranges;
612 pinctrl-names = "default";
613 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
614 dwc3@65c00000 {
615 compatible = "snps,dwc3";
616 reg = <0x65c00000 0x10000>;
617 interrupts = <0 137 4>;
618 tx-fifo-resize;
619 };
620 };
621
622 nand: nand@68000000 {
623 compatible = "socionext,denali-nand-v5b";
624 status = "disabled";
625 reg-names = "nand_data", "denali_reg";
626 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
627 interrupts = <0 65 4>;
628 pinctrl-names = "default";
629 pinctrl-0 = <&pinctrl_nand>;
630 clocks = <&sys_clk 2>;
631 nand-ecc-strength = <8>;
632 };
633
634 emmc: sdhc@68400000 {
635 compatible = "socionext,uniphier-sdhc";
636 status = "disabled";
637 reg = <0x68400000 0x800>;
638 interrupts = <0 78 4>;
639 pinctrl-names = "default";
640 pinctrl-0 = <&pinctrl_emmc>;
641 clocks = <&sd_clk 1>;
642 reset-names = "host";
643 resets = <&sd_rst 1>;
644 bus-width = <8>;
645 non-removable;
646 cap-mmc-highspeed;
647 cap-mmc-hw-reset;
648 no-3-3-v;
649 };
650
651 sd: sdhc@68800000 {
652 compatible = "socionext,uniphier-sdhc";
653 status = "disabled";
654 reg = <0x68800000 0x800>;
655 interrupts = <0 76 4>;
656 pinctrl-names = "default", "1.8v";
657 pinctrl-0 = <&pinctrl_sd>;
658 pinctrl-1 = <&pinctrl_sd_1v8>;
659 clocks = <&sd_clk 0>;
660 reset-names = "host";
661 resets = <&sd_rst 0>;
662 bus-width = <4>;
663 cap-sd-highspeed;
664 sd-uhs-sdr12;
665 sd-uhs-sdr25;
666 sd-uhs-sdr50;
Masahiro Yamada10ee0a62015-08-28 22:33:14 +0900667 };
668 };
Masahiro Yamada8f062432015-12-16 10:54:07 +0900669};
Masahiro Yamada10ee0a62015-08-28 22:33:14 +0900670
Masahiro Yamadacd622142016-12-05 18:31:39 +0900671/include/ "uniphier-pinctrl.dtsi"