blob: a8775c77dc2e04cd151bda57fc370e61ace71cee [file] [log] [blame]
Peng Fan1c643302019-07-31 07:01:34 +00001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
5 * Copyright 2019 NXP
6 *
7 * Gated clock implementation
8 */
9
Patrick Delaunay560e1e02021-11-19 15:12:07 +010010#define LOG_CATEGORY UCLASS_CLK
11
Peng Fan1c643302019-07-31 07:01:34 +000012#include <common.h>
Patrick Delaunay572c4462021-11-19 15:12:06 +010013#include <clk.h>
Patrick Delaunay560e1e02021-11-19 15:12:07 +010014#include <log.h>
Peng Fan1c643302019-07-31 07:01:34 +000015#include <clk-uclass.h>
Patrick Delaunay572c4462021-11-19 15:12:06 +010016#include <malloc.h>
17#include <asm/io.h>
Peng Fan1c643302019-07-31 07:01:34 +000018#include <dm/device.h>
Patrick Delaunay560e1e02021-11-19 15:12:07 +010019#include <dm/device_compat.h>
Simon Glass61b29b82020-02-03 07:36:15 -070020#include <dm/devres.h>
Simon Glasscd93d622020-05-10 11:40:13 -060021#include <linux/bitops.h>
Peng Fan1c643302019-07-31 07:01:34 +000022#include <linux/clk-provider.h>
Simon Glass61b29b82020-02-03 07:36:15 -070023#include <linux/err.h>
Peng Fan1c643302019-07-31 07:01:34 +000024
Patrick Delaunay572c4462021-11-19 15:12:06 +010025#include "clk.h"
26
Peng Fan1c643302019-07-31 07:01:34 +000027#define UBOOT_DM_CLK_GATE "clk_gate"
28
29/**
30 * DOC: basic gatable clock which can gate and ungate it's output
31 *
32 * Traits of this clock:
33 * prepare - clk_(un)prepare only ensures parent is (un)prepared
34 * enable - clk_enable and clk_disable are functional & control gating
35 * rate - inherits rate from parent. No clk_set_rate support
36 * parent - fixed parent. No clk_set_parent support
37 */
38
39/*
40 * It works on following logic:
41 *
42 * For enabling clock, enable = 1
43 * set2dis = 1 -> clear bit -> set = 0
44 * set2dis = 0 -> set bit -> set = 1
45 *
46 * For disabling clock, enable = 0
47 * set2dis = 1 -> set bit -> set = 1
48 * set2dis = 0 -> clear bit -> set = 0
49 *
50 * So, result is always: enable xor set2dis.
51 */
52static void clk_gate_endisable(struct clk *clk, int enable)
53{
Sean Anderson78ce0bd2020-06-24 06:41:06 -040054 struct clk_gate *gate = to_clk_gate(clk);
Peng Fan1c643302019-07-31 07:01:34 +000055 int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
56 u32 reg;
57
58 set ^= enable;
59
60 if (gate->flags & CLK_GATE_HIWORD_MASK) {
61 reg = BIT(gate->bit_idx + 16);
62 if (set)
63 reg |= BIT(gate->bit_idx);
64 } else {
Simon Glass4051c402023-02-05 15:40:43 -070065#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
Peng Fan2b129572019-07-31 07:01:57 +000066 reg = gate->io_gate_val;
67#else
Peng Fan1c643302019-07-31 07:01:34 +000068 reg = readl(gate->reg);
Peng Fan2b129572019-07-31 07:01:57 +000069#endif
Peng Fan1c643302019-07-31 07:01:34 +000070
71 if (set)
72 reg |= BIT(gate->bit_idx);
73 else
74 reg &= ~BIT(gate->bit_idx);
75 }
76
77 writel(reg, gate->reg);
78}
79
80static int clk_gate_enable(struct clk *clk)
81{
82 clk_gate_endisable(clk, 1);
83
84 return 0;
85}
86
87static int clk_gate_disable(struct clk *clk)
88{
89 clk_gate_endisable(clk, 0);
90
91 return 0;
92}
93
94int clk_gate_is_enabled(struct clk *clk)
95{
Sean Anderson78ce0bd2020-06-24 06:41:06 -040096 struct clk_gate *gate = to_clk_gate(clk);
Peng Fan1c643302019-07-31 07:01:34 +000097 u32 reg;
98
Simon Glass4051c402023-02-05 15:40:43 -070099#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
Peng Fan2b129572019-07-31 07:01:57 +0000100 reg = gate->io_gate_val;
101#else
Peng Fan1c643302019-07-31 07:01:34 +0000102 reg = readl(gate->reg);
Peng Fan2b129572019-07-31 07:01:57 +0000103#endif
Peng Fan1c643302019-07-31 07:01:34 +0000104
105 /* if a set bit disables this clk, flip it before masking */
106 if (gate->flags & CLK_GATE_SET_TO_DISABLE)
107 reg ^= BIT(gate->bit_idx);
108
109 reg &= BIT(gate->bit_idx);
110
111 return reg ? 1 : 0;
112}
113
114const struct clk_ops clk_gate_ops = {
115 .enable = clk_gate_enable,
116 .disable = clk_gate_disable,
117 .get_rate = clk_generic_get_rate,
118};
119
120struct clk *clk_register_gate(struct device *dev, const char *name,
121 const char *parent_name, unsigned long flags,
122 void __iomem *reg, u8 bit_idx,
123 u8 clk_gate_flags, spinlock_t *lock)
124{
125 struct clk_gate *gate;
126 struct clk *clk;
127 int ret;
128
129 if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
130 if (bit_idx > 15) {
Patrick Delaunay560e1e02021-11-19 15:12:07 +0100131 dev_err(dev, "gate bit exceeds LOWORD field\n");
Peng Fan1c643302019-07-31 07:01:34 +0000132 return ERR_PTR(-EINVAL);
133 }
134 }
135
136 /* allocate the gate */
137 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
138 if (!gate)
139 return ERR_PTR(-ENOMEM);
140
141 /* struct clk_gate assignments */
142 gate->reg = reg;
143 gate->bit_idx = bit_idx;
144 gate->flags = clk_gate_flags;
Simon Glass4051c402023-02-05 15:40:43 -0700145#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
Peng Fan2b129572019-07-31 07:01:57 +0000146 gate->io_gate_val = *(u32 *)reg;
147#endif
Peng Fan1c643302019-07-31 07:01:34 +0000148
149 clk = &gate->clk;
Dario Binacchi16bdc852020-04-13 14:36:27 +0200150 clk->flags = flags;
Peng Fan1c643302019-07-31 07:01:34 +0000151
152 ret = clk_register(clk, UBOOT_DM_CLK_GATE, name, parent_name);
153 if (ret) {
154 kfree(gate);
155 return ERR_PTR(ret);
156 }
157
158 return clk;
159}
160
161U_BOOT_DRIVER(clk_gate) = {
162 .name = UBOOT_DM_CLK_GATE,
163 .id = UCLASS_CLK,
164 .ops = &clk_gate_ops,
165 .flags = DM_FLAG_PRE_RELOC,
166};