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wdenk4a9cbbe2002-08-27 09:48:53 +00001/*
2 * (C) Copyright 2000, 2001
3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 */
24
25/*
26 * FPGA support
27 */
28#include <common.h>
29#include <command.h>
Jon Loeligerbaa26db2007-07-08 17:51:39 -050030#if defined(CONFIG_CMD_NET)
wdenk4a9cbbe2002-08-27 09:48:53 +000031#include <net.h>
32#endif
wdenk8bde7f72003-06-27 21:31:46 +000033#include <fpga.h>
wdenkc3d2b4b2005-01-22 18:13:04 +000034#include <malloc.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000035
36#if 0
37#define FPGA_DEBUG
38#endif
39
40#ifdef FPGA_DEBUG
41#define PRINTF(fmt,args...) printf (fmt ,##args)
42#else
43#define PRINTF(fmt,args...)
44#endif
45
wdenk4a9cbbe2002-08-27 09:48:53 +000046/* Local functions */
wdenkd4ca31c2004-01-02 14:00:00 +000047static void fpga_usage (cmd_tbl_t * cmdtp);
48static int fpga_get_op (char *opstr);
wdenk4a9cbbe2002-08-27 09:48:53 +000049
50/* Local defines */
51#define FPGA_NONE -1
52#define FPGA_INFO 0
53#define FPGA_LOAD 1
wdenk30ce5ab2005-01-09 18:12:51 +000054#define FPGA_LOADB 2
wdenk4a9cbbe2002-08-27 09:48:53 +000055#define FPGA_DUMP 3
Stefan Roesef0ff4692006-08-15 14:15:51 +020056#define FPGA_LOADMK 4
wdenk4a9cbbe2002-08-27 09:48:53 +000057
wdenk30ce5ab2005-01-09 18:12:51 +000058/* Convert bitstream data and load into the fpga */
59int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
60{
Matthias Fuchs01335022007-12-27 17:12:34 +010061#if defined(CONFIG_FPGA_XILINX)
Wolfgang Denk8b019da2005-08-08 00:14:41 +020062 unsigned int length;
Wolfgang Denk8b019da2005-08-08 00:14:41 +020063 unsigned int swapsize;
wdenk30ce5ab2005-01-09 18:12:51 +000064 char buffer[80];
Wolfgang Denk8b019da2005-08-08 00:14:41 +020065 unsigned char *dataptr;
Wolfgang Denk8b019da2005-08-08 00:14:41 +020066 unsigned int i;
wdenk30ce5ab2005-01-09 18:12:51 +000067 int rc;
68
Wolfgang Denk77ddac92005-10-13 16:45:02 +020069 dataptr = (unsigned char *)fpgadata;
wdenk30ce5ab2005-01-09 18:12:51 +000070
Wolfgang Denk8b019da2005-08-08 00:14:41 +020071 /* skip the first bytes of the bitsteam, their meaning is unknown */
72 length = (*dataptr << 8) + *(dataptr+1);
73 dataptr+=2;
74 dataptr+=length;
wdenk30ce5ab2005-01-09 18:12:51 +000075
76 /* get design name (identifier, length, string) */
Wolfgang Denk8b019da2005-08-08 00:14:41 +020077 length = (*dataptr << 8) + *(dataptr+1);
78 dataptr+=2;
wdenk30ce5ab2005-01-09 18:12:51 +000079 if (*dataptr++ != 0x61) {
Wolfgang Denk8b019da2005-08-08 00:14:41 +020080 PRINTF ("%s: Design name identifier not recognized in bitstream\n",
81 __FUNCTION__ );
wdenk30ce5ab2005-01-09 18:12:51 +000082 return FPGA_FAIL;
83 }
84
wdenka562e1b2005-01-09 18:21:42 +000085 length = (*dataptr << 8) + *(dataptr+1);
wdenk30ce5ab2005-01-09 18:12:51 +000086 dataptr+=2;
87 for(i=0;i<length;i++)
88 buffer[i]=*dataptr++;
wdenka562e1b2005-01-09 18:21:42 +000089
Wolfgang Denk8b019da2005-08-08 00:14:41 +020090 printf(" design filename = \"%s\"\n", buffer);
wdenk30ce5ab2005-01-09 18:12:51 +000091
92 /* get part number (identifier, length, string) */
93 if (*dataptr++ != 0x62) {
Wolfgang Denk8b019da2005-08-08 00:14:41 +020094 printf("%s: Part number identifier not recognized in bitstream\n",
95 __FUNCTION__ );
wdenk30ce5ab2005-01-09 18:12:51 +000096 return FPGA_FAIL;
97 }
wdenka562e1b2005-01-09 18:21:42 +000098
Wolfgang Denk8b019da2005-08-08 00:14:41 +020099 length = (*dataptr << 8) + *(dataptr+1);
100 dataptr+=2;
wdenka562e1b2005-01-09 18:21:42 +0000101 for(i=0;i<length;i++)
wdenk30ce5ab2005-01-09 18:12:51 +0000102 buffer[i]=*dataptr++;
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200103 printf(" part number = \"%s\"\n", buffer);
wdenka562e1b2005-01-09 18:21:42 +0000104
wdenk30ce5ab2005-01-09 18:12:51 +0000105 /* get date (identifier, length, string) */
106 if (*dataptr++ != 0x63) {
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200107 printf("%s: Date identifier not recognized in bitstream\n",
108 __FUNCTION__);
wdenk30ce5ab2005-01-09 18:12:51 +0000109 return FPGA_FAIL;
110 }
wdenka562e1b2005-01-09 18:21:42 +0000111
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200112 length = (*dataptr << 8) + *(dataptr+1);
113 dataptr+=2;
wdenk30ce5ab2005-01-09 18:12:51 +0000114 for(i=0;i<length;i++)
115 buffer[i]=*dataptr++;
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200116 printf(" date = \"%s\"\n", buffer);
wdenk30ce5ab2005-01-09 18:12:51 +0000117
118 /* get time (identifier, length, string) */
119 if (*dataptr++ != 0x64) {
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200120 printf("%s: Time identifier not recognized in bitstream\n",__FUNCTION__);
wdenk30ce5ab2005-01-09 18:12:51 +0000121 return FPGA_FAIL;
122 }
wdenka562e1b2005-01-09 18:21:42 +0000123
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200124 length = (*dataptr << 8) + *(dataptr+1);
125 dataptr+=2;
wdenk30ce5ab2005-01-09 18:12:51 +0000126 for(i=0;i<length;i++)
127 buffer[i]=*dataptr++;
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200128 printf(" time = \"%s\"\n", buffer);
wdenka562e1b2005-01-09 18:21:42 +0000129
wdenk30ce5ab2005-01-09 18:12:51 +0000130 /* get fpga data length (identifier, length) */
131 if (*dataptr++ != 0x65) {
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200132 printf("%s: Data length identifier not recognized in bitstream\n",
133 __FUNCTION__);
wdenk30ce5ab2005-01-09 18:12:51 +0000134 return FPGA_FAIL;
135 }
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +0200136 swapsize = ((unsigned int) *dataptr <<24) +
137 ((unsigned int) *(dataptr+1) <<16) +
138 ((unsigned int) *(dataptr+2) <<8 ) +
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200139 ((unsigned int) *(dataptr+3) ) ;
wdenk30ce5ab2005-01-09 18:12:51 +0000140 dataptr+=4;
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200141 printf(" bytes in bitstream = %d\n", swapsize);
wdenka562e1b2005-01-09 18:21:42 +0000142
Matthias Fuchsc26acc12007-12-27 17:13:11 +0100143 rc = fpga_load(dev, dataptr, swapsize);
wdenk30ce5ab2005-01-09 18:12:51 +0000144 return rc;
145#else
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200146 printf("Bitstream support only for Xilinx devices\n");
wdenk30ce5ab2005-01-09 18:12:51 +0000147 return FPGA_FAIL;
148#endif
149}
150
wdenk4a9cbbe2002-08-27 09:48:53 +0000151/* ------------------------------------------------------------------------- */
152/* command form:
153 * fpga <op> <device number> <data addr> <datasize>
154 * where op is 'load', 'dump', or 'info'
155 * If there is no device number field, the fpga environment variable is used.
156 * If there is no data addr field, the fpgadata environment variable is used.
157 * The info command requires no data address field.
158 */
wdenkd4ca31c2004-01-02 14:00:00 +0000159int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +0000160{
wdenkd4ca31c2004-01-02 14:00:00 +0000161 int op, dev = FPGA_INVALID_DEVICE;
162 size_t data_size = 0;
163 void *fpga_data = NULL;
164 char *devstr = getenv ("fpga");
165 char *datastr = getenv ("fpgadata");
166 int rc = FPGA_FAIL;
wdenk4a9cbbe2002-08-27 09:48:53 +0000167
wdenkd4ca31c2004-01-02 14:00:00 +0000168 if (devstr)
169 dev = (int) simple_strtoul (devstr, NULL, 16);
170 if (datastr)
171 fpga_data = (void *) simple_strtoul (datastr, NULL, 16);
wdenk4a9cbbe2002-08-27 09:48:53 +0000172
wdenkd4ca31c2004-01-02 14:00:00 +0000173 switch (argc) {
174 case 5: /* fpga <op> <dev> <data> <datasize> */
175 data_size = simple_strtoul (argv[4], NULL, 16);
176 case 4: /* fpga <op> <dev> <data> */
177 fpga_data = (void *) simple_strtoul (argv[3], NULL, 16);
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200178 PRINTF ("%s: fpga_data = 0x%x\n", __FUNCTION__, (uint) fpga_data);
wdenkd4ca31c2004-01-02 14:00:00 +0000179 case 3: /* fpga <op> <dev | data addr> */
180 dev = (int) simple_strtoul (argv[2], NULL, 16);
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200181 PRINTF ("%s: device = %d\n", __FUNCTION__, dev);
wdenkd4ca31c2004-01-02 14:00:00 +0000182 /* FIXME - this is a really weak test */
183 if ((argc == 3) && (dev > fpga_count ())) { /* must be buffer ptr */
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +0200184 PRINTF ("%s: Assuming buffer pointer in arg 3\n",
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200185 __FUNCTION__);
wdenkd4ca31c2004-01-02 14:00:00 +0000186 fpga_data = (void *) dev;
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200187 PRINTF ("%s: fpga_data = 0x%x\n",
188 __FUNCTION__, (uint) fpga_data);
wdenkd4ca31c2004-01-02 14:00:00 +0000189 dev = FPGA_INVALID_DEVICE; /* reset device num */
190 }
191 case 2: /* fpga <op> */
192 op = (int) fpga_get_op (argv[1]);
193 break;
194 default:
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200195 PRINTF ("%s: Too many or too few args (%d)\n",
196 __FUNCTION__, argc);
wdenkd4ca31c2004-01-02 14:00:00 +0000197 op = FPGA_NONE; /* force usage display */
198 break;
199 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000200
wdenkd4ca31c2004-01-02 14:00:00 +0000201 switch (op) {
202 case FPGA_NONE:
203 fpga_usage (cmdtp);
204 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000205
wdenkd4ca31c2004-01-02 14:00:00 +0000206 case FPGA_INFO:
207 rc = fpga_info (dev);
208 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000209
wdenkd4ca31c2004-01-02 14:00:00 +0000210 case FPGA_LOAD:
211 rc = fpga_load (dev, fpga_data, data_size);
212 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000213
wdenk30ce5ab2005-01-09 18:12:51 +0000214 case FPGA_LOADB:
215 rc = fpga_loadbitstream(dev, fpga_data, data_size);
216 break;
217
Stefan Roesef0ff4692006-08-15 14:15:51 +0200218 case FPGA_LOADMK:
219 {
220 image_header_t header;
221 image_header_t *hdr = &header;
222 ulong data;
223
224 memmove (&header, (char *)fpga_data, sizeof(image_header_t));
225 if (ntohl(hdr->ih_magic) != IH_MAGIC) {
226 puts ("Bad Magic Number\n");
227 return 1;
228 }
Stefan Roese77d50342006-10-07 11:33:03 +0200229 data = ((ulong)fpga_data + sizeof(image_header_t));
Stefan Roesef0ff4692006-08-15 14:15:51 +0200230 data_size = ntohl(hdr->ih_size);
Stefan Roese77d50342006-10-07 11:33:03 +0200231 rc = fpga_load (dev, (void *)data, data_size);
Stefan Roesef0ff4692006-08-15 14:15:51 +0200232 }
233 break;
234
wdenkd4ca31c2004-01-02 14:00:00 +0000235 case FPGA_DUMP:
236 rc = fpga_dump (dev, fpga_data, data_size);
237 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000238
wdenkd4ca31c2004-01-02 14:00:00 +0000239 default:
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200240 printf ("Unknown operation\n");
wdenkd4ca31c2004-01-02 14:00:00 +0000241 fpga_usage (cmdtp);
242 break;
243 }
244 return (rc);
wdenk4a9cbbe2002-08-27 09:48:53 +0000245}
246
wdenkd4ca31c2004-01-02 14:00:00 +0000247static void fpga_usage (cmd_tbl_t * cmdtp)
wdenk4a9cbbe2002-08-27 09:48:53 +0000248{
wdenkd4ca31c2004-01-02 14:00:00 +0000249 printf ("Usage:\n%s\n", cmdtp->usage);
wdenk4a9cbbe2002-08-27 09:48:53 +0000250}
251
252/*
253 * Map op to supported operations. We don't use a table since we
254 * would just have to relocate it from flash anyway.
255 */
wdenkd4ca31c2004-01-02 14:00:00 +0000256static int fpga_get_op (char *opstr)
wdenk4a9cbbe2002-08-27 09:48:53 +0000257{
258 int op = FPGA_NONE;
259
260 if (!strcmp ("info", opstr)) {
261 op = FPGA_INFO;
wdenk30ce5ab2005-01-09 18:12:51 +0000262 } else if (!strcmp ("loadb", opstr)) {
263 op = FPGA_LOADB;
wdenkd4ca31c2004-01-02 14:00:00 +0000264 } else if (!strcmp ("load", opstr)) {
wdenk4a9cbbe2002-08-27 09:48:53 +0000265 op = FPGA_LOAD;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200266 } else if (!strcmp ("loadmk", opstr)) {
267 op = FPGA_LOADMK;
wdenkd4ca31c2004-01-02 14:00:00 +0000268 } else if (!strcmp ("dump", opstr)) {
wdenk4a9cbbe2002-08-27 09:48:53 +0000269 op = FPGA_DUMP;
270 }
271
wdenkd4ca31c2004-01-02 14:00:00 +0000272 if (op == FPGA_NONE) {
wdenk4a9cbbe2002-08-27 09:48:53 +0000273 printf ("Unknown fpga operation \"%s\"\n", opstr);
274 }
275 return op;
276}
277
wdenkd4ca31c2004-01-02 14:00:00 +0000278U_BOOT_CMD (fpga, 6, 1, do_fpga,
wdenkdd875c72004-01-03 21:24:46 +0000279 "fpga - loadable FPGA image support\n",
wdenkd4ca31c2004-01-02 14:00:00 +0000280 "fpga [operation type] [device number] [image address] [image size]\n"
281 "fpga operations:\n"
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200282 "\tinfo\tlist known device information\n"
283 "\tload\tLoad device from memory buffer\n"
284 "\tloadb\tLoad device from bitstream buffer (Xilinx devices only)\n"
Stefan Roesef0ff4692006-08-15 14:15:51 +0200285 "\tloadmk\tLoad device generated with mkimage\n"
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200286 "\tdump\tLoad device to memory buffer\n");