blob: 859fb3c7787af8562336e6c7e378b70b9fb3c994 [file] [log] [blame]
wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2002
3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenke2211742002-11-02 23:30:20 +00006 */
7
8#include <common.h> /* core U-Boot definitions */
9#include <spartan2.h> /* Spartan-II device family */
10
wdenke2211742002-11-02 23:30:20 +000011/* Define FPGA_DEBUG to get debug printf's */
12#ifdef FPGA_DEBUG
13#define PRINTF(fmt,args...) printf (fmt ,##args)
14#else
15#define PRINTF(fmt,args...)
16#endif
17
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020018#undef CONFIG_SYS_FPGA_CHECK_BUSY
19#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
wdenke2211742002-11-02 23:30:20 +000020
21/* Note: The assumption is that we cannot possibly run fast enough to
22 * overrun the device (the Slave Parallel mode can free run at 50MHz).
23 * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
24 * the board config file to slow things down.
25 */
26#ifndef CONFIG_FPGA_DELAY
27#define CONFIG_FPGA_DELAY()
28#endif
29
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020030#ifndef CONFIG_SYS_FPGA_WAIT
31#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
wdenke2211742002-11-02 23:30:20 +000032#endif
33
Michal Simekf8c1be92014-03-13 12:49:21 +010034static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize);
35static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize);
36/* static int spartan2_sp_info(xilinx_desc *desc ); */
wdenke2211742002-11-02 23:30:20 +000037
Michal Simekf8c1be92014-03-13 12:49:21 +010038static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
39static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
40/* static int spartan2_ss_info(xilinx_desc *desc ); */
wdenke2211742002-11-02 23:30:20 +000041
42/* ------------------------------------------------------------------------- */
43/* Spartan-II Generic Implementation */
Michal Simek7a78bd22014-05-02 14:09:30 +020044static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize,
45 bitstream_type bstype)
wdenke2211742002-11-02 23:30:20 +000046{
47 int ret_val = FPGA_FAIL;
48
49 switch (desc->iface) {
50 case slave_serial:
51 PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
Michal Simekb625b9a2014-03-13 11:23:43 +010052 ret_val = spartan2_ss_load(desc, buf, bsize);
wdenke2211742002-11-02 23:30:20 +000053 break;
54
55 case slave_parallel:
56 PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
Michal Simekb625b9a2014-03-13 11:23:43 +010057 ret_val = spartan2_sp_load(desc, buf, bsize);
wdenke2211742002-11-02 23:30:20 +000058 break;
59
60 default:
61 printf ("%s: Unsupported interface type, %d\n",
62 __FUNCTION__, desc->iface);
63 }
64
65 return ret_val;
66}
67
Michal Simek14cfc4f2014-03-13 13:07:57 +010068static int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
wdenke2211742002-11-02 23:30:20 +000069{
70 int ret_val = FPGA_FAIL;
71
72 switch (desc->iface) {
73 case slave_serial:
74 PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
Michal Simekb625b9a2014-03-13 11:23:43 +010075 ret_val = spartan2_ss_dump(desc, buf, bsize);
wdenke2211742002-11-02 23:30:20 +000076 break;
77
78 case slave_parallel:
79 PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
Michal Simekb625b9a2014-03-13 11:23:43 +010080 ret_val = spartan2_sp_dump(desc, buf, bsize);
wdenke2211742002-11-02 23:30:20 +000081 break;
82
83 default:
84 printf ("%s: Unsupported interface type, %d\n",
85 __FUNCTION__, desc->iface);
86 }
87
88 return ret_val;
89}
90
Michal Simek14cfc4f2014-03-13 13:07:57 +010091static int spartan2_info(xilinx_desc *desc)
wdenke2211742002-11-02 23:30:20 +000092{
93 return FPGA_SUCCESS;
94}
95
96
wdenke2211742002-11-02 23:30:20 +000097/* ------------------------------------------------------------------------- */
98/* Spartan-II Slave Parallel Generic Implementation */
99
Michal Simekf8c1be92014-03-13 12:49:21 +0100100static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
wdenke2211742002-11-02 23:30:20 +0000101{
102 int ret_val = FPGA_FAIL; /* assume the worst */
Michal Simekb625b9a2014-03-13 11:23:43 +0100103 xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns;
wdenke2211742002-11-02 23:30:20 +0000104
105 PRINTF ("%s: start with interface functions @ 0x%p\n",
106 __FUNCTION__, fn);
107
108 if (fn) {
109 size_t bytecount = 0;
110 unsigned char *data = (unsigned char *) buf;
111 int cookie = desc->cookie; /* make a local copy */
112 unsigned long ts; /* timestamp */
113
114 PRINTF ("%s: Function Table:\n"
115 "ptr:\t0x%p\n"
116 "struct: 0x%p\n"
117 "pre: 0x%p\n"
118 "pgm:\t0x%p\n"
119 "init:\t0x%p\n"
120 "err:\t0x%p\n"
121 "clk:\t0x%p\n"
122 "cs:\t0x%p\n"
123 "wr:\t0x%p\n"
124 "read data:\t0x%p\n"
125 "write data:\t0x%p\n"
126 "busy:\t0x%p\n"
127 "abort:\t0x%p\n",
128 "post:\t0x%p\n\n",
129 __FUNCTION__, &fn, fn, fn->pre, fn->pgm, fn->init, fn->err,
130 fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, fn->busy,
131 fn->abort, fn->post);
132
133 /*
134 * This code is designed to emulate the "Express Style"
135 * Continuous Data Loading in Slave Parallel Mode for
136 * the Spartan-II Family.
137 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
wdenke2211742002-11-02 23:30:20 +0000139 printf ("Loading FPGA Device %d...\n", cookie);
140#endif
141 /*
142 * Run the pre configuration function if there is one.
143 */
144 if (*fn->pre) {
145 (*fn->pre) (cookie);
146 }
147
148 /* Establish the initial state */
York Sun472d5462013-04-01 11:29:11 -0700149 (*fn->pgm) (true, true, cookie); /* Assert the program, commit */
wdenke2211742002-11-02 23:30:20 +0000150
151 /* Get ready for the burn */
152 CONFIG_FPGA_DELAY ();
York Sun472d5462013-04-01 11:29:11 -0700153 (*fn->pgm) (false, true, cookie); /* Deassert the program, commit */
wdenke2211742002-11-02 23:30:20 +0000154
155 ts = get_timer (0); /* get current time */
156 /* Now wait for INIT and BUSY to go high */
157 do {
158 CONFIG_FPGA_DELAY ();
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159 if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
wdenke2211742002-11-02 23:30:20 +0000160 puts ("** Timeout waiting for INIT to clear.\n");
161 (*fn->abort) (cookie); /* abort the burn */
162 return FPGA_FAIL;
163 }
164 } while ((*fn->init) (cookie) && (*fn->busy) (cookie));
165
York Sun472d5462013-04-01 11:29:11 -0700166 (*fn->wr) (true, true, cookie); /* Assert write, commit */
167 (*fn->cs) (true, true, cookie); /* Assert chip select, commit */
168 (*fn->clk) (true, true, cookie); /* Assert the clock pin */
wdenke2211742002-11-02 23:30:20 +0000169
170 /* Load the data */
171 while (bytecount < bsize) {
172 /* XXX - do we check for an Ctrl-C press in here ??? */
173 /* XXX - Check the error bit? */
174
York Sun472d5462013-04-01 11:29:11 -0700175 (*fn->wdata) (data[bytecount++], true, cookie); /* write the data */
wdenke2211742002-11-02 23:30:20 +0000176 CONFIG_FPGA_DELAY ();
York Sun472d5462013-04-01 11:29:11 -0700177 (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
wdenke2211742002-11-02 23:30:20 +0000178 CONFIG_FPGA_DELAY ();
York Sun472d5462013-04-01 11:29:11 -0700179 (*fn->clk) (true, true, cookie); /* Assert the clock pin */
wdenke2211742002-11-02 23:30:20 +0000180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#ifdef CONFIG_SYS_FPGA_CHECK_BUSY
wdenke2211742002-11-02 23:30:20 +0000182 ts = get_timer (0); /* get current time */
183 while ((*fn->busy) (cookie)) {
184 /* XXX - we should have a check in here somewhere to
185 * make sure we aren't busy forever... */
186
187 CONFIG_FPGA_DELAY ();
York Sun472d5462013-04-01 11:29:11 -0700188 (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
wdenke2211742002-11-02 23:30:20 +0000189 CONFIG_FPGA_DELAY ();
York Sun472d5462013-04-01 11:29:11 -0700190 (*fn->clk) (true, true, cookie); /* Assert the clock pin */
wdenke2211742002-11-02 23:30:20 +0000191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192 if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
wdenke2211742002-11-02 23:30:20 +0000193 puts ("** Timeout waiting for BUSY to clear.\n");
194 (*fn->abort) (cookie); /* abort the burn */
195 return FPGA_FAIL;
196 }
197 }
198#endif
199
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
wdenke2211742002-11-02 23:30:20 +0000201 if (bytecount % (bsize / 40) == 0)
202 putc ('.'); /* let them know we are alive */
203#endif
204 }
205
206 CONFIG_FPGA_DELAY ();
York Sun472d5462013-04-01 11:29:11 -0700207 (*fn->cs) (false, true, cookie); /* Deassert the chip select */
208 (*fn->wr) (false, true, cookie); /* Deassert the write pin */
wdenke2211742002-11-02 23:30:20 +0000209
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
wdenke2211742002-11-02 23:30:20 +0000211 putc ('\n'); /* terminate the dotted line */
212#endif
213
214 /* now check for done signal */
215 ts = get_timer (0); /* get current time */
216 ret_val = FPGA_SUCCESS;
217 while ((*fn->done) (cookie) == FPGA_FAIL) {
wdenke2211742002-11-02 23:30:20 +0000218
219 CONFIG_FPGA_DELAY ();
York Sun472d5462013-04-01 11:29:11 -0700220 (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
wdenke2211742002-11-02 23:30:20 +0000221 CONFIG_FPGA_DELAY ();
York Sun472d5462013-04-01 11:29:11 -0700222 (*fn->clk) (true, true, cookie); /* Assert the clock pin */
wdenke2211742002-11-02 23:30:20 +0000223
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224 if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
wdenke2211742002-11-02 23:30:20 +0000225 puts ("** Timeout waiting for DONE to clear.\n");
226 (*fn->abort) (cookie); /* abort the burn */
227 ret_val = FPGA_FAIL;
228 break;
229 }
230 }
231
wdenke2211742002-11-02 23:30:20 +0000232 /*
233 * Run the post configuration function if there is one.
234 */
Matthias Fuchs3818b672009-02-15 22:28:36 +0100235 if (*fn->post)
wdenke2211742002-11-02 23:30:20 +0000236 (*fn->post) (cookie);
wdenke2211742002-11-02 23:30:20 +0000237
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
Matthias Fuchs3818b672009-02-15 22:28:36 +0100239 if (ret_val == FPGA_SUCCESS)
240 puts ("Done.\n");
241 else
wdenke2211742002-11-02 23:30:20 +0000242 puts ("Fail.\n");
243#endif
wdenke2211742002-11-02 23:30:20 +0000244
245 } else {
246 printf ("%s: NULL Interface function table!\n", __FUNCTION__);
247 }
248
249 return ret_val;
250}
251
Michal Simekf8c1be92014-03-13 12:49:21 +0100252static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize)
wdenke2211742002-11-02 23:30:20 +0000253{
254 int ret_val = FPGA_FAIL; /* assume the worst */
Michal Simekb625b9a2014-03-13 11:23:43 +0100255 xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns;
wdenke2211742002-11-02 23:30:20 +0000256
257 if (fn) {
258 unsigned char *data = (unsigned char *) buf;
259 size_t bytecount = 0;
260 int cookie = desc->cookie; /* make a local copy */
261
262 printf ("Starting Dump of FPGA Device %d...\n", cookie);
263
York Sun472d5462013-04-01 11:29:11 -0700264 (*fn->cs) (true, true, cookie); /* Assert chip select, commit */
265 (*fn->clk) (true, true, cookie); /* Assert the clock pin */
wdenke2211742002-11-02 23:30:20 +0000266
267 /* dump the data */
268 while (bytecount < bsize) {
269 /* XXX - do we check for an Ctrl-C press in here ??? */
270
York Sun472d5462013-04-01 11:29:11 -0700271 (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
272 (*fn->clk) (true, true, cookie); /* Assert the clock pin */
wdenke2211742002-11-02 23:30:20 +0000273 (*fn->rdata) (&(data[bytecount++]), cookie); /* read the data */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
wdenke2211742002-11-02 23:30:20 +0000275 if (bytecount % (bsize / 40) == 0)
276 putc ('.'); /* let them know we are alive */
277#endif
278 }
279
York Sun472d5462013-04-01 11:29:11 -0700280 (*fn->cs) (false, false, cookie); /* Deassert the chip select */
281 (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
282 (*fn->clk) (true, true, cookie); /* Assert the clock pin */
wdenke2211742002-11-02 23:30:20 +0000283
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
wdenke2211742002-11-02 23:30:20 +0000285 putc ('\n'); /* terminate the dotted line */
286#endif
287 puts ("Done.\n");
288
289 /* XXX - checksum the data? */
290 } else {
291 printf ("%s: NULL Interface function table!\n", __FUNCTION__);
292 }
293
294 return ret_val;
295}
296
297
wdenke2211742002-11-02 23:30:20 +0000298/* ------------------------------------------------------------------------- */
299
Michal Simekf8c1be92014-03-13 12:49:21 +0100300static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
wdenke2211742002-11-02 23:30:20 +0000301{
wdenk8bde7f72003-06-27 21:31:46 +0000302 int ret_val = FPGA_FAIL; /* assume the worst */
Michal Simekb625b9a2014-03-13 11:23:43 +0100303 xilinx_spartan2_slave_serial_fns *fn = desc->iface_fns;
wdenk8bde7f72003-06-27 21:31:46 +0000304 int i;
Matthias Fuchs437fc732007-12-27 17:13:05 +0100305 unsigned char val;
wdenk8bde7f72003-06-27 21:31:46 +0000306
wdenk7f6c2cb2002-11-10 22:06:23 +0000307 PRINTF ("%s: start with interface functions @ 0x%p\n",
308 __FUNCTION__, fn);
309
310 if (fn) {
311 size_t bytecount = 0;
312 unsigned char *data = (unsigned char *) buf;
313 int cookie = desc->cookie; /* make a local copy */
314 unsigned long ts; /* timestamp */
315
316 PRINTF ("%s: Function Table:\n"
317 "ptr:\t0x%p\n"
318 "struct: 0x%p\n"
319 "pgm:\t0x%p\n"
320 "init:\t0x%p\n"
321 "clk:\t0x%p\n"
322 "wr:\t0x%p\n"
323 "done:\t0x%p\n\n",
wdenk8bde7f72003-06-27 21:31:46 +0000324 __FUNCTION__, &fn, fn, fn->pgm, fn->init,
325 fn->clk, fn->wr, fn->done);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
wdenk7f6c2cb2002-11-10 22:06:23 +0000327 printf ("Loading FPGA Device %d...\n", cookie);
328#endif
329
330 /*
331 * Run the pre configuration function if there is one.
332 */
333 if (*fn->pre) {
334 (*fn->pre) (cookie);
335 }
336
337 /* Establish the initial state */
York Sun472d5462013-04-01 11:29:11 -0700338 (*fn->pgm) (true, true, cookie); /* Assert the program, commit */
wdenk7f6c2cb2002-11-10 22:06:23 +0000339
wdenk8bde7f72003-06-27 21:31:46 +0000340 /* Wait for INIT state (init low) */
wdenk7f6c2cb2002-11-10 22:06:23 +0000341 ts = get_timer (0); /* get current time */
342 do {
343 CONFIG_FPGA_DELAY ();
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344 if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
wdenk7f6c2cb2002-11-10 22:06:23 +0000345 puts ("** Timeout waiting for INIT to start.\n");
346 return FPGA_FAIL;
347 }
348 } while (!(*fn->init) (cookie));
wdenk8bde7f72003-06-27 21:31:46 +0000349
wdenk7f6c2cb2002-11-10 22:06:23 +0000350 /* Get ready for the burn */
351 CONFIG_FPGA_DELAY ();
York Sun472d5462013-04-01 11:29:11 -0700352 (*fn->pgm) (false, true, cookie); /* Deassert the program, commit */
wdenk7f6c2cb2002-11-10 22:06:23 +0000353
354 ts = get_timer (0); /* get current time */
355 /* Now wait for INIT to go high */
356 do {
357 CONFIG_FPGA_DELAY ();
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358 if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
wdenk7f6c2cb2002-11-10 22:06:23 +0000359 puts ("** Timeout waiting for INIT to clear.\n");
360 return FPGA_FAIL;
361 }
362 } while ((*fn->init) (cookie));
363
364 /* Load the data */
365 while (bytecount < bsize) {
wdenk8bde7f72003-06-27 21:31:46 +0000366
367 /* Xilinx detects an error if INIT goes low (active)
368 while DONE is low (inactive) */
369 if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
370 puts ("** CRC error during FPGA load.\n");
371 return (FPGA_FAIL);
372 }
373 val = data [bytecount ++];
374 i = 8;
375 do {
376 /* Deassert the clock */
York Sun472d5462013-04-01 11:29:11 -0700377 (*fn->clk) (false, true, cookie);
wdenk8bde7f72003-06-27 21:31:46 +0000378 CONFIG_FPGA_DELAY ();
379 /* Write data */
York Sun472d5462013-04-01 11:29:11 -0700380 (*fn->wr) ((val & 0x80), true, cookie);
wdenk8bde7f72003-06-27 21:31:46 +0000381 CONFIG_FPGA_DELAY ();
382 /* Assert the clock */
York Sun472d5462013-04-01 11:29:11 -0700383 (*fn->clk) (true, true, cookie);
wdenk8bde7f72003-06-27 21:31:46 +0000384 CONFIG_FPGA_DELAY ();
385 val <<= 1;
386 i --;
387 } while (i > 0);
388
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
wdenk7f6c2cb2002-11-10 22:06:23 +0000390 if (bytecount % (bsize / 40) == 0)
391 putc ('.'); /* let them know we are alive */
392#endif
393 }
394
395 CONFIG_FPGA_DELAY ();
396
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
wdenk7f6c2cb2002-11-10 22:06:23 +0000398 putc ('\n'); /* terminate the dotted line */
399#endif
400
401 /* now check for done signal */
402 ts = get_timer (0); /* get current time */
403 ret_val = FPGA_SUCCESS;
York Sun472d5462013-04-01 11:29:11 -0700404 (*fn->wr) (true, true, cookie);
wdenk7f6c2cb2002-11-10 22:06:23 +0000405
406 while (! (*fn->done) (cookie)) {
wdenk7f6c2cb2002-11-10 22:06:23 +0000407
408 CONFIG_FPGA_DELAY ();
York Sun472d5462013-04-01 11:29:11 -0700409 (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
wdenk7f6c2cb2002-11-10 22:06:23 +0000410 CONFIG_FPGA_DELAY ();
York Sun472d5462013-04-01 11:29:11 -0700411 (*fn->clk) (true, true, cookie); /* Assert the clock pin */
wdenk7f6c2cb2002-11-10 22:06:23 +0000412
wdenk8bde7f72003-06-27 21:31:46 +0000413 putc ('*');
414
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415 if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
wdenk7f6c2cb2002-11-10 22:06:23 +0000416 puts ("** Timeout waiting for DONE to clear.\n");
417 ret_val = FPGA_FAIL;
418 break;
419 }
420 }
421 putc ('\n'); /* terminate the dotted line */
422
Matthias Fuchs21d39d52007-12-27 17:12:43 +0100423 /*
424 * Run the post configuration function if there is one.
425 */
Matthias Fuchs3818b672009-02-15 22:28:36 +0100426 if (*fn->post)
Matthias Fuchs21d39d52007-12-27 17:12:43 +0100427 (*fn->post) (cookie);
Matthias Fuchs21d39d52007-12-27 17:12:43 +0100428
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
Matthias Fuchs3818b672009-02-15 22:28:36 +0100430 if (ret_val == FPGA_SUCCESS)
wdenk7f6c2cb2002-11-10 22:06:23 +0000431 puts ("Done.\n");
Matthias Fuchs3818b672009-02-15 22:28:36 +0100432 else
wdenk7f6c2cb2002-11-10 22:06:23 +0000433 puts ("Fail.\n");
wdenk7f6c2cb2002-11-10 22:06:23 +0000434#endif
435
436 } else {
437 printf ("%s: NULL Interface function table!\n", __FUNCTION__);
438 }
439
440 return ret_val;
wdenke2211742002-11-02 23:30:20 +0000441}
442
Michal Simekf8c1be92014-03-13 12:49:21 +0100443static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
wdenke2211742002-11-02 23:30:20 +0000444{
wdenk8bde7f72003-06-27 21:31:46 +0000445 /* Readback is only available through the Slave Parallel and */
446 /* boundary-scan interfaces. */
wdenk7f6c2cb2002-11-10 22:06:23 +0000447 printf ("%s: Slave Serial Dumping is unavailable\n",
wdenke2211742002-11-02 23:30:20 +0000448 __FUNCTION__);
449 return FPGA_FAIL;
450}
Michal Simek14cfc4f2014-03-13 13:07:57 +0100451
452struct xilinx_fpga_op spartan2_op = {
453 .load = spartan2_load,
454 .dump = spartan2_dump,
455 .info = spartan2_info,
456};