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Wolfgang Denk460c3222005-08-04 01:14:12 +02001/* ported from ctfb.c (linux kernel):
2 * Created in Jan - July 2000 by Thomas Höhenleitner <th@visuelle-maschinen.de>
3 *
4 * Ported to U-Boot:
5 * (C) Copyright 2002 Denis Peter, MPL AG Switzerland
wdenkc6097192002-11-03 00:24:07 +00006 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
wdenkc6097192002-11-03 00:24:07 +000026#include <common.h>
27
28#ifdef CONFIG_VIDEO
29
30#include <pci.h>
31#include <video_fb.h>
wdenkeeb1b772004-03-23 22:53:55 +000032#include "videomodes.h"
wdenkc6097192002-11-03 00:24:07 +000033
34#ifdef CONFIG_VIDEO_CT69000
35
36/* debug */
37#undef VGA_DEBUG
38#undef VGA_DUMP_REG
39#ifdef VGA_DEBUG
40#define PRINTF(fmt,args...) printf (fmt ,##args)
41#else
42#define PRINTF(fmt,args...)
43#endif
44
45/* Macros */
46#ifndef min
47#define min( a, b ) ( ( a ) < ( b ) ) ? ( a ) : ( b )
48#endif
49#ifndef max
50#define max( a, b ) ( ( a ) > ( b ) ) ? ( a ) : ( b )
51#endif
52#ifdef minmax
53#error "term minmax already used."
54#endif
55#define minmax( a, x, b ) max( ( a ), min( ( x ), ( b ) ) )
56#define N_ELTS( x ) ( sizeof( x ) / sizeof( x[ 0 ] ) )
57
58/* CT Register Offsets */
59#define CT_AR_O 0x3c0 /* Index and Data write port of the attribute Registers */
60#define CT_GR_O 0x3ce /* Index port of the Graphic Controller Registers */
61#define CT_SR_O 0x3c4 /* Index port of the Sequencer Controller */
62#define CT_CR_O 0x3d4 /* Index port of the CRT Controller */
63#define CT_XR_O 0x3d6 /* Extended Register index */
64#define CT_MSR_W_O 0x3c2 /* Misc. Output Register (write only) */
65#define CT_LUT_MASK_O 0x3c6 /* Color Palette Mask */
66#define CT_LUT_START_O 0x3c8 /* Color Palette Write Mode Index */
67#define CT_LUT_RGB_O 0x3c9 /* Color Palette Data Port */
68#define CT_STATUS_REG0_O 0x3c2 /* Status Register 0 (read only) */
69#define CT_STATUS_REG1_O 0x3da /* Input Status Register 1 (read only) */
70
71#define CT_FP_O 0x3d0 /* Index port of the Flat panel Registers */
72#define CT_MR_O 0x3d2 /* Index Port of the Multimedia Extension */
73
74/* defines for the memory mapped registers */
75#define BR00_o 0x400000 /* Source and Destination Span Register */
76#define BR01_o 0x400004 /* Pattern/Source Expansion Background Color & Transparency Key Register */
77#define BR02_o 0x400008 /* Pattern/Source Expansion Foreground Color Register */
78#define BR03_o 0x40000C /* Monochrome Source Control Register */
79#define BR04_o 0x400010 /* BitBLT Control Register */
80#define BR05_o 0x400014 /* Pattern Address Registe */
81#define BR06_o 0x400018 /* Source Address Register */
82#define BR07_o 0x40001C /* Destination Address Register */
83#define BR08_o 0x400020 /* Destination Width & Height Register */
84#define BR09_o 0x400024 /* Source Expansion Background Color & Transparency Key Register */
85#define BR0A_o 0x400028 /* Source Expansion Foreground Color Register */
86
87#define CURSOR_SIZE 0x1000 /* in KByte for HW Cursor */
88#define PATTERN_ADR (pGD->dprBase + CURSOR_SIZE) /* pattern Memory after Cursor Memory */
89#define PATTERN_SIZE 8*8*4 /* 4 Bytes per Pixel 8 x 8 Pixel */
90#define ACCELMEMORY (CURSOR_SIZE + PATTERN_SIZE) /* reserved Memory for BITBlt and hw cursor */
91
92/* Some Mode definitions */
93#define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */
94#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */
95#define FB_SYNC_EXT 4 /* external sync */
96#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */
97#define FB_SYNC_BROADCAST 16 /* broadcast video timings */
98 /* vtotal = 144d/288n/576i => PAL */
99 /* vtotal = 121d/242n/484i => NTSC */
100#define FB_SYNC_ON_GREEN 32 /* sync on green */
101
102#define FB_VMODE_NONINTERLACED 0 /* non interlaced */
103#define FB_VMODE_INTERLACED 1 /* interlaced */
104#define FB_VMODE_DOUBLE 2 /* double scan */
105#define FB_VMODE_MASK 255
106
107#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */
108#define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */
109#define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */
110
111#define text 0
112#define fntwidth 8
113
114/* table for VGA Initialization */
115typedef struct {
116 const unsigned char reg;
117 const unsigned char val;
118} CT_CFG_TABLE;
119
120/* this table provides some basic initialisations such as Memory Clock etc */
121static CT_CFG_TABLE xreg[] = {
122 {0x09, 0x01}, /* CRT Controller Extensions Enable */
123 {0x0A, 0x02}, /* Frame Buffer Mapping */
124 {0x0B, 0x01}, /* PCI Write Burst support */
125 {0x20, 0x00}, /* BitBLT Configuration */
126 {0x40, 0x03}, /* Memory Access Control */
127 {0x60, 0x00}, /* Video Pin Control */
128 {0x61, 0x00}, /* DPMS Synch control */
129 {0x62, 0x00}, /* GPIO Pin Control */
130 {0x63, 0xBD}, /* GPIO Pin Data */
131 {0x67, 0x00}, /* Pin Tri-State */
132 {0x80, 0x80}, /* Pixel Pipeline Config 0 register */
133 {0xA0, 0x00}, /* Cursor 1 Control Reg */
134 {0xA1, 0x00}, /* Cursor 1 Vertical Extension Reg */
135 {0xA2, 0x00}, /* Cursor 1 Base Address Low */
136 {0xA3, 0x00}, /* Cursor 1 Base Address High */
137 {0xA4, 0x00}, /* Cursor 1 X-Position Low */
138 {0xA5, 0x00}, /* Cursor 1 X-Position High */
139 {0xA6, 0x00}, /* Cursor 1 Y-Position Low */
140 {0xA7, 0x00}, /* Cursor 1 Y-Position High */
141 {0xA8, 0x00}, /* Cursor 2 Control Reg */
142 {0xA9, 0x00}, /* Cursor 2 Vertical Extension Reg */
143 {0xAA, 0x00}, /* Cursor 2 Base Address Low */
144 {0xAB, 0x00}, /* Cursor 2 Base Address High */
145 {0xAC, 0x00}, /* Cursor 2 X-Position Low */
146 {0xAD, 0x00}, /* Cursor 2 X-Position High */
147 {0xAE, 0x00}, /* Cursor 2 Y-Position Low */
148 {0xAF, 0x00}, /* Cursor 2 Y-Position High */
149 {0xC0, 0x7D}, /* Dot Clock 0 VCO M-Divisor */
150 {0xC1, 0x07}, /* Dot Clock 0 VCO N-Divisor */
151 {0xC3, 0x34}, /* Dot Clock 0 Divisor select */
152 {0xC4, 0x55}, /* Dot Clock 1 VCO M-Divisor */
153 {0xC5, 0x09}, /* Dot Clock 1 VCO N-Divisor */
154 {0xC7, 0x24}, /* Dot Clock 1 Divisor select */
155 {0xC8, 0x7D}, /* Dot Clock 2 VCO M-Divisor */
156 {0xC9, 0x07}, /* Dot Clock 2 VCO N-Divisor */
157 {0xCB, 0x34}, /* Dot Clock 2 Divisor select */
158 {0xCC, 0x38}, /* Memory Clock 0 VCO M-Divisor */
159 {0xCD, 0x03}, /* Memory Clock 0 VCO N-Divisor */
160 {0xCE, 0x90}, /* Memory Clock 0 Divisor select */
161 {0xCF, 0x06}, /* Clock Config */
162 {0xD0, 0x0F}, /* Power Down */
163 {0xD1, 0x01}, /* Power Down BitBLT */
164 {0xFF, 0xFF} /* end of table */
165};
166/* Clock Config:
167 * =============
168 *
169 * PD Registers:
170 * -------------
171 * Bit2 and Bit4..6 are used for the Loop Divisor and Post Divisor.
172 * They are encoded as follows:
173 *
174 * +---+--------------+
175 * | 2 | Loop Divisor |
176 * +---+--------------+
177 * | 1 | 1 |
178 * +---+--------------+
179 * | 0 | 4 |
180 * +---+--------------+
181 * Note: The Memory Clock does not have a Loop Divisor.
182 * +---+---+---+--------------+
183 * | 6 | 5 | 4 | Post Divisor |
184 * +---+---+---+--------------+
185 * | 0 | 0 | 0 | 1 |
186 * +---+---+---+--------------+
187 * | 0 | 0 | 1 | 2 |
188 * +---+---+---+--------------+
189 * | 0 | 1 | 0 | 4 |
190 * +---+---+---+--------------+
191 * | 0 | 1 | 1 | 8 |
192 * +---+---+---+--------------+
193 * | 1 | 0 | 0 | 16 |
194 * +---+---+---+--------------+
195 * | 1 | 0 | 1 | 32 |
196 * +---+---+---+--------------+
197 * | 1 | 1 | X | reserved |
198 * +---+---+---+--------------+
199 *
200 * All other bits are reserved in these registers.
201 *
202 * Clock VCO M Registers:
203 * ----------------------
204 * These Registers contain the M Value -2.
205 *
206 * Clock VCO N Registers:
207 * ----------------------
208 * These Registers contain the N Value -2.
209 *
210 * Formulas:
211 * ---------
212 * Fvco = (Fref * Loop Divisor * M/N), whereas 100MHz < Fvco < 220MHz
213 * Fout = Fvco / Post Divisor
214 *
215 * Dot Clk0 (default 25MHz):
216 * -------------------------
217 * Fvco = 14.318 * 127 / 9 = 202.045MHz
218 * Fout = 202.045MHz / 8 = 25.25MHz
219 * Post Divisor = 8
220 * Loop Divisor = 1
221 * XRC0 = (M - 2) = 125 = 0x7D
222 * XRC1 = (N - 2) = 7 = 0x07
223 * XRC3 = 0x34
224 *
225 * Dot Clk1 (default 28MHz):
226 * -------------------------
227 * Fvco = 14.318 * 87 / 11 = 113.24MHz
228 * Fout = 113.24MHz / 4 = 28.31MHz
229 * Post Divisor = 4
230 * Loop Divisor = 1
231 * XRC4 = (M - 2) = 85 = 0x55
232 * XRC5 = (N - 2) = 9 = 0x09
233 * XRC7 = 0x24
234 *
235 * Dot Clk2 (variable for extended modes set to 25MHz):
236 * ----------------------------------------------------
237 * Fvco = 14.318 * 127 / 9 = 202.045MHz
238 * Fout = 202.045MHz / 8 = 25.25MHz
239 * Post Divisor = 8
240 * Loop Divisor = 1
241 * XRC8 = (M - 2) = 125 = 0x7D
242 * XRC9 = (N - 2) = 7 = 0x07
243 * XRCB = 0x34
244 *
245 * Memory Clk for most modes >50MHz:
246 * ----------------------------------
247 * Fvco = 14.318 * 58 / 5 = 166MHz
248 * Fout = 166MHz / 2 = 83MHz
249 * Post Divisor = 2
250 * XRCC = (M - 2) = 57 = 0x38
251 * XRCD = (N - 2) = 3 = 0x03
252 * XRCE = 0x90
253 *
254 * Note Bit7 enables the clock source from the VCO
255 *
256 */
257
wdenkc6097192002-11-03 00:24:07 +0000258/*******************************************************************
259 * Chips struct
260 *******************************************************************/
261struct ctfb_chips_properties {
262 int device_id; /* PCI Device ID */
263 unsigned long max_mem; /* memory for frame buffer */
264 int vld_set; /* value of VLD if bit2 in clock control is set */
265 int vld_not_set; /* value of VLD if bit2 in clock control is set */
266 int mn_diff; /* difference between M/N Value + mn_diff = M/N Register */
267 int mn_min; /* min value of M/N Value */
268 int mn_max; /* max value of M/N Value */
269 int vco_min; /* VCO Min in MHz */
270 int vco_max; /* VCO Max in MHz */
271};
272
273static const struct ctfb_chips_properties chips[] = {
274 {PCI_DEVICE_ID_CT_69000, 0x200000, 1, 4, -2, 3, 257, 100, 220},
275 {PCI_DEVICE_ID_CT_65555, 0x100000, 16, 4, 0, 1, 255, 48, 220}, /* NOT TESTED */
276 {0, 0, 0, 0, 0, 0, 0, 0, 0} /* Terminator */
277};
278
wdenkc6097192002-11-03 00:24:07 +0000279/*
280 * The Graphic Device
281 */
282GraphicDevice ctfb;
283
284/*******************************************************************************
285*
286* Low Level Routines
287*/
288
289/*******************************************************************************
290*
291* Read CT ISA register
292*/
293#ifdef VGA_DEBUG
294static unsigned char
295ctRead (unsigned short index)
296{
297 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
298 if (index == CT_AR_O)
299 /* synch the Flip Flop */
300 in8 (pGD->isaBase + CT_STATUS_REG1_O);
301
302 return (in8 (pGD->isaBase + index));
303}
304#endif
305/*******************************************************************************
306*
307* Write CT ISA register
308*/
309static void
310ctWrite (unsigned short index, unsigned char val)
311{
312 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
313
314 out8 ((pGD->isaBase + index), val);
315}
316
317/*******************************************************************************
318*
319* Read CT ISA register indexed
320*/
321static unsigned char
322ctRead_i (unsigned short index, char reg)
323{
324 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
325 if (index == CT_AR_O)
326 /* synch the Flip Flop */
327 in8 (pGD->isaBase + CT_STATUS_REG1_O);
328 out8 ((pGD->isaBase + index), reg);
329 return (in8 (pGD->isaBase + index + 1));
330}
331
332/*******************************************************************************
333*
334* Write CT ISA register indexed
335*/
336static void
337ctWrite_i (unsigned short index, char reg, char val)
338{
339 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
340 if (index == CT_AR_O) {
341 /* synch the Flip Flop */
342 in8 (pGD->isaBase + CT_STATUS_REG1_O);
343 out8 ((pGD->isaBase + index), reg);
344 out8 ((pGD->isaBase + index), val);
345 } else {
346 out8 ((pGD->isaBase + index), reg);
347 out8 ((pGD->isaBase + index + 1), val);
348 }
349}
350
351/*******************************************************************************
352*
353* Write a table of CT ISA register
354*/
355static void
356ctLoadRegs (unsigned short index, CT_CFG_TABLE * regTab)
357{
358 while (regTab->reg != 0xFF) {
359 ctWrite_i (index, regTab->reg, regTab->val);
360 regTab++;
361 }
362}
363
364/*****************************************************************************/
365static void
366SetArRegs (void)
367{
368 int i, tmp;
369
370 for (i = 0; i < 0x10; i++)
371 ctWrite_i (CT_AR_O, i, i);
372 if (text)
373 tmp = 0x04;
374 else
375 tmp = 0x41;
376
377 ctWrite_i (CT_AR_O, 0x10, tmp); /* Mode Control Register */
378 ctWrite_i (CT_AR_O, 0x11, 0x00); /* Overscan Color Register */
379 ctWrite_i (CT_AR_O, 0x12, 0x0f); /* Memory Plane Enable Register */
380 if (fntwidth == 9)
381 tmp = 0x08;
382 else
383 tmp = 0x00;
384 ctWrite_i (CT_AR_O, 0x13, tmp); /* Horizontal Pixel Panning */
385 ctWrite_i (CT_AR_O, 0x14, 0x00); /* Color Select Register */
386 ctWrite (CT_AR_O, 0x20); /* enable video */
387}
388
389/*****************************************************************************/
390static void
391SetGrRegs (void)
392{ /* Set Graphics Mode */
393 int i;
394
395 for (i = 0; i < 0x05; i++)
396 ctWrite_i (CT_GR_O, i, 0);
397 if (text) {
398 ctWrite_i (CT_GR_O, 0x05, 0x10);
399 ctWrite_i (CT_GR_O, 0x06, 0x02);
400 } else {
401 ctWrite_i (CT_GR_O, 0x05, 0x40);
402 ctWrite_i (CT_GR_O, 0x06, 0x05);
403 }
404 ctWrite_i (CT_GR_O, 0x07, 0x0f);
405 ctWrite_i (CT_GR_O, 0x08, 0xff);
406}
407
408/*****************************************************************************/
409static void
410SetSrRegs (void)
411{
412 int tmp = 0;
413
414 ctWrite_i (CT_SR_O, 0x00, 0x00); /* reset */
415 /*rr( sr, 0x01, tmp );
416 if( fntwidth == 8 ) tmp |= 0x01; else tmp &= ~0x01;
417 wr( sr, 0x01, tmp ); */
418 if (fntwidth == 8)
419 ctWrite_i (CT_SR_O, 0x01, 0x01); /* Clocking Mode Register */
420 else
421 ctWrite_i (CT_SR_O, 0x01, 0x00); /* Clocking Mode Register */
422 ctWrite_i (CT_SR_O, 0x02, 0x0f); /* Enable CPU wr access to given memory plane */
423 ctWrite_i (CT_SR_O, 0x03, 0x00); /* Character Map Select Register */
424 if (text)
425 tmp = 0x02;
426 else
427 tmp = 0x0e;
428 ctWrite_i (CT_SR_O, 0x04, tmp); /* Enable CPU accesses to the rest of the 256KB
429 total VGA memory beyond the first 64KB and set
430 fb mapping mode. */
431 ctWrite_i (CT_SR_O, 0x00, 0x03); /* enable */
432}
433
434/*****************************************************************************/
435static void
436SetBitsPerPixelIntoXrRegs (int bpp)
437{
438 unsigned int n = (bpp >> 3), tmp; /* only for 15, 8, 16, 24 bpp */
439 static char md[4] = { 0x04, 0x02, 0x05, 0x06 }; /* DisplayColorMode */
440 static char off[4] = { ~0x20, ~0x30, ~0x20, ~0x10 }; /* mask */
441 static char on[4] = { 0x10, 0x00, 0x10, 0x20 }; /* mask */
442 if (bpp == 15)
443 n = 0;
444 tmp = ctRead_i (CT_XR_O, 0x20);
445 tmp &= off[n];
446 tmp |= on[n];
447 ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */
448 ctWrite_i (CT_XR_O, 0x81, md[n]);
449}
450
451/*****************************************************************************/
452static void
453SetCrRegs (struct ctfb_res_modes *var, int bits_per_pixel)
454{ /* he -le- ht|0 hd -ri- hs -h- he */
455 unsigned char cr[0x7a];
456 int i, tmp;
457 unsigned int hd, hs, he, ht, hbe; /* Horizontal. */
458 unsigned int vd, vs, ve, vt; /* vertical */
459 unsigned int bpp, wd, dblscan, interlaced, bcast, CrtHalfLine;
460 unsigned int CompSyncCharClkDelay, CompSyncPixelClkDelay;
461 unsigned int NTSC_PAL_HorizontalPulseWidth, BlDelayCtrl;
462 unsigned int HorizontalEqualizationPulses;
463 unsigned int HorizontalSerration1Start, HorizontalSerration2Start;
464
465 const int LineCompare = 0x3ff;
466 unsigned int TextScanLines = 1; /* this is in fact a vertical zoom factor */
467 unsigned int RAMDAC_BlankPedestalEnable = 0; /* 1=en-, 0=disable, see XR82 */
468
469 hd = (var->xres) / 8; /* HDisp. */
470 hs = (var->xres + var->right_margin) / 8; /* HsStrt */
471 he = (var->xres + var->right_margin + var->hsync_len) / 8; /* HsEnd */
472 ht = (var->left_margin + var->xres + var->right_margin + var->hsync_len) / 8; /* HTotal */
473 hbe = ht - 1; /* HBlankEnable todo docu wants ht here, but it does not work */
474 /* ve -up- vt|0 vd -lo- vs -v- ve */
475 vd = var->yres; /* VDisplay */
476 vs = var->yres + var->lower_margin; /* VSyncStart */
477 ve = var->yres + var->lower_margin + var->vsync_len; /* VSyncEnd */
478 vt = var->upper_margin + var->yres + var->lower_margin + var->vsync_len; /* VTotal */
479 bpp = bits_per_pixel;
480 dblscan = (var->vmode & FB_VMODE_DOUBLE) ? 1 : 0;
481 interlaced = var->vmode & FB_VMODE_INTERLACED;
482 bcast = var->sync & FB_SYNC_BROADCAST;
483 CrtHalfLine = bcast ? (hd >> 1) : 0;
484 BlDelayCtrl = bcast ? 1 : 0;
485 CompSyncCharClkDelay = 0; /* 2 bit */
486 CompSyncPixelClkDelay = 0; /* 3 bit */
487 if (bcast) {
488 NTSC_PAL_HorizontalPulseWidth = 7; /*( var->hsync_len >> 1 ) + 1 */
489 HorizontalEqualizationPulses = 0; /* inverse value */
490 HorizontalSerration1Start = 31; /* ( ht >> 1 ) */
491 HorizontalSerration2Start = 89; /* ( ht >> 1 ) */
492 } else {
493 NTSC_PAL_HorizontalPulseWidth = 0;
494 /* 4 bit: hsync pulse width = ( ( CR74[4:0] - CR74[5] )
495 * / 2 ) + 1 --> CR74[4:0] = 2*(hs-1) + CR74[5] */
496 HorizontalEqualizationPulses = 1; /* inverse value */
497 HorizontalSerration1Start = 0; /* ( ht >> 1 ) */
498 HorizontalSerration2Start = 0; /* ( ht >> 1 ) */
499 }
500
501 if (bpp == 15)
502 bpp = 16;
503 wd = var->xres * bpp / 64; /* double words per line */
504 if (interlaced) { /* we divide all vertical timings, exept vd */
505 vs >>= 1;
506 ve >>= 1;
507 vt >>= 1;
508 }
509 memset (cr, 0, sizeof (cr));
510 cr[0x00] = 0xff & (ht - 5);
511 cr[0x01] = hd - 1; /* soll:4f ist 59 */
512 cr[0x02] = hd;
513 cr[0x03] = (hbe & 0x1F) | 0x80; /* hd + ht - hd */
514 cr[0x04] = hs;
515 cr[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f);
516 cr[0x06] = (vt - 2) & 0xFF;
517 cr[0x30] = (vt - 2) >> 8;
518 cr[0x07] = ((vt & 0x100) >> 8)
519 | ((vd & 0x100) >> 7)
520 | ((vs & 0x100) >> 6)
521 | ((vs & 0x100) >> 5)
522 | ((LineCompare & 0x100) >> 4)
523 | ((vt & 0x200) >> 4)
524 | ((vd & 0x200) >> 3)
525 | ((vs & 0x200) >> 2);
526 cr[0x08] = 0x00;
527 cr[0x09] = (dblscan << 7)
528 | ((LineCompare & 0x200) >> 3)
529 | ((vs & 0x200) >> 4)
530 | (TextScanLines - 1);
531 cr[0x10] = vs & 0xff; /* VSyncPulseStart */
532 cr[0x32] = (vs & 0xf00) >> 8; /* VSyncPulseStart */
533 cr[0x11] = (ve & 0x0f); /* | 0x20; */
534 cr[0x12] = (vd - 1) & 0xff; /* LineCount */
535 cr[0x31] = ((vd - 1) & 0xf00) >> 8; /* LineCount */
536 cr[0x13] = wd & 0xff;
537 cr[0x41] = (wd & 0xf00) >> 8;
538 cr[0x15] = vs & 0xff;
539 cr[0x33] = (vs & 0xf00) >> 8;
540 cr[0x38] = (0x100 & (ht - 5)) >> 8;
541 cr[0x3C] = 0xc0 & hbe;
542 cr[0x16] = (vt - 1) & 0xff; /* vbe - docu wants vt here, */
543 cr[0x17] = 0xe3; /* but it does not work */
544 cr[0x18] = 0xff & LineCompare;
545 cr[0x22] = 0xff; /* todo? */
546 cr[0x70] = interlaced ? (0x80 | CrtHalfLine) : 0x00; /* check:0xa6 */
547 cr[0x71] = 0x80 | (RAMDAC_BlankPedestalEnable << 6)
548 | (BlDelayCtrl << 5)
549 | ((0x03 & CompSyncCharClkDelay) << 3)
550 | (0x07 & CompSyncPixelClkDelay); /* todo: see XR82 */
551 cr[0x72] = HorizontalSerration1Start;
552 cr[0x73] = HorizontalSerration2Start;
553 cr[0x74] = (HorizontalEqualizationPulses << 5)
554 | NTSC_PAL_HorizontalPulseWidth;
555 /* todo: ct69000 has also 0x75-79 */
556 /* now set the registers */
557 for (i = 0; i <= 0x0d; i++) { /*CR00 .. CR0D */
558 ctWrite_i (CT_CR_O, i, cr[i]);
559 }
560 for (i = 0x10; i <= 0x18; i++) { /*CR10 .. CR18 */
561 ctWrite_i (CT_CR_O, i, cr[i]);
562 }
563 i = 0x22; /*CR22 */
564 ctWrite_i (CT_CR_O, i, cr[i]);
565 for (i = 0x30; i <= 0x33; i++) { /*CR30 .. CR33 */
566 ctWrite_i (CT_CR_O, i, cr[i]);
567 }
568 i = 0x38; /*CR38 */
569 ctWrite_i (CT_CR_O, i, cr[i]);
570 i = 0x3C; /*CR3C */
571 ctWrite_i (CT_CR_O, i, cr[i]);
572 for (i = 0x40; i <= 0x41; i++) { /*CR40 .. CR41 */
573 ctWrite_i (CT_CR_O, i, cr[i]);
574 }
575 for (i = 0x70; i <= 0x74; i++) { /*CR70 .. CR74 */
576 ctWrite_i (CT_CR_O, i, cr[i]);
577 }
578 tmp = ctRead_i (CT_CR_O, 0x40);
579 tmp &= 0x0f;
580 tmp |= 0x80;
581 ctWrite_i (CT_CR_O, 0x40, tmp); /* StartAddressEnable */
582}
583
584/* pixelclock control */
585
586/*****************************************************************************
587 We have a rational number p/q and need an m/n which is very close to p/q
588 but has m and n within mnmin and mnmax. We have no floating point in the
589 kernel. We can use long long without divide. And we have time to compute...
590******************************************************************************/
591static unsigned int
592FindBestPQFittingMN (unsigned int p, unsigned int q, unsigned int mnmin,
593 unsigned int mnmax, unsigned int *pm, unsigned int *pn)
594{
595 /* this code is not for general purpose usable but good for our number ranges */
596 unsigned int n = mnmin, m = 0;
597 long long int L = 0, P = p, Q = q, H = P >> 1;
598 long long int D = 0x7ffffffffffffffLL;
599 for (n = mnmin; n <= mnmax; n++) {
600 m = mnmin; /* p/q ~ m/n -> p*n ~ m*q -> p*n-x*q ~ 0 */
601 L = P * n - m * Q; /* n * vco - m * fref should be near 0 */
602 while (L > 0 && m < mnmax) {
603 L -= q; /* difference is greater as 0 subtract fref */
604 m++; /* and increment m */
605 }
606 /* difference is less or equal than 0 or m > maximum */
607 if (m > mnmax)
608 break; /* no solution: if we increase n we get the same situation */
609 /* L is <= 0 now */
610 if (-L > H && m > mnmin) { /* if difference > the half fref */
611 L += q; /* we take the situation before */
612 m--; /* because its closer to 0 */
613 }
614 L = (L < 0) ? -L : +L; /* absolute value */
615 if (D < L) /* if last difference was better take next n */
616 continue;
617 D = L;
618 *pm = m;
619 *pn = n; /* keep improved data */
620 if (D == 0)
621 break; /* best result we can get */
622 }
623 return (unsigned int) (0xffffffff & D);
624}
625
626/* that is the hardware < 69000 we have to manage
627 +---------+ +-------------------+ +----------------------+ +--+
628 | REFCLK |__|NTSC Divisor Select|__|FVCO Reference Divisor|__|÷N|__
629 | 14.3MHz | |(NTSCDS) (÷1, ÷5) | |Select (RDS) (÷1, ÷4) | | | |
630 +---------+ +-------------------+ +----------------------+ +--+ |
631 ___________________________________________________________________|
632 |
633 | fvco fout
634 | +--------+ +------------+ +-----+ +-------------------+ +----+
635 +-| Phase |__|Charge Pump |__| VCO |_____|Post Divisor (PD) |___|CLK |--->
636 +-| Detect | |& Filter VCO| | | | |÷1, 2, 4, 8, 16, 32| | |
637 | +--------+ +------------+ +-----+ | +-------------------+ +----+
638 | |
639 | +--+ +---------------+ |
640 |____|÷M|___|VCO Loop Divide|__________|
641 | | |(VLD)(÷4, ÷16) |
642 +--+ +---------------+
643****************************************************************************
644 that is the hardware >= 69000 we have to manage
645 +---------+ +--+
646 | REFCLK |__|÷N|__
647 | 14.3MHz | | | |
648 +---------+ +--+ |
649 __________________|
650 |
651 | fvco fout
652 | +--------+ +------------+ +-----+ +-------------------+ +----+
653 +-| Phase |__|Charge Pump |__| VCO |_____|Post Divisor (PD) |___|CLK |--->
654 +-| Detect | |& Filter VCO| | | | |÷1, 2, 4, 8, 16, 32| | |
655 | +--------+ +------------+ +-----+ | +-------------------+ +----+
656 | |
657 | +--+ +---------------+ |
658 |____|÷M|___|VCO Loop Divide|__________|
659 | | |(VLD)(÷1, ÷4) |
660 +--+ +---------------+
661
662
663*/
664
665#define VIDEO_FREF 14318180; /* Hz */
666/*****************************************************************************/
667static int
668ReadPixClckFromXrRegsBack (struct ctfb_chips_properties *param)
669{
670 unsigned int m, n, vld, pd, PD, fref, xr_cb, i, pixclock;
671 i = 0;
672 pixclock = -1;
673 fref = VIDEO_FREF;
674 m = ctRead_i (CT_XR_O, 0xc8);
675 n = ctRead_i (CT_XR_O, 0xc9);
676 m -= param->mn_diff;
677 n -= param->mn_diff;
678 xr_cb = ctRead_i (CT_XR_O, 0xcb);
679 PD = (0x70 & xr_cb) >> 4;
680 pd = 1;
681 for (i = 0; i < PD; i++) {
682 pd *= 2;
683 }
684 vld = (0x04 & xr_cb) ? param->vld_set : param->vld_not_set;
685 if (n * vld * m) {
686 unsigned long long p = 1000000000000LL * pd * n;
687 unsigned long long q = (long long) fref * vld * m;
688 while ((p > 0xffffffffLL) || (q > 0xffffffffLL)) {
689 p >>= 1; /* can't divide with long long so we scale down */
690 q >>= 1;
691 }
692 pixclock = (unsigned) p / (unsigned) q;
693 } else
694 printf ("Invalid data in xr regs.\n");
695 return pixclock;
696}
697
698/*****************************************************************************/
699static void
700FindAndSetPllParamIntoXrRegs (unsigned int pixelclock,
701 struct ctfb_chips_properties *param)
702{
703 unsigned int m, n, vld, pd, PD, fref, xr_cb;
704 unsigned int fvcomin, fvcomax, pclckmin, pclckmax, pclk;
705 unsigned int pfreq, fvco, new_pixclock;
wdenk3e386912003-04-05 00:53:31 +0000706 unsigned int D,nback,mback;
wdenkc6097192002-11-03 00:24:07 +0000707
708 fref = VIDEO_FREF;
709 pd = 1;
710 PD = 0;
711 fvcomin = param->vco_min;
712 fvcomax = param->vco_max; /* MHz */
713 pclckmin = 1000000 / fvcomax + 1; /* 4546 */
714 pclckmax = 32000000 / fvcomin - 1; /* 666665 */
715 pclk = minmax (pclckmin, pixelclock, pclckmax); /* ps pp */
716 pfreq = 250 * (4000000000U / pclk);
717 fvco = pfreq; /* Hz */
718 new_pixclock = 0;
719 while (fvco < fvcomin * 1000000) {
720 /* double VCO starting with the pixelclock frequency
721 * as long as it is lower than the minimal VCO frequency */
722 fvco *= 2;
723 pd *= 2;
724 PD++;
725 }
726 /* fvco is exactly pd * pixelclock and higher than the ninmal VCO frequency */
wdenk3e386912003-04-05 00:53:31 +0000727 /* first try */
728 vld = param->vld_set;
729 D=FindBestPQFittingMN (fvco / vld, fref, param->mn_min, param->mn_max, &m, &n); /* rds = 1 */
730 mback=m;
731 nback=n;
732 /* second try */
733 vld = param->vld_not_set;
734 if(D<FindBestPQFittingMN (fvco / vld, fref, param->mn_min, param->mn_max, &m, &n)) { /* rds = 1 */
735 /* first try was better */
736 m=mback;
737 n=nback;
738 vld = param->vld_set;
739 }
wdenkc6097192002-11-03 00:24:07 +0000740 m += param->mn_diff;
741 n += param->mn_diff;
742 PRINTF ("VCO %d, pd %d, m %d n %d vld %d \n", fvco, pd, m, n, vld);
743 xr_cb = ((0x7 & PD) << 4) | (vld == param->vld_set ? 0x04 : 0);
744 /* All four of the registers used for dot clock 2 (XRC8 - XRCB) must be
745 * written, and in order from XRC8 to XRCB, before the hardware will
746 * update the synthesizer s settings.
747 */
748 ctWrite_i (CT_XR_O, 0xc8, m);
749 ctWrite_i (CT_XR_O, 0xc9, n); /* xrca does not exist in CT69000 and CT69030 */
750 ctWrite_i (CT_XR_O, 0xca, 0); /* because of a hw bug I guess, but we write */
751 ctWrite_i (CT_XR_O, 0xcb, xr_cb); /* 0 to it for savety */
752 new_pixclock = ReadPixClckFromXrRegsBack (param);
753 PRINTF ("pixelclock.set = %d, pixelclock.real = %d \n",
754 pixelclock, new_pixclock);
755}
756
757/*****************************************************************************/
758static void
759SetMsrRegs (struct ctfb_res_modes *mode)
760{
761 unsigned char h_synch_high, v_synch_high;
762
763 h_synch_high = (mode->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 0x40; /* horizontal Synch High active */
764 v_synch_high = (mode->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 0x80; /* vertical Synch High active */
765 ctWrite (CT_MSR_W_O, (h_synch_high | v_synch_high | 0x29));
766 /* upper64K==0x20, CLC2select==0x08, RAMenable==0x02!(todo), CGA==0x01
767 * Selects the upper 64KB page.Bit5=1
768 * CLK2 (left reserved in standard VGA) Bit3|2=1|0
769 * Disables CPU access to frame buffer. Bit1=0
770 * Sets the I/O address decode for ST01, FCR, and all CR registers
771 * to the 3Dx I/O address range (CGA emulation). Bit0=1
772 */
773}
774
775/************************************************************************************/
776#ifdef VGA_DUMP_REG
777
778static void
779ctDispRegs (unsigned short index, int from, int to)
780{
781 unsigned char status;
782 int i;
783
784 for (i = from; i < to; i++) {
785 status = ctRead_i (index, i);
786 printf ("%02X: is %02X\n", i, status);
787 }
788}
789
790void
791video_dump_reg (void)
792{
793 int i;
794
795 printf ("Extended Regs:\n");
796 ctDispRegs (CT_XR_O, 0, 0xC);
797 ctDispRegs (CT_XR_O, 0xe, 0xf);
798 ctDispRegs (CT_XR_O, 0x20, 0x21);
799 ctDispRegs (CT_XR_O, 0x40, 0x50);
800 ctDispRegs (CT_XR_O, 0x60, 0x64);
801 ctDispRegs (CT_XR_O, 0x67, 0x68);
802 ctDispRegs (CT_XR_O, 0x70, 0x72);
803 ctDispRegs (CT_XR_O, 0x80, 0x83);
804 ctDispRegs (CT_XR_O, 0xA0, 0xB0);
805 ctDispRegs (CT_XR_O, 0xC0, 0xD3);
806 printf ("Sequencer Regs:\n");
807 ctDispRegs (CT_SR_O, 0, 0x8);
808 printf ("Graphic Regs:\n");
809 ctDispRegs (CT_GR_O, 0, 0x9);
810 printf ("CRT Regs:\n");
811 ctDispRegs (CT_CR_O, 0, 0x19);
812 ctDispRegs (CT_CR_O, 0x22, 0x23);
813 ctDispRegs (CT_CR_O, 0x30, 0x34);
814 ctDispRegs (CT_CR_O, 0x38, 0x39);
815 ctDispRegs (CT_CR_O, 0x3C, 0x3D);
816 ctDispRegs (CT_CR_O, 0x40, 0x42);
817 ctDispRegs (CT_CR_O, 0x70, 0x80);
818 /* don't display the attributes */
819}
820
821#endif
822
823#ifdef CONFIG_VIDEO_HW_CURSOR
824/***************************************************************
825 * Set Hardware Cursor in Pixel
826 */
827void
828video_set_hw_cursor (int x, int y)
829{
830 int sig_x = 0, sig_y = 0;
831 if (x < 0) {
832 x *= -1;
833 sig_x = 1;
834 }
835 if (y < 0) {
836 y *= -1;
837 sig_y = 1;
838 }
839 ctWrite_i (CT_XR_O, 0xa4, x & 0xff);
840 ctWrite_i (CT_XR_O, 0xa5, (x >> 8) & 0x7);
841 ctWrite_i (CT_XR_O, 0xa6, y & 0xff);
842 ctWrite_i (CT_XR_O, 0xa7, (y >> 8) & 0x7);
843}
844
845/***************************************************************
846 * Init Hardware Cursor. To know the size of the Cursor,
847 * we have to know the Font size.
848 */
849void
850video_init_hw_cursor (int font_width, int font_height)
851{
852 unsigned char xr_80;
853 unsigned long *curs, pattern;
854 int i;
855 int cursor_start;
856 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
857
858 cursor_start = pGD->dprBase;
859 xr_80 = ctRead_i (CT_XR_O, 0x80);
860 /* set start address */
861 ctWrite_i (CT_XR_O, 0xa2, (cursor_start >> 8) & 0xf0);
862 ctWrite_i (CT_XR_O, 0xa3, (cursor_start >> 16) & 0x3f);
863 /* set cursor shape */
864 curs = (unsigned long *) cursor_start;
865 i = 0;
866 while (i < 0x400) {
867 curs[i++] = 0xffffffff; /* AND mask */
868 curs[i++] = 0xffffffff; /* AND mask */
869 curs[i++] = 0; /* XOR mask */
870 curs[i++] = 0; /* XOR mask */
871 /* Transparent */
872 }
873 pattern = 0xffffffff >> font_width;
874 i = 0;
875 while (i < (font_height * 2)) {
876 curs[i++] = pattern; /* AND mask */
877 curs[i++] = pattern; /* AND mask */
878 curs[i++] = 0; /* XOR mask */
879 curs[i++] = 0; /* XOR mask */
880 /* Cursor Color 0 */
881 }
882 /* set blink rate */
883 ctWrite_i (CT_FP_O, 0x19, 0xf);
884
885 /* set cursors colors */
886 xr_80 = ctRead_i (CT_XR_O, 0x80);
887 xr_80 |= 0x1; /* alternate palette select */
888 ctWrite_i (CT_XR_O, 0x80, xr_80);
889 video_set_lut (4, CONSOLE_FG_COL, CONSOLE_FG_COL, CONSOLE_FG_COL);
890 /* position 4 is color 0 cursor 0 */
891 xr_80 &= 0xfe; /* normal palette select */
892 ctWrite_i (CT_XR_O, 0x80, xr_80);
893 /* cursor enable */
894 ctWrite_i (CT_XR_O, 0xa0, 0x91);
895 xr_80 |= 0x10; /* enable hwcursor */
896 ctWrite_i (CT_XR_O, 0x80, xr_80);
897 video_set_hw_cursor (0, 0);
898}
899#endif /* CONFIG_VIDEO_HW_CURSOR */
900
901/***************************************************************
902 * Wait for BitBlt ready
903 */
904static int
905video_wait_bitblt (unsigned long addr)
906{
907 unsigned long br04;
908 int i = 0;
909 br04 = in32r (addr);
910 while (br04 & 0x80000000) {
911 udelay (1);
912 br04 = in32r (addr);
913 if (i++ > 1000000) {
914 printf ("ERROR Timeout %lx\n", br04);
915 return 1;
916 }
917 }
918 return 0;
919}
920
921/***************************************************************
922 * Set up BitBlt Registrs
923 */
924static void
925SetDrawingEngine (int bits_per_pixel)
926{
927 unsigned long br04, br00;
928 unsigned char tmp;
929
930 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
931
932 tmp = ctRead_i (CT_XR_O, 0x20); /* BitBLT Configuration */
933 tmp |= 0x02; /* reset BitBLT */
934 ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */
935 udelay (10);
936 tmp &= 0xfd; /* release reset BitBLT */
937 ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */
938 video_wait_bitblt (pGD->pciBase + BR04_o);
939
940 /* set pattern Address */
941 out32r (pGD->pciBase + BR05_o, PATTERN_ADR & 0x003ffff8);
942 br04 = 0;
943 if (bits_per_pixel == 1) {
944 br04 |= 0x00040000; /* monochome Pattern */
945 br04 |= 0x00001000; /* monochome source */
946 }
947 br00 = ((pGD->winSizeX * pGD->gdfBytesPP) << 16) + (pGD->winSizeX * pGD->gdfBytesPP); /* bytes per scanline */
948 out32r (pGD->pciBase + BR00_o, br00); /* */
949 out32r (pGD->pciBase + BR08_o, (10 << 16) + 10); /* dummy */
950 out32r (pGD->pciBase + BR04_o, br04); /* write all 0 */
951 out32r (pGD->pciBase + BR07_o, 0); /* destination */
952 video_wait_bitblt (pGD->pciBase + BR04_o);
953}
954
wdenkc6097192002-11-03 00:24:07 +0000955/****************************************************************************
956* supported Video Chips
957*/
958static struct pci_device_id supported[] = {
959 {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69000},
960 {}
961};
962
963/*******************************************************************************
964*
965* Init video chip
966*/
967void *
968video_hw_init (void)
969{
970 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
971 unsigned short device_id;
972 pci_dev_t devbusfn;
973 int videomode;
974 unsigned long t1, hsynch, vsynch;
975 unsigned int pci_mem_base, *vm;
976 int tmp, i, bits_per_pixel;
977 char *penv;
978 struct ctfb_res_modes *res_mode;
979 struct ctfb_res_modes var_mode;
980 struct ctfb_chips_properties *chips_param;
981 /* Search for video chip */
982
983 if ((devbusfn = pci_find_devices (supported, 0)) < 0) {
984#ifdef CONFIG_VIDEO_ONBOARD
985 printf ("Video: Controller not found !\n");
986#endif
987 return (NULL);
988 }
989
990 /* PCI setup */
991 pci_write_config_dword (devbusfn, PCI_COMMAND,
992 (PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
993 pci_read_config_word (devbusfn, PCI_DEVICE_ID, &device_id);
994 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pci_mem_base);
995 pci_mem_base = pci_mem_to_phys (devbusfn, pci_mem_base);
996
997 /* get chips params */
998 for (chips_param = (struct ctfb_chips_properties *) &chips[0];
999 chips_param->device_id != 0; chips_param++) {
1000 if (chips_param->device_id == device_id)
1001 break;
1002 }
1003 if (chips_param->device_id == 0) {
1004#ifdef CONFIG_VIDEO_ONBOARD
1005 printf ("Video: controller 0x%X not supported\n", device_id);
1006#endif
1007 return NULL;
1008 }
1009 /* supported Video controller found */
1010 printf ("Video: ");
1011
1012 tmp = 0;
1013 videomode = 0x301;
1014 /* get video mode via environment */
1015 if ((penv = getenv ("videomode")) != NULL) {
1016 /* deceide if it is a string */
1017 if (penv[0] <= '9') {
1018 videomode = (int) simple_strtoul (penv, NULL, 16);
1019 tmp = 1;
1020 }
1021 } else {
1022 tmp = 1;
1023 }
1024 if (tmp) {
1025 /* parameter are vesa modes */
1026 /* search params */
1027 for (i = 0; i < VESA_MODES_COUNT; i++) {
1028 if (vesa_modes[i].vesanr == videomode)
1029 break;
1030 }
1031 if (i == VESA_MODES_COUNT) {
1032 printf ("no VESA Mode found, switching to mode 0x301 ");
1033 i = 0;
1034 }
1035 res_mode =
1036 (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].
1037 resindex];
1038 bits_per_pixel = vesa_modes[i].bits_per_pixel;
1039 } else {
1040
1041 res_mode = (struct ctfb_res_modes *) &var_mode;
1042 bits_per_pixel = video_get_params (res_mode, penv);
1043 }
1044
1045 /* calculate available color depth for controller memory */
1046 if (bits_per_pixel == 15)
1047 tmp = 2;
1048 else
1049 tmp = bits_per_pixel >> 3; /* /8 */
1050 if (((chips_param->max_mem -
1051 ACCELMEMORY) / (res_mode->xres * res_mode->yres)) < tmp) {
1052 tmp =
1053 ((chips_param->max_mem -
1054 ACCELMEMORY) / (res_mode->xres * res_mode->yres));
1055 if (tmp == 0) {
1056 printf
1057 ("No matching videomode found .-> reduce resolution\n");
1058 return NULL;
1059 } else {
1060 printf ("Switching back to %d Bits per Pixel ",
1061 tmp << 3);
1062 bits_per_pixel = tmp << 3;
1063 }
1064 }
1065
1066 /* calculate hsynch and vsynch freq (info only) */
1067 t1 = (res_mode->left_margin + res_mode->xres +
1068 res_mode->right_margin + res_mode->hsync_len) / 8;
1069 t1 *= 8;
1070 t1 *= res_mode->pixclock;
1071 t1 /= 1000;
1072 hsynch = 1000000000L / t1;
1073 t1 *=
1074 (res_mode->upper_margin + res_mode->yres +
1075 res_mode->lower_margin + res_mode->vsync_len);
1076 t1 /= 1000;
1077 vsynch = 1000000000L / t1;
1078
1079 /* fill in Graphic device struct */
1080 sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
1081 res_mode->yres, bits_per_pixel, (hsynch / 1000),
1082 (vsynch / 1000));
1083 printf ("%s\n", pGD->modeIdent);
1084 pGD->winSizeX = res_mode->xres;
1085 pGD->winSizeY = res_mode->yres;
1086 pGD->plnSizeX = res_mode->xres;
1087 pGD->plnSizeY = res_mode->yres;
1088 switch (bits_per_pixel) {
1089 case 8:
1090 pGD->gdfBytesPP = 1;
1091 pGD->gdfIndex = GDF__8BIT_INDEX;
1092 break;
1093 case 15:
1094 pGD->gdfBytesPP = 2;
1095 pGD->gdfIndex = GDF_15BIT_555RGB;
1096 break;
1097 case 16:
1098 pGD->gdfBytesPP = 2;
1099 pGD->gdfIndex = GDF_16BIT_565RGB;
1100 break;
1101 case 24:
1102 pGD->gdfBytesPP = 3;
1103 pGD->gdfIndex = GDF_24BIT_888RGB;
1104 break;
1105 }
1106 pGD->isaBase = CFG_ISA_IO_BASE_ADDRESS;
1107 pGD->pciBase = pci_mem_base;
1108 pGD->frameAdrs = pci_mem_base;
1109 pGD->memSize = chips_param->max_mem;
1110 /* Cursor Start Address */
1111 pGD->dprBase =
1112 (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) + pci_mem_base;
1113 if ((pGD->dprBase & 0x0fff) != 0) {
1114 /* allign it */
1115 pGD->dprBase &= 0xfffff000;
1116 pGD->dprBase += 0x00001000;
1117 }
1118 PRINTF ("Cursor Start %x Pattern Start %x\n", pGD->dprBase,
1119 PATTERN_ADR);
1120 pGD->vprBase = pci_mem_base; /* Dummy */
1121 pGD->cprBase = pci_mem_base; /* Dummy */
1122 /* set up Hardware */
1123
1124 ctWrite (CT_MSR_W_O, 0x01);
1125
1126 /* set the extended Registers */
1127 ctLoadRegs (CT_XR_O, xreg);
1128 /* set atribute registers */
1129 SetArRegs ();
1130 /* set Graphics register */
1131 SetGrRegs ();
1132 /* set sequencer */
1133 SetSrRegs ();
1134
1135 /* set msr */
1136 SetMsrRegs (res_mode);
1137
1138 /* set CRT Registers */
1139 SetCrRegs (res_mode, bits_per_pixel);
1140 /* set color mode */
1141 SetBitsPerPixelIntoXrRegs (bits_per_pixel);
1142
1143 /* set PLL */
1144 FindAndSetPllParamIntoXrRegs (res_mode->pixclock, chips_param);
1145
1146 ctWrite_i (CT_SR_O, 0, 0x03); /* clear synchronous reset */
1147 /* Clear video memory */
1148 i = pGD->memSize / 4;
1149 vm = (unsigned int *) pGD->pciBase;
1150 while (i--)
1151 *vm++ = 0;
1152 SetDrawingEngine (bits_per_pixel);
1153#ifdef VGA_DUMP_REG
1154 video_dump_reg ();
1155#endif
1156
1157 return ((void *) &ctfb);
1158}
1159
1160 /*******************************************************************************
1161*
1162* Set a RGB color in the LUT (8 bit index)
1163*/
1164void
1165video_set_lut (unsigned int index, /* color number */
1166 unsigned char r, /* red */
1167 unsigned char g, /* green */
1168 unsigned char b /* blue */
1169 )
1170{
1171
1172 ctWrite (CT_LUT_MASK_O, 0xff);
1173
1174 ctWrite (CT_LUT_START_O, (char) index);
1175
1176 ctWrite (CT_LUT_RGB_O, r); /* red */
1177 ctWrite (CT_LUT_RGB_O, g); /* green */
1178 ctWrite (CT_LUT_RGB_O, b); /* blue */
1179 udelay (1);
1180 ctWrite (CT_LUT_MASK_O, 0xff);
1181}
1182
1183/*******************************************************************************
1184*
1185* Drawing engine fill on screen region
1186*/
1187void
1188video_hw_rectfill (unsigned int bpp, /* bytes per pixel */
1189 unsigned int dst_x, /* dest pos x */
1190 unsigned int dst_y, /* dest pos y */
1191 unsigned int dim_x, /* frame width */
1192 unsigned int dim_y, /* frame height */
1193 unsigned int color /* fill color */
1194 )
1195{
1196 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
1197 unsigned long *p, br04;
1198
1199 video_wait_bitblt (pGD->pciBase + BR04_o);
1200
1201 p = (unsigned long *) PATTERN_ADR;
1202 dim_x *= bpp;
1203 if (bpp == 3)
1204 bpp++; /* 24Bit needs a 32bit pattern */
1205 memset (p, color, (bpp * sizeof (unsigned char) * 8 * 8)); /* 8 x 8 pattern data */
1206 out32r (pGD->pciBase + BR07_o, ((pGD->winSizeX * dst_y) + dst_x) * pGD->gdfBytesPP); /* destination */
1207 br04 = in32r (pGD->pciBase + BR04_o) & 0xffffff00;
1208 br04 |= 0xF0; /* write Pattern P -> D */
1209 out32r (pGD->pciBase + BR04_o, br04); /* */
1210 out32r (pGD->pciBase + BR08_o, (dim_y << 16) + dim_x); /* starts the BITBlt */
1211 video_wait_bitblt (pGD->pciBase + BR04_o);
1212}
1213
1214/*******************************************************************************
1215*
1216* Drawing engine bitblt with screen region
1217*/
1218void
1219video_hw_bitblt (unsigned int bpp, /* bytes per pixel */
1220 unsigned int src_x, /* source pos x */
1221 unsigned int src_y, /* source pos y */
1222 unsigned int dst_x, /* dest pos x */
1223 unsigned int dst_y, /* dest pos y */
1224 unsigned int dim_x, /* frame width */
1225 unsigned int dim_y /* frame height */
1226 )
1227{
1228 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
1229 unsigned long br04;
1230
1231 br04 = in32r (pGD->pciBase + BR04_o);
1232
1233 /* to prevent data corruption due to overlap, we have to
1234 * find out if, and how the frames overlaps */
1235 if (src_x < dst_x) {
1236 /* src is more left than dest
1237 * the frame may overlap -> start from right to left */
1238 br04 |= 0x00000100; /* set bit 8 */
1239 src_x += dim_x;
1240 dst_x += dim_x;
1241 } else {
1242 br04 &= 0xfffffeff; /* clear bit 8 left to right */
1243 }
1244 if (src_y < dst_y) {
1245 /* src is higher than dst
1246 * the frame may overlap => start from bottom */
1247 br04 |= 0x00000200; /* set bit 9 */
1248 src_y += dim_y;
1249 dst_y += dim_y;
1250 } else {
1251 br04 &= 0xfffffdff; /* clear bit 9 top to bottom */
1252 }
1253 dim_x *= bpp;
1254 out32r (pGD->pciBase + BR06_o, ((pGD->winSizeX * src_y) + src_x) * pGD->gdfBytesPP); /* source */
1255 out32r (pGD->pciBase + BR07_o, ((pGD->winSizeX * dst_y) + dst_x) * pGD->gdfBytesPP); /* destination */
1256 br04 &= 0xffffff00;
1257 br04 |= 0x000000CC; /* S -> D */
1258 out32r (pGD->pciBase + BR04_o, br04); /* */
1259 out32r (pGD->pciBase + BR08_o, (dim_y << 16) + dim_x); /* start the BITBlt */
1260 video_wait_bitblt (pGD->pciBase + BR04_o);
1261}
1262
1263#endif /* CONFIG_CT69000 */
1264
1265#endif /* CONFIG_VIDEO */