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Stefan Roese5568e612005-11-22 13:20:42 +01001/*
Stefan Roese62534be2006-03-17 10:28:24 +01002 * (C) Copyright 2005-2006
Stefan Roese5568e612005-11-22 13:20:42 +01003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/************************************************************************
27 * board/config_p3p440.h - configuration for Prodrive P3P440
28 ***********************************************************************/
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*-----------------------------------------------------------------------
34 * High Level Configuration Options
35 *----------------------------------------------------------------------*/
36#define CONFIG_P3P440 1 /* Board is P3P440 */
37#define CONFIG_440GP 1 /* Specifc GP support */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +020038#define CONFIG_440 1 /* ... PPC440 family */
Stefan Roese5568e612005-11-22 13:20:42 +010039#define CONFIG_4xx 1 /* ... PPC4xx family */
40#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
41#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
42#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
43
44/*-----------------------------------------------------------------------
45 * Base addresses -- Note these are effective addresses where the
46 * actual resources get mapped (not physical addresses)
47 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
49#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH */
50#define CONFIG_SYS_MONITOR_BASE 0xfffc0000 /* start of monitor */
51#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
53#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
Stefan Roese5568e612005-11-22 13:20:42 +010054
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#define CONFIG_SYS_USB_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000000)
Stefan Roese5568e612005-11-22 13:20:42 +010056
57/*-----------------------------------------------------------------------
58 * Initial RAM & stack pointer (placed in internal SRAM)
59 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
61#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
62#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
Stefan Roese5568e612005-11-22 13:20:42 +010063
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
65#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roese5568e612005-11-22 13:20:42 +010066
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
68#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
Stefan Roese5568e612005-11-22 13:20:42 +010069
70/*-----------------------------------------------------------------------
71 * DDR SDRAM
72 *----------------------------------------------------------------------*/
73#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0*/
Stefan Roese62534be2006-03-17 10:28:24 +010074#define CONFIG_SDRAM_ECC /* enable ECC support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_SDRAM_TABLE { \
Stefan Roese62534be2006-03-17 10:28:24 +010076 {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
77 {(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */
Stefan Roese5568e612005-11-22 13:20:42 +010078
79/*-----------------------------------------------------------------------
80 * Serial Port
81 *----------------------------------------------------------------------*/
Stefan Roese550650d2010-09-20 16:05:31 +020082#define CONFIG_CONS_INDEX 1 /* Use UART0 */
83#define CONFIG_SYS_NS16550
84#define CONFIG_SYS_NS16550_SERIAL
85#define CONFIG_SYS_NS16550_REG_SIZE 1
86#define CONFIG_SYS_NS16550_CLK get_serial_clock()
87
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#undef CONFIG_SYS_EXT_SERIAL_CLOCK
Stefan Roese5568e612005-11-22 13:20:42 +010089#define CONFIG_BAUDRATE 115200
90
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_BAUDRATE_TABLE \
Stefan Roese5568e612005-11-22 13:20:42 +010092 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
93 57600, 115200, 230400, 460800, 921600 }
94
95/*-----------------------------------------------------------------------
96 * I2C
97 *----------------------------------------------------------------------*/
98#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
99#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Stefan Roesed0b0dca2010-04-01 14:37:24 +0200100#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
102#define CONFIG_SYS_I2C_SLAVE 0x7F
103#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
Stefan Roese5568e612005-11-22 13:20:42 +0100104
105/*-----------------------------------------------------------------------
106 * I2C RTC
107 *----------------------------------------------------------------------*/
108#define CONFIG_RTC_MAX6900 1 /* MAX6900 RTC */
109
110/*-----------------------------------------------------------------------
111 * I2C EEPROM (PCF8594C) for environment
112 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */
114#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
Stefan Roese5568e612005-11-22 13:20:42 +0100115/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
117#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */
Stefan Roese5568e612005-11-22 13:20:42 +0100118 /* 8 byte page write mode using */
119 /* last 3 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */
Stefan Roese5568e612005-11-22 13:20:42 +0100121
122/*-----------------------------------------------------------------------
123 * Default configuration (environment varibles...)
124 *----------------------------------------------------------------------*/
125#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100126 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Stefan Roese5568e612005-11-22 13:20:42 +0100127 "echo"
128
129#undef CONFIG_BOOTARGS
130
131#define CONFIG_EXTRA_ENV_SETTINGS \
132 "netdev=eth0\0" \
133 "hostname=p3p440\0" \
134 "nfsargs=setenv bootargs root=/dev/nfs rw " \
135 "nfsroot=${serverip}:${rootpath}\0" \
136 "ramargs=setenv bootargs root=/dev/ram rw\0" \
137 "addip=setenv bootargs ${bootargs} " \
138 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
139 ":${hostname}:${netdev}:off panic=1\0" \
140 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
141 "flash_nfs=run nfsargs addip addtty;" \
142 "bootm ${kernel_addr}\0" \
143 "flash_self=run ramargs addip addtty;" \
144 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
145 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
146 "bootm\0" \
147 "rootpath=/opt/eldk/ppc_4xx\0" \
148 "bootfile=/tftpboot/p3p440/uImage\0" \
149 "kernel_addr=ff800000\0" \
150 "ramdisk_addr=ff810000\0" \
151 "load=tftp 100000 /tftpboot/p3p440/u-boot.bin\0" \
152 "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
153 "cp.b 100000 fffc0000 40000;" \
154 "setenv filesize;saveenv\0" \
Detlev Zundeld8ab58b2008-03-06 16:45:53 +0100155 "upd=run load update\0" \
Stefan Roese2662b402006-04-01 13:41:03 +0200156 "unlock=yes\0" \
Stefan Roese5568e612005-11-22 13:20:42 +0100157 ""
158#define CONFIG_BOOTCOMMAND "run net_nfs"
159
160#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
161
162#define CONFIG_BAUDRATE 115200
163
164#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Stefan Roese5568e612005-11-22 13:20:42 +0100166
Ben Warren96e21f82008-10-27 23:50:15 -0700167#define CONFIG_PPC4xx_EMAC
Stefan Roese5568e612005-11-22 13:20:42 +0100168#define CONFIG_MII 1 /* MII PHY management */
169#define CONFIG_PHY_ADDR 0x1c /* PHY address */
170#define CONFIG_HAS_ETH1
171#define CONFIG_PHY1_ADDR 0x1d /* EMAC1 PHY address */
172#define CONFIG_NET_MULTI 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
Stefan Roese5568e612005-11-22 13:20:42 +0100174
175#define CONFIG_NETCONSOLE /* include NetConsole support */
176
Stefan Roese5568e612005-11-22 13:20:42 +0100177
Jon Loeliger26a34562007-07-04 22:33:17 -0500178/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500179 * BOOTP options
180 */
181#define CONFIG_BOOTP_BOOTFILESIZE
182#define CONFIG_BOOTP_BOOTPATH
183#define CONFIG_BOOTP_GATEWAY
184#define CONFIG_BOOTP_HOSTNAME
185
186
187/*
Jon Loeliger26a34562007-07-04 22:33:17 -0500188 * Command line configuration.
189 */
190#include <config_cmd_default.h>
191
192#define CONFIG_CMD_ASKENV
193#define CONFIG_CMD_DATE
194#define CONFIG_CMD_DHCP
195#define CONFIG_CMD_DIAG
196#define CONFIG_CMD_ELF
197#define CONFIG_CMD_I2C
198#define CONFIG_CMD_IRQ
199#define CONFIG_CMD_MII
200#define CONFIG_CMD_NET
201#define CONFIG_CMD_NFS
202#define CONFIG_CMD_PCI
203#define CONFIG_CMD_PING
204#define CONFIG_CMD_REGINFO
205#define CONFIG_CMD_EEPROM
206#define CONFIG_CMD_SNTP
207
Stefan Roese5568e612005-11-22 13:20:42 +0100208
209#undef CONFIG_WATCHDOG /* watchdog disabled */
210
211/*-----------------------------------------------------------------------
212 * Miscellaneous configurable options
213 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_LONGHELP /* undef to save memory */
215#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger26a34562007-07-04 22:33:17 -0500216#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Stefan Roese5568e612005-11-22 13:20:42 +0100218#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Stefan Roese5568e612005-11-22 13:20:42 +0100220#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
222#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
223#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Stefan Roese5568e612005-11-22 13:20:42 +0100224
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
226#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Stefan Roese5568e612005-11-22 13:20:42 +0100227
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
229#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
Stefan Roese5568e612005-11-22 13:20:42 +0100230
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Stefan Roese5568e612005-11-22 13:20:42 +0100232
233#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
234#define CONFIG_LOOPW 1 /* enable loopw command */
235#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
236#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
237
238/*-----------------------------------------------------------------------
239 * PCI stuff
240 *----------------------------------------------------------------------*/
241/* General PCI */
242#define CONFIG_PCI /* include pci support */
243#define CONFIG_PCI_PNP /* do pci plug-and-play */
244#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
Stefan Roese5568e612005-11-22 13:20:42 +0100246
247/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
Stefan Roese5568e612005-11-22 13:20:42 +0100249
250#define CONFIG_DISABLE_PISE_TEST /* disable PISE test (PCIX only)*/
251
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
253#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
Stefan Roese5568e612005-11-22 13:20:42 +0100254
255/*-----------------------------------------------------------------------
256 * External Bus Controller (EBC) Setup
257 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_FLASH0 0xFF800000
259#define CONFIG_SYS_FLASH1 0xFF000000
260#define CONFIG_SYS_FLASH2 0xFE800000
261#define CONFIG_SYS_FLASH3 0xFE000000
262#define CONFIG_SYS_USB 0xF0000000
Stefan Roese5568e612005-11-22 13:20:42 +0100263
264/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_EBC_PB0AP 0x03050200
266#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
Stefan Roese5568e612005-11-22 13:20:42 +0100267
268/* Memory Bank 1 (Flash Bank 1, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_EBC_PB1AP 0x03050200
270#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FLASH1 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
Stefan Roese5568e612005-11-22 13:20:42 +0100271
272/* Memory Bank 2 (Flash Bank 2, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_EBC_PB2AP 0x03050200
274#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FLASH2 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
Stefan Roese5568e612005-11-22 13:20:42 +0100275
276/* Memory Bank 3 (Flash Bank 3, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_EBC_PB3AP 0x03050200
278#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FLASH3 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
Stefan Roese5568e612005-11-22 13:20:42 +0100279
280/* Memory Bank 7 (USB controller) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_EBC_PB7AP 0x02015000
282#define CONFIG_SYS_EBC_PB7CR (CONFIG_SYS_USB | 0xFE000) /* BAS=0xF00,BS=128MB,BU=R/W,BW=16bit*/
Stefan Roese5568e612005-11-22 13:20:42 +0100283
284/*-----------------------------------------------------------------------
285 * FLASH related
286 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200288#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Stefan Roese5568e612005-11-22 13:20:42 +0100289
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH3, CONFIG_SYS_FLASH2, CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
Stefan Roese5568e612005-11-22 13:20:42 +0100291
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */
293#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
Stefan Roese5568e612005-11-22 13:20:42 +0100294
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
296#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roese5568e612005-11-22 13:20:42 +0100297
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
299#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
Stefan Roese62534be2006-03-17 10:28:24 +0100300
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
302#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
Stefan Roese5568e612005-11-22 13:20:42 +0100303
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200304#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roese5568e612005-11-22 13:20:42 +0100305
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200306#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200308#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Stefan Roese5568e612005-11-22 13:20:42 +0100309
310/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200311#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
312#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Stefan Roese5568e612005-11-22 13:20:42 +0100313
314/*
315 * For booting Linux, the board info and command line data
316 * have to be in the first 8 MB of memory, since this is
317 * the maximum mapped by the Linux kernel during initialization.
318 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Stefan Roese5568e612005-11-22 13:20:42 +0100320
321/*
322 * Internal Definitions
323 *
324 * Boot Flags
325 */
326#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
327#define BOOTFLAG_WARM 0x02 /* Software reboot */
328
Jon Loeliger26a34562007-07-04 22:33:17 -0500329#if defined(CONFIG_CMD_KGDB)
Stefan Roese5568e612005-11-22 13:20:42 +0100330#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
331#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
332#endif
333#endif /* __CONFIG_H */