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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Alex Zuepke <azu@sysgo.de>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenkcd0a9de2004-02-23 20:48:38 +000020 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenkc6097192002-11-03 00:24:07 +000021 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#include <common.h>
30#include <clps7111.h>
wdenkc6097192002-11-03 00:24:07 +000031#include <asm/proc-armv/ptrace.h>
wdenk39539882004-07-01 16:30:44 +000032#include <asm/hardware.h>
wdenkc6097192002-11-03 00:24:07 +000033
wdenk2d1a5372004-02-23 19:30:57 +000034#ifndef CONFIG_NETARM
wdenkc6097192002-11-03 00:24:07 +000035/* we always count down the max. */
36#define TIMER_LOAD_VAL 0xffff
wdenkc6097192002-11-03 00:24:07 +000037/* macro to read the 16 bit timer */
38#define READ_TIMER (IO_TC1D & 0xffff)
Gary Jennejohn6bd24472007-01-24 12:16:56 +010039
40#ifdef CONFIG_LPC2292
41#undef READ_TIMER
42#define READ_TIMER (0xFFFFFFFF - GET32(T0TC))
43#endif
44
wdenk2d1a5372004-02-23 19:30:57 +000045#else
46#define IRQEN (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE))
wdenkcd0a9de2004-02-23 20:48:38 +000047#define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL))
48#define TM2STAT (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_STATUS))
wdenk2d1a5372004-02-23 19:30:57 +000049#define TIMER_LOAD_VAL NETARM_GEN_TSTAT_CTC_MASK
50#define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK)
51#endif
wdenkc6097192002-11-03 00:24:07 +000052
wdenka1f4a3d2004-07-11 22:19:26 +000053#ifdef CONFIG_S3C4510B
54/* require interrupts for the S3C4510B */
55# ifndef CONFIG_USE_IRQ
56# error CONFIG_USE_IRQ _must_ be defined when using CONFIG_S3C4510B
57# else
58static struct _irq_handler IRQ_HANDLER[N_IRQS];
59# endif
60#endif /* CONFIG_S3C4510B */
61
wdenkc6097192002-11-03 00:24:07 +000062#ifdef CONFIG_USE_IRQ
wdenkc6097192002-11-03 00:24:07 +000063void do_irq (struct pt_regs *pt_regs)
64{
Andreas Engel6d0943a2008-01-14 09:06:52 +000065#if defined(CONFIG_S3C4510B)
wdenka1f4a3d2004-07-11 22:19:26 +000066 unsigned int pending;
67
68 while ( (pending = GET_REG( REG_INTOFFSET)) != 0x54) { /* sentinal value for no pending interrutps */
69 IRQ_HANDLER[pending>>2].m_func( IRQ_HANDLER[pending>>2].m_data);
70
71 /* clear pending interrupt */
72 PUT_REG( REG_INTPEND, (1<<(pending>>2)));
73 }
Wolfgang Denk87cb6862005-10-06 17:08:18 +020074#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
75 /* No do_irq() for IntegratorAP/CM720T as yet */
Gary Jennejohn6bd24472007-01-24 12:16:56 +010076#elif defined(CONFIG_LPC2292)
77
78 void (*pfnct)(void);
79
80 pfnct = (void (*)(void))VICVectAddr;
81
82 (*pfnct)();
wdenka1f4a3d2004-07-11 22:19:26 +000083#else
84#error do_irq() not defined for this CPU type
85#endif
wdenkc6097192002-11-03 00:24:07 +000086}
Andreas Engel6d0943a2008-01-14 09:06:52 +000087#endif
wdenka1f4a3d2004-07-11 22:19:26 +000088
89#ifdef CONFIG_S3C4510B
90static void default_isr( void *data) {
91 printf ("default_isr(): called for IRQ %d\n", (int)data);
92}
93
94static void timer_isr( void *data) {
95 unsigned int *pTime = (unsigned int *)data;
96
97 (*pTime)++;
98 if ( !(*pTime % (CFG_HZ/4))) {
99 /* toggle LED 0 */
100 PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1);
101 }
102
103}
104#endif
105
Wolfgang Denk87cb6862005-10-06 17:08:18 +0200106#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
107 /* Use IntegratorAP routines in board/integratorap.c */
108#else
109
Wolfgang Denk96782c62005-10-09 00:22:48 +0200110static ulong timestamp;
111static ulong lastdec;
112
wdenkc6097192002-11-03 00:24:07 +0000113int interrupt_init (void)
114{
wdenk39539882004-07-01 16:30:44 +0000115
116#if defined(CONFIG_NETARM)
wdenkcd0a9de2004-02-23 20:48:38 +0000117 /* disable all interrupts */
wdenk2d1a5372004-02-23 19:30:57 +0000118 IRQEN = 0;
119
120 /* operate timer 2 in non-prescale mode */
121 TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CFG_HZ) |
122 NETARM_GEN_TCTL_ENABLE |
123 NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL));
124
125 /* set timer 2 counter */
126 lastdec = TIMER_LOAD_VAL;
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200127#elif defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
wdenkc6097192002-11-03 00:24:07 +0000128 /* disable all interrupts */
129 IO_INTMR1 = 0;
130
131 /* operate timer 1 in prescale mode */
132 IO_SYSCON1 |= SYSCON1_TC1M;
133
134 /* select 2kHz clock source for timer 1 */
135 IO_SYSCON1 &= ~SYSCON1_TC1S;
136
137 /* set timer 1 counter */
138 lastdec = IO_TC1D = TIMER_LOAD_VAL;
wdenk39539882004-07-01 16:30:44 +0000139#elif defined(CONFIG_S3C4510B)
wdenka1f4a3d2004-07-11 22:19:26 +0000140 int i;
141
142 /* install default interrupt handlers */
143 for ( i = 0; i < N_IRQS; i++) {
144 IRQ_HANDLER[i].m_data = (void *)i;
145 IRQ_HANDLER[i].m_func = default_isr;
146 }
147
148 /* configure interrupts for IRQ mode */
149 PUT_REG( REG_INTMODE, 0x0);
150 /* clear any pending interrupts */
151 PUT_REG( REG_INTPEND, 0x1FFFFF);
152
wdenk39539882004-07-01 16:30:44 +0000153 lastdec = 0;
wdenka1f4a3d2004-07-11 22:19:26 +0000154
155 /* install interrupt handler for timer */
156 IRQ_HANDLER[INT_TIMER0].m_data = (void *)&timestamp;
157 IRQ_HANDLER[INT_TIMER0].m_func = timer_isr;
158
159 /* configure free running timer 0 */
160 PUT_REG( REG_TMOD, 0x0);
161 /* Stop timer 0 */
162 CLR_REG( REG_TMOD, TM0_RUN);
163
164 /* Configure for interval mode */
165 CLR_REG( REG_TMOD, TM1_TOGGLE);
166
167 /*
168 * Load Timer data register with count down value.
169 * count_down_val = CFG_SYS_CLK_FREQ/CFG_HZ
170 */
171 PUT_REG( REG_TDATA0, (CFG_SYS_CLK_FREQ / CFG_HZ));
172
173 /*
174 * Enable global interrupt
175 * Enable timer0 interrupt
176 */
177 CLR_REG( REG_INTMASK, ((1<<INT_GLOBAL) | (1<<INT_TIMER0)));
178
179 /* Start timer */
180 SET_REG( REG_TMOD, TM0_RUN);
Gary Jennejohn6bd24472007-01-24 12:16:56 +0100181#elif defined(CONFIG_LPC2292)
182 PUT32(T0IR, 0); /* disable all timer0 interrupts */
183 PUT32(T0TCR, 0); /* disable timer0 */
184 PUT32(T0PR, CFG_SYS_CLK_FREQ / CFG_HZ);
185 PUT32(T0MCR, 0);
186 PUT32(T0TC, 0);
187 PUT32(T0TCR, 1); /* enable timer0 */
wdenka1f4a3d2004-07-11 22:19:26 +0000188
wdenk39539882004-07-01 16:30:44 +0000189#else
190#error No interrupt_init() defined for this CPU type
wdenk2d1a5372004-02-23 19:30:57 +0000191#endif
wdenkc6097192002-11-03 00:24:07 +0000192 timestamp = 0;
193
194 return (0);
195}
196
Wolfgang Denk87cb6862005-10-06 17:08:18 +0200197#endif /* ! IntegratorAP */
198
wdenkc6097192002-11-03 00:24:07 +0000199/*
200 * timer without interrupts
201 */
202
wdenk39539882004-07-01 16:30:44 +0000203
Gary Jennejohn6bd24472007-01-24 12:16:56 +0100204#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) || defined(CONFIG_LPC2292)
wdenk39539882004-07-01 16:30:44 +0000205
wdenkc6097192002-11-03 00:24:07 +0000206void reset_timer (void)
207{
208 reset_timer_masked ();
209}
210
211ulong get_timer (ulong base)
212{
213 return get_timer_masked () - base;
214}
215
216void set_timer (ulong t)
217{
218 timestamp = t;
219}
220
221void udelay (unsigned long usec)
222{
223 ulong tmo;
224
225 tmo = usec / 1000;
226 tmo *= CFG_HZ;
227 tmo /= 1000;
228
229 tmo += get_timer (0);
230
231 while (get_timer_masked () < tmo)
Gary Jennejohn6bd24472007-01-24 12:16:56 +0100232#ifdef CONFIG_LPC2292
233 /* GJ - not sure whether this is really needed or a misunderstanding */
234 __asm__ __volatile__(" nop");
235#else
wdenkc6097192002-11-03 00:24:07 +0000236 /*NOP*/;
Gary Jennejohn6bd24472007-01-24 12:16:56 +0100237#endif
wdenkc6097192002-11-03 00:24:07 +0000238}
239
240void reset_timer_masked (void)
241{
242 /* reset time */
243 lastdec = READ_TIMER;
244 timestamp = 0;
245}
246
247ulong get_timer_masked (void)
248{
249 ulong now = READ_TIMER;
250
251 if (lastdec >= now) {
252 /* normal mode */
253 timestamp += lastdec - now;
254 } else {
255 /* we have an overflow ... */
256 timestamp += lastdec + TIMER_LOAD_VAL - now;
257 }
258 lastdec = now;
259
260 return timestamp;
261}
262
263void udelay_masked (unsigned long usec)
264{
265 ulong tmo;
wdenk101e8df2005-04-04 12:08:28 +0000266 ulong endtime;
267 signed long diff;
wdenkc6097192002-11-03 00:24:07 +0000268
wdenk101e8df2005-04-04 12:08:28 +0000269 if (usec >= 1000) {
270 tmo = usec / 1000;
271 tmo *= CFG_HZ;
272 tmo /= 1000;
273 } else {
274 tmo = usec * CFG_HZ;
275 tmo /= (1000*1000);
276 }
wdenkc6097192002-11-03 00:24:07 +0000277
wdenk101e8df2005-04-04 12:08:28 +0000278 endtime = get_timer_masked () + tmo;
wdenkc6097192002-11-03 00:24:07 +0000279
wdenk101e8df2005-04-04 12:08:28 +0000280 do {
281 ulong now = get_timer_masked ();
282 diff = endtime - now;
283 } while (diff >= 0);
wdenkc6097192002-11-03 00:24:07 +0000284}
wdenk39539882004-07-01 16:30:44 +0000285
286#elif defined(CONFIG_S3C4510B)
287
wdenka1f4a3d2004-07-11 22:19:26 +0000288ulong get_timer (ulong base)
289{
290 return timestamp - base;
291}
wdenk39539882004-07-01 16:30:44 +0000292
293void udelay (unsigned long usec)
294{
wdenka1f4a3d2004-07-11 22:19:26 +0000295 u32 ticks;
wdenk39539882004-07-01 16:30:44 +0000296
wdenka1f4a3d2004-07-11 22:19:26 +0000297 ticks = (usec * CFG_HZ) / 1000000;
wdenk39539882004-07-01 16:30:44 +0000298
wdenka1f4a3d2004-07-11 22:19:26 +0000299 ticks += get_timer (0);
wdenk39539882004-07-01 16:30:44 +0000300
wdenka1f4a3d2004-07-11 22:19:26 +0000301 while (get_timer (0) < ticks)
302 /*NOP*/;
wdenk39539882004-07-01 16:30:44 +0000303
wdenk39539882004-07-01 16:30:44 +0000304}
305
Wolfgang Denk87cb6862005-10-06 17:08:18 +0200306#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
307 /* No timer routines for IntegratorAP/CM720T as yet */
wdenk39539882004-07-01 16:30:44 +0000308#else
309#error Timer routines not defined for this CPU type
310#endif