Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / c2fd3f57040d4d8e858f0449afe46416cfad95da / . / include / configs / socfpga_cyclone5.h
blob: 1227711f32c70de8db00c5963d5387ac7fc03470 [file] [log] [blame]
Dinh Nguyen77754402012-10-04 06:46:02 +0000[diff] [blame]1/*
Pavel Machek5095ee02014-09-08 14:08:45 +0200[diff] [blame]2 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
Dinh Nguyen77754402012-10-04 06:46:02 +0000[diff] [blame]3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +0200[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0+
Dinh Nguyen77754402012-10-04 06:46:02 +0000[diff] [blame]5 */
Pavel Machek5095ee02014-09-08 14:08:45 +0200[diff] [blame]6#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__
7#define __CONFIG_SOCFPGA_CYCLONE5_H__
Dinh Nguyen77754402012-10-04 06:46:02 +0000[diff] [blame]8
9#include <asm/arch/socfpga_base_addrs.h>
Chin Liang See5d649d22013-09-11 11:24:48 -0500[diff] [blame]10#include "../../board/altera/socfpga/pinmux_config.h"
Chin Liang Seedc4d4aa2014-06-10 01:17:42 -0500[diff] [blame]11#include "../../board/altera/socfpga/iocsr_config.h"
Chin Liang Seeddfeb0a2014-03-04 22:13:53 -0600[diff] [blame]12#include "../../board/altera/socfpga/pll_config.h"
Dinh Nguyen77754402012-10-04 06:46:02 +0000[diff] [blame]13
Marek Vasut47f9b4e2014-09-08 14:08:45 +0200[diff] [blame]14/* U-Boot Commands */
15#define CONFIG_SYS_NO_FLASH
16#include <config_cmd_default.h>
17#define CONFIG_DOS_PARTITION
18#define CONFIG_FAT_WRITE
19#define CONFIG_HW_WATCHDOG
20
21#define CONFIG_CMD_ASKENV
22#define CONFIG_CMD_BOOTZ
23#define CONFIG_CMD_CACHE
Marek Vasute5e87172014-12-30 20:04:20 +0100[diff] [blame]24#define CONFIG_CMD_DFU
Marek Vasut47f9b4e2014-09-08 14:08:45 +0200[diff] [blame]25#define CONFIG_CMD_DHCP
26#define CONFIG_CMD_EXT4
27#define CONFIG_CMD_EXT4_WRITE
28#define CONFIG_CMD_FAT
29#define CONFIG_CMD_FPGA
Marek Vasut2f210632014-09-19 13:28:47 +0200[diff] [blame]30#define CONFIG_CMD_FS_GENERIC
Marek Vasut47f9b4e2014-09-08 14:08:45 +0200[diff] [blame]31#define CONFIG_CMD_GREPENV
32#define CONFIG_CMD_MII
33#define CONFIG_CMD_MMC
34#define CONFIG_CMD_NET
35#define CONFIG_CMD_PING
36#define CONFIG_CMD_SETEXPR
Marek Vasute5e87172014-12-30 20:04:20 +0100[diff] [blame]37#define CONFIG_CMD_USB
38#define CONFIG_CMD_USB_MASS_STORAGE
Marek Vasut47f9b4e2014-09-08 14:08:45 +0200[diff] [blame]39
Marek Vasut47f9b4e2014-09-08 14:08:45 +0200[diff] [blame]40
Pavel Machek5095ee02014-09-08 14:08:45 +0200[diff] [blame]41/* Memory configurations */
Marek Vasut47f9b4e2014-09-08 14:08:45 +0200[diff] [blame]42#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
Dinh Nguyen77754402012-10-04 06:46:02 +0000[diff] [blame]43
Marek Vasut47f9b4e2014-09-08 14:08:45 +0200[diff] [blame]44/* Booting Linux */
45#define CONFIG_BOOTDELAY 3
46#define CONFIG_BOOTFILE "zImage"
Anatolij Gustschin116f5d52014-11-07 01:12:03 +0100[diff] [blame]47#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
Chin Liang See97ce2742014-09-19 05:33:19 -0500[diff] [blame]48#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
Marek Vasut47f9b4e2014-09-08 14:08:45 +0200[diff] [blame]49#define CONFIG_BOOTCOMMAND "run ramboot"
Chin Liang See97ce2742014-09-19 05:33:19 -0500[diff] [blame]50#else
Marek Vasut47f9b4e2014-09-08 14:08:45 +0200[diff] [blame]51#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
52#endif
53#define CONFIG_LOADADDR 0x8000
54#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
55
Pavel Machek5095ee02014-09-08 14:08:45 +0200[diff] [blame]56/* Ethernet on SoC (EMAC) */
57#if defined(CONFIG_CMD_NET)
Marek Vasut5a1d0ad2014-10-10 01:50:23 +0200[diff] [blame]58#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS
Marek Vasut47f9b4e2014-09-08 14:08:45 +0200[diff] [blame]59#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
Marek Vasut47f9b4e2014-09-08 14:08:45 +0200[diff] [blame]60
61/* PHY */
Marek Vasut47f9b4e2014-09-08 14:08:45 +0200[diff] [blame]62#define CONFIG_PHY_MICREL
63#define CONFIG_PHY_MICREL_KSZ9021
64#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
65#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
66#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
67#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
68
Chin Liang See97ce2742014-09-19 05:33:19 -0500[diff] [blame]69#endif
Dinh Nguyen77754402012-10-04 06:46:02 +0000[diff] [blame]70
Marek Vasute5e87172014-12-30 20:04:20 +0100[diff] [blame]71/* USB */
72#ifdef CONFIG_CMD_USB
73#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
74#endif
75#define CONFIG_G_DNL_MANUFACTURER "Altera"
76
Pavel Machek5095ee02014-09-08 14:08:45 +0200[diff] [blame]77/* Extra Environment */
78#define CONFIG_HOSTNAME socfpga_cyclone5
Dinh Nguyen77754402012-10-04 06:46:02 +0000[diff] [blame]79
80#define CONFIG_EXTRA_ENV_SETTINGS \
81 "verify=n\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200[diff] [blame]82 "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
Dinh Nguyen77754402012-10-04 06:46:02 +0000[diff] [blame]83 "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
84 "bootm ${loadaddr} - ${fdt_addr}\0" \
Chin Liang See97ce2742014-09-19 05:33:19 -0500[diff] [blame]85 "bootimage=zImage\0" \
Dinh Nguyen77754402012-10-04 06:46:02 +0000[diff] [blame]86 "fdt_addr=100\0" \
Chin Liang See97ce2742014-09-19 05:33:19 -0500[diff] [blame]87 "fdtimage=socfpga.dtb\0" \
88 "fsloadcmd=ext2load\0" \
89 "bootm ${loadaddr} - ${fdt_addr}\0" \
90 "mmcroot=/dev/mmcblk0p2\0" \
91 "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
92 " root=${mmcroot} rw rootwait;" \
93 "bootz ${loadaddr} - ${fdt_addr}\0" \
94 "mmcload=mmc rescan;" \
Marek Vasut2f210632014-09-19 13:28:47 +0200[diff] [blame]95 "load mmc 0:1 ${loadaddr} ${bootimage};" \
96 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
Dinh Nguyen77754402012-10-04 06:46:02 +0000[diff] [blame]97 "qspiroot=/dev/mtdblock0\0" \
98 "qspirootfstype=jffs2\0" \
99 "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
100 " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
101 "bootm ${loadaddr} - ${fdt_addr}\0"
102
Pavel Machek5095ee02014-09-08 14:08:45 +0200[diff] [blame]103/* The rest of the configuration is shared */
104#include <configs/socfpga_common.h>
Dinh Nguyen77754402012-10-04 06:46:02 +0000[diff] [blame]105
Pavel Machek5095ee02014-09-08 14:08:45 +0200[diff] [blame]106#endif /* __CONFIG_SOCFPGA_CYCLONE5_H__ */