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Wolfgang Denk3df5bea2005-10-09 01:41:48 +02001/***********************************************************************
2 *
3 * Copyright 2003 by FS Forth-Systeme GmbH.
4 * All rights reserved.
5 *
6 * $Id$
7 * @Author: Markus Pietrek
8 * @Descr: Defines the NS7520 ethernet registers.
9 * Stick with the old ETH prefix names instead going to the
10 * new EFE names in the manual.
11 * NS7520_ETH_* refer to NS7520 Hardware
12 * Reference/January 2003 [1]
13 * PHY_LXT971_* refer to Intel LXT971 Datasheet
14 * #249414 Rev. 02 [2]
15 * Partly derived from netarm_eth_module.h
16 *
17 * Modified by Arthur Shipkowski <art@videon-central.com> from the
18 * Linux version to be properly formatted for U-Boot (i.e. no C++ comments)
19 *
20 ***********************************************************************/
21
22#ifndef FS_NS7520_ETH_H
23#define FS_NS7520_ETH_H
24
25#ifdef CONFIG_DRIVER_NS7520_ETHERNET
26
Hugo Villeneuvefec61432008-06-18 12:10:31 -040027#include <miiphy.h>
Wolfgang Denk3df5bea2005-10-09 01:41:48 +020028#include "lxt971a.h"
29
30/* The port addresses */
31
Wolfgang Denk53677ef2008-05-20 16:00:29 +020032#define NS7520_ETH_MODULE_BASE (0xFF800000)
Wolfgang Denk3df5bea2005-10-09 01:41:48 +020033
34#define get_eth_reg_addr(c) \
35 ((volatile unsigned int*) ( NS7520_ETH_MODULE_BASE+(unsigned int) (c)))
36#define NS7520_ETH_EGCR (0x0000) /* Ethernet Gen Control */
37#define NS7520_ETH_EGSR (0x0004) /* Ethernet Gen Status */
38#define NS7520_ETH_FIFO (0x0008) /* FIFO Data */
39#define NS7520_ETH_FIFOL (0x000C) /* FIFO Data Last */
40#define NS7520_ETH_ETSR (0x0010) /* Ethernet Transmit Status */
41#define NS7520_ETH_ERSR (0x0014) /* Ethernet Receive Status */
42#define NS7520_ETH_MAC1 (0x0400) /* MAC Config 1 */
43#define NS7520_ETH_MAC2 (0x0404) /* MAC Config 2 */
44#define NS7520_ETH_IPGT (0x0408) /* Back2Back InterPacket Gap */
45#define NS7520_ETH_IPGR (0x040C) /* non back2back InterPacket Gap */
46#define NS7520_ETH_CLRT (0x0410) /* Collision Window/Retry */
47#define NS7520_ETH_MAXF (0x0414) /* Maximum Frame Register */
48#define NS7520_ETH_SUPP (0x0418) /* PHY Support */
49#define NS7520_ETH_TEST (0x041C) /* Test Register */
50#define NS7520_ETH_MCFG (0x0420) /* MII Management Configuration */
51#define NS7520_ETH_MCMD (0x0424) /* MII Management Command */
52#define NS7520_ETH_MADR (0x0428) /* MII Management Address */
53#define NS7520_ETH_MWTD (0x042C) /* MII Management Write Data */
54#define NS7520_ETH_MRDD (0x0430) /* MII Management Read Data */
55#define NS7520_ETH_MIND (0x0434) /* MII Management Indicators */
56#define NS7520_ETH_SMII (0x0438) /* SMII Status Register */
57#define NS7520_ETH_SA1 (0x0440) /* Station Address 1 */
58#define NS7520_ETH_SA2 (0x0444) /* Station Address 2 */
59#define NS7520_ETH_SA3 (0x0448) /* Station Address 3 */
60#define NS7520_ETH_SAFR (0x05C0) /* Station Address Filter */
61#define NS7520_ETH_HT1 (0x05D0) /* Hash Table 1 */
62#define NS7520_ETH_HT2 (0x05D4) /* Hash Table 2 */
63#define NS7520_ETH_HT3 (0x05D8) /* Hash Table 3 */
64#define NS7520_ETH_HT4 (0x05DC) /* Hash Table 4 */
65
66/* EGCR Ethernet General Control Register Bit Fields*/
67
68#define NS7520_ETH_EGCR_ERX (0x80000000) /* Enable Receive FIFO */
69#define NS7520_ETH_EGCR_ERXDMA (0x40000000) /* Enable Receive DMA */
70#define NS7520_ETH_EGCR_ERXLNG (0x20000000) /* Accept Long packets */
71#define NS7520_ETH_EGCR_ERXSHT (0x10000000) /* Accept Short packets */
72#define NS7520_ETH_EGCR_ERXREG (0x08000000) /* Enable Receive Data Interrupt */
73#define NS7520_ETH_EGCR_ERFIFOH (0x04000000) /* Enable Receive Half-Full Int */
74#define NS7520_ETH_EGCR_ERXBR (0x02000000) /* Enable Receive buffer ready */
75#define NS7520_ETH_EGCR_ERXBAD (0x01000000) /* Accept bad receive packets */
76#define NS7520_ETH_EGCR_ETX (0x00800000) /* Enable Transmit FIFO */
77#define NS7520_ETH_EGCR_ETXDMA (0x00400000) /* Enable Transmit DMA */
78#define NS7520_ETH_EGCR_ETXWM_R (0x00300000) /* Enable Transmit FIFO mark Reserv */
79#define NS7520_ETH_EGCR_ETXWM_75 (0x00200000) /* Enable Transmit FIFO mark 75% */
80#define NS7520_ETH_EGCR_ETXWM_50 (0x00100000) /* Enable Transmit FIFO mark 50% */
81#define NS7520_ETH_EGCR_ETXWM_25 (0x00000000) /* Enable Transmit FIFO mark 25% */
82#define NS7520_ETH_EGCR_ETXREG (0x00080000) /* Enable Transmit Data Read Int */
83#define NS7520_ETH_EGCR_ETFIFOH (0x00040000) /* Enable Transmit Fifo Half Int */
84#define NS7520_ETH_EGCR_ETXBC (0x00020000) /* Enable Transmit Buffer Compl Int */
85#define NS7520_ETH_EGCR_EFULLD (0x00010000) /* Enable Full Duplex Operation */
86#define NS7520_ETH_EGCR_MODE_MA (0x0000C000) /* Mask */
87#define NS7520_ETH_EGCR_MODE_SEE (0x0000C000) /* 10 Mbps SEEQ ENDEC PHY */
88#define NS7520_ETH_EGCR_MODE_LEV (0x00008000) /* 10 Mbps Level1 ENDEC PHY */
89#define NS7520_ETH_EGCR_RES1 (0x00002000) /* Reserved */
90#define NS7520_ETH_EGCR_RXCINV (0x00001000) /* Invert the receive clock input */
91#define NS7520_ETH_EGCR_TXCINV (0x00000800) /* Invert the transmit clock input */
92#define NS7520_ETH_EGCR_PNA (0x00000400) /* pSOS pNA buffer */
93#define NS7520_ETH_EGCR_MAC_RES (0x00000200) /* MAC Software reset */
94#define NS7520_ETH_EGCR_ITXA (0x00000100) /* Insert Transmit Source Address */
95#define NS7520_ETH_EGCR_ENDEC_MA (0x000000FC) /* ENDEC media control bits */
96#define NS7520_ETH_EGCR_EXINT_MA (0x00000003) /* Mask */
97#define NS7520_ETH_EGCR_EXINT_RE (0x00000003) /* Reserved */
98#define NS7520_ETH_EGCR_EXINT_TP (0x00000002) /* TP-PMD Mode */
99#define NS7520_ETH_EGCR_EXINT_10 (0x00000001) /* 10-MBit Mode */
100#define NS7520_ETH_EGCR_EXINT_NO (0x00000000) /* MII normal operation */
101
102/* EGSR Ethernet General Status Register Bit Fields*/
103
104#define NS7520_ETH_EGSR_RES1 (0xC0000000) /* Reserved */
105#define NS7520_ETH_EGSR_RXFDB_MA (0x30000000) /* Receive FIFO mask */
106#define NS7520_ETH_EGSR_RXFDB_3 (0x30000000) /* Receive FIFO 3 bytes available */
107#define NS7520_ETH_EGSR_RXFDB_2 (0x20000000) /* Receive FIFO 2 bytes available */
108#define NS7520_ETH_EGCR_RXFDB_1 (0x10000000) /* Receive FIFO 1 Bytes available */
109#define NS7520_ETH_EGCR_RXFDB_4 (0x00000000) /* Receive FIFO 4 Bytes available */
110#define NS7520_ETH_EGSR_RXREGR (0x08000000) /* Receive Register Ready */
111#define NS7520_ETH_EGSR_RXFIFOH (0x04000000) /* Receive FIFO Half Full */
112#define NS7520_ETH_EGSR_RXBR (0x02000000) /* Receive Buffer Ready */
113#define NS7520_ETH_EGSR_RXSKIP (0x01000000) /* Receive Buffer Skip */
114#define NS7520_ETH_EGSR_RES2 (0x00F00000) /* Reserved */
115#define NS7520_ETH_EGSR_TXREGE (0x00080000) /* Transmit Register Empty */
116#define NS7520_ETH_EGSR_TXFIFOH (0x00040000) /* Transmit FIFO half empty */
117#define NS7520_ETH_EGSR_TXBC (0x00020000) /* Transmit buffer complete */
118#define NS7520_ETH_EGSR_TXFIFOE (0x00010000) /* Transmit FIFO empty */
119#define NS7520_ETH_EGSR_RXPINS (0x0000FC00) /* ENDEC Phy Status */
120#define NS7520_ETH_EGSR_RES3 (0x000003FF) /* Reserved */
121
122/* ETSR Ethernet Transmit Status Register Bit Fields*/
123
124#define NS7520_ETH_ETSR_RES1 (0xFFFF0000) /* Reserved */
125#define NS7520_ETH_ETSR_TXOK (0x00008000) /* Packet transmitted OK */
126#define NS7520_ETH_ETSR_TXBR (0x00004000) /* Broadcast packet transmitted */
127#define NS7520_ETH_ETSR_TXMC (0x00002000) /* Multicast packet transmitted */
128#define NS7520_ETH_ETSR_TXAL (0x00001000) /* Transmit abort - late collision */
129#define NS7520_ETH_ETSR_TXAED (0x00000800) /* Transmit abort - deferral */
130#define NS7520_ETH_ETSR_TXAEC (0x00000400) /* Transmit abort - exc collisions */
131#define NS7520_ETH_ETSR_TXAUR (0x00000200) /* Transmit abort - underrun */
132#define NS7520_ETH_ETSR_TXAJ (0x00000100) /* Transmit abort - jumbo */
133#define NS7520_ETH_ETSR_RES2 (0x00000080) /* Reserved */
134#define NS7520_ETH_ETSR_TXDEF (0x00000040) /* Transmit Packet Deferred */
135#define NS7520_ETH_ETSR_TXCRC (0x00000020) /* Transmit CRC error */
136#define NS7520_ETH_ETSR_RES3 (0x00000010) /* Reserved */
137#define NS7520_ETH_ETSR_TXCOLC (0x0000000F) /* Transmit Collision Count */
138
139/* ERSR Ethernet Receive Status Register Bit Fields*/
140
141#define NS7520_ETH_ERSR_RXSIZE (0xFFFF0000) /* Receive Buffer Size */
142#define NS7520_ETH_ERSR_RXCE (0x00008000) /* Receive Carrier Event */
143#define NS7520_ETH_ERSR_RXDV (0x00004000) /* Receive Data Violation Event */
144#define NS7520_ETH_ERSR_RXOK (0x00002000) /* Receive Packet OK */
145#define NS7520_ETH_ERSR_RXBR (0x00001000) /* Receive Broadcast Packet */
146#define NS7520_ETH_ERSR_RXMC (0x00000800) /* Receive Multicast Packet */
147#define NS7520_ETH_ERSR_RXCRC (0x00000400) /* Receive Packet has CRC error */
148#define NS7520_ETH_ERSR_RXDR (0x00000200) /* Receive Packet has dribble error */
149#define NS7520_ETH_ERSR_RXCV (0x00000100) /* Receive Packet code violation */
150#define NS7520_ETH_ERSR_RXLNG (0x00000080) /* Receive Packet too long */
151#define NS7520_ETH_ERSR_RXSHT (0x00000040) /* Receive Packet too short */
152#define NS7520_ETH_ERSR_ROVER (0x00000020) /* Recive overflow */
153#define NS7520_ETH_ERSR_RES (0x0000001F) /* Reserved */
154
155/* MAC1 MAC Configuration Register 1 Bit Fields*/
156
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200157#define NS7520_ETH_MAC1_RES1 (0xFFFF0000) /* Reserved */
Wolfgang Denk3df5bea2005-10-09 01:41:48 +0200158#define NS7520_ETH_MAC1_SRST (0x00008000) /* Soft Reset */
159#define NS7520_ETH_MAC1_SIMMRST (0x00004000) /* Simulation Reset */
160#define NS7520_ETH_MAC1_RES2 (0x00003000) /* Reserved */
161#define NS7520_ETH_MAC1_RPEMCSR (0x00000800) /* Reset PEMCS/RX */
162#define NS7520_ETH_MAC1_RPERFUN (0x00000400) /* Reset PERFUN */
163#define NS7520_ETH_MAC1_RPEMCST (0x00000200) /* Reset PEMCS/TX */
164#define NS7520_ETH_MAC1_RPETFUN (0x00000100) /* Reset PETFUN */
165#define NS7520_ETH_MAC1_RES3 (0x000000E0) /* Reserved */
166#define NS7520_ETH_MAC1_LOOPBK (0x00000010) /* Internal Loopback */
167#define NS7520_ETH_MAC1_TXFLOW (0x00000008) /* TX flow control */
168#define NS7520_ETH_MAC1_RXFLOW (0x00000004) /* RX flow control */
169#define NS7520_ETH_MAC1_PALLRX (0x00000002) /* Pass ALL receive frames */
170#define NS7520_ETH_MAC1_RXEN (0x00000001) /* Receive enable */
171
172/* MAC Configuration Register 2 Bit Fields*/
173
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200174#define NS7520_ETH_MAC2_RES1 (0xFFFF8000) /* Reserved */
Wolfgang Denk3df5bea2005-10-09 01:41:48 +0200175#define NS7520_ETH_MAC2_EDEFER (0x00004000) /* Excess Deferral */
176#define NS7520_ETH_MAC2_BACKP (0x00002000) /* Backpressure/NO back off */
177#define NS7520_ETH_MAC2_NOBO (0x00001000) /* No back off */
178#define NS7520_ETH_MAC2_RES2 (0x00000C00) /* Reserved */
179#define NS7520_ETH_MAC2_LONGP (0x00000200) /* Long Preable enforcement */
180#define NS7520_ETH_MAC2_PUREP (0x00000100) /* Pure preamble enforcement */
181#define NS7520_ETH_MAC2_AUTOP (0x00000080) /* Auto detect PAD enable */
182#define NS7520_ETH_MAC2_VLANP (0x00000040) /* VLAN pad enable */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200183#define NS7520_ETH_MAC2_PADEN (0x00000020) /* PAD/CRC enable */
Wolfgang Denk3df5bea2005-10-09 01:41:48 +0200184#define NS7520_ETH_MAC2_CRCEN (0x00000010) /* CRC enable */
185#define NS7520_ETH_MAC2_DELCRC (0x00000008) /* Delayed CRC */
186#define NS7520_ETH_MAC2_HUGE (0x00000004) /* Huge frame enable */
187#define NS7520_ETH_MAC2_FLENC (0x00000002) /* Frame length checking */
188#define NS7520_ETH_MAC2_FULLD (0x00000001) /* Full duplex */
189
190/* IPGT Back-to-Back Inter-Packet-Gap Register Bit Fields*/
191
192#define NS7520_ETH_IPGT_RES (0xFFFFFF80) /* Reserved */
193#define NS7520_ETH_IPGT_IPGT (0x0000007F) /* Back-to-Back Interpacket Gap */
194
195/* IPGR Non Back-to-Back Inter-Packet-Gap Register Bit Fields*/
196
197#define NS7520_ETH_IPGR_RES1 (0xFFFF8000) /* Reserved */
198#define NS7520_ETH_IPGR_IPGR1 (0x00007F00) /* Non Back-to-back Interpacket Gap */
199#define NS7520_ETH_IPGR_RES2 (0x00000080) /* Reserved */
200#define NS7520_ETH_IPGR_IPGR2 (0x0000007F) /* Non back-to-back Interpacket Gap */
201
202/* CLRT Collision Windows/Collision Retry Register Bit Fields*/
203
204#define NS7520_ETH_CLRT_RES1 (0xFFFFC000) /* Reserved */
205#define NS7520_ETH_CLRT_CWIN (0x00003F00) /* Collision Windows */
206#define NS7520_ETH_CLRT_RES2 (0x000000F0) /* Reserved */
207#define NS7520_ETH_CLRT_RETX (0x0000000F) /* Retransmission maximum */
208
209/* MAXF Maximum Frame Register Bit Fields*/
210
211#define NS7520_ETH_MAXF_RES1 (0xFFFF0000) /* Reserved */
212#define NS7520_ETH_MAXF_MAXF (0x0000FFFF) /* Maximum frame length */
213
214/* SUPP PHY Support Register Bit Fields*/
215
216#define NS7520_ETH_SUPP_RES1 (0xFFFFFF00) /* Reserved */
217#define NS7520_ETH_SUPP_RPE100X (0x00000080) /* Reset PE100X module */
218#define NS7520_ETH_SUPP_FORCEQ (0x00000040) /* Force Quit */
219#define NS7520_ETH_SUPP_NOCIPH (0x00000020) /* No Cipher */
220#define NS7520_ETH_SUPP_DLINKF (0x00000010) /* Disable link fail */
221#define NS7520_ETH_SUPP_RPE10T (0x00000008) /* Reset PE10T module */
222#define NS7520_ETH_SUPP_RES2 (0x00000004) /* Reserved */
223#define NS7520_ETH_SUPP_JABBER (0x00000002) /* Enable Jabber protection */
224#define NS7520_ETH_SUPP_BITMODE (0x00000001) /* Bit Mode */
225
226/* TEST Register Bit Fields*/
227
228#define NS7520_ETH_TEST_RES1 (0xFFFFFFF8) /* Reserved */
229#define NS7520_ETH_TEST_TBACK (0x00000004) /* Test backpressure */
230#define NS7520_ETH_TEST_TPAUSE (0x00000002) /* Test Pause */
231#define NS7520_ETH_TEST_SPQ (0x00000001) /* Shortcut pause quanta */
232
233/* MCFG MII Management Configuration Register Bit Fields*/
234
235#define NS7520_ETH_MCFG_RES1 (0xFFFF0000) /* Reserved */
236#define NS7520_ETH_MCFG_RMIIM (0x00008000) /* Reset MII management */
237#define NS7520_ETH_MCFG_RES2 (0x00007FE0) /* Reserved */
238#define NS7520_ETH_MCFG_CLKS_MA (0x0000001C) /* Clock Select */
239#define NS7520_ETH_MCFG_CLKS_4 (0x00000004) /* Sysclk / 4 */
240#define NS7520_ETH_MCFG_CLKS_6 (0x00000008) /* Sysclk / 6 */
241#define NS7520_ETH_MCFG_CLKS_8 (0x0000000C) /* Sysclk / 8 */
242#define NS7520_ETH_MCFG_CLKS_10 (0x00000010) /* Sysclk / 10 */
243#define NS7520_ETH_MCFG_CLKS_14 (0x00000014) /* Sysclk / 14 */
244#define NS7520_ETH_MCFG_CLKS_20 (0x00000018) /* Sysclk / 20 */
245#define NS7520_ETH_MCFG_CLKS_28 (0x0000001C) /* Sysclk / 28 */
246#define NS7520_ETH_MCFG_SPRE (0x00000002) /* Suppress preamble */
247#define NS7520_ETH_MCFG_SCANI (0x00000001) /* Scan increment */
248
249/* MCMD MII Management Command Register Bit Fields*/
250
251#define NS7520_ETH_MCMD_RES1 (0xFFFFFFFC) /* Reserved */
252#define NS7520_ETH_MCMD_SCAN (0x00000002) /* Automatically Scan for Read Data */
253#define NS7520_ETH_MCMD_READ (0x00000001) /* Single scan for Read Data */
254
255/* MCMD MII Management Address Register Bit Fields*/
256
257#define NS7520_ETH_MADR_RES1 (0xFFFFE000) /* Reserved */
258#define NS7520_ETH_MADR_DADR (0x00001F00) /* MII PHY device address */
259#define NS7520_ETH_MADR_RES2 (0x000000E0) /* Reserved */
260#define NS7520_ETH_MADR_RADR (0x0000001F) /* MII PHY register address */
261
262/* MWTD MII Management Write Data Register Bit Fields*/
263
264#define NS7520_ETH_MWTD_RES1 (0xFFFF0000) /* Reserved */
265#define NS7520_ETH_MWTD_MWTD (0x0000FFFF) /* MII Write Data */
266
267/* MRRD MII Management Read Data Register Bit Fields*/
268
269#define NS7520_ETH_MRRD_RES1 (0xFFFF0000) /* Reserved */
270#define NS7520_ETH_MRRD_MRDD (0x0000FFFF) /* MII Read Data */
271
272/* MIND MII Management Indicators Register Bit Fields*/
273
274#define NS7520_ETH_MIND_RES1 (0xFFFFFFF8) /* Reserved */
275#define NS7520_ETH_MIND_NVALID (0x00000004) /* Read Data not valid */
276#define NS7520_ETH_MIND_SCAN (0x00000002) /* Automatically scan for read data */
277#define NS7520_ETH_MIND_BUSY (0x00000001) /* MII interface busy */
278
279/* SMII Status Register Bit Fields*/
280
281#define NS7520_ETH_SMII_RES1 (0xFFFFFFE0) /* Reserved */
282#define NS7520_ETH_SMII_CLASH (0x00000010) /* MAC-to-MAC with PHY */
283#define NS7520_ETH_SMII_JABBER (0x00000008) /* Jabber condition present */
284#define NS7520_ETH_SMII_LINK (0x00000004) /* Link OK */
285#define NS7520_ETH_SMII_DUPLEX (0x00000002) /* Full-duplex operation */
286#define NS7520_ETH_SMII_SPEED (0x00000001) /* 100 Mbps */
287
288/* SA1 Station Address 1 Register Bit Fields*/
289
290#define NS7520_ETH_SA1_RES1 (0xFFFF0000) /* Reserved */
291#define NS7520_ETH_SA1_OCTET1 (0x0000FF00) /* Station Address octet 1 */
292#define NS7520_ETH_SA1_OCTET2 (0x000000FF) /* Station Address octet 2 */
293
294/* SA2 Station Address 2 Register Bit Fields*/
295
296#define NS7520_ETH_SA2_RES1 (0xFFFF0000) /* Reserved */
297#define NS7520_ETH_SA2_OCTET3 (0x0000FF00) /* Station Address octet 3 */
298#define NS7520_ETH_SA2_OCTET4 (0x000000FF) /* Station Address octet 4 */
299
300/* SA3 Station Address 3 Register Bit Fields*/
301
302#define NS7520_ETH_SA3_RES1 (0xFFFF0000) /* Reserved */
303#define NS7520_ETH_SA3_OCTET5 (0x0000FF00) /* Station Address octet 5 */
304#define NS7520_ETH_SA3_OCTET6 (0x000000FF) /* Station Address octet 6 */
305
306/* SAFR Station Address Filter Register Bit Fields*/
307
308#define NS7520_ETH_SAFR_RES1 (0xFFFFFFF0) /* Reserved */
309#define NS7520_ETH_SAFR_PRO (0x00000008) /* Enable Promiscuous mode */
310#define NS7520_ETH_SAFR_PRM (0x00000004) /* Accept ALL multicast packets */
311#define NS7520_ETH_SAFR_PRA (0x00000002) /* Accept multicast packets table */
312#define NS7520_ETH_SAFR_BROAD (0x00000001) /* Accept ALL Broadcast packets */
313
314/* HT1 Hash Table 1 Register Bit Fields*/
315
316#define NS7520_ETH_HT1_RES1 (0xFFFF0000) /* Reserved */
317#define NS7520_ETH_HT1_HT1 (0x0000FFFF) /* CRC value 15-0 */
318
319/* HT2 Hash Table 2 Register Bit Fields*/
320
321#define NS7520_ETH_HT2_RES1 (0xFFFF0000) /* Reserved */
322#define NS7520_ETH_HT2_HT2 (0x0000FFFF) /* CRC value 31-16 */
323
324/* HT3 Hash Table 3 Register Bit Fields*/
325
326#define NS7520_ETH_HT3_RES1 (0xFFFF0000) /* Reserved */
327#define NS7520_ETH_HT3_HT3 (0x0000FFFF) /* CRC value 47-32 */
328
329/* HT4 Hash Table 4 Register Bit Fields*/
330
331#define NS7520_ETH_HT4_RES1 (0xFFFF0000) /* Reserved */
332#define NS7520_ETH_HT4_HT4 (0x0000FFFF) /* CRC value 63-48 */
333
334#endif /* CONFIG_DRIVER_NS7520_ETHERNET */
335
336#endif /* FS_NS7520_ETH_H */