blob: e527c08b18d910de02f34d01c5082ae4cf802915 [file] [log] [blame]
Guennadi Liakhovetski9b077732008-08-31 00:39:46 +02001/*
2 * (C) Copyright 2007
3 * Byungjae Lee, Samsung Erectronics, bjlee@samsung.com.
4 * - only support for S3C6400
5 *
6 * (C) Copyright 2008
7 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/************************************************
26 * NAME : s3c6400.h
27 *
28 * Based on S3C6400 User's manual Rev 0.0
29 ************************************************/
30
31#ifndef __S3C6400_H__
32#define __S3C6400_H__
33
Guennadi Liakhovetski9b077732008-08-31 00:39:46 +020034#define S3C64XX_UART_CHANNELS 3
35#define S3C64XX_SPI_CHANNELS 2
36
37#include <asm/hardware.h>
38
39#define ELFIN_CLOCK_POWER_BASE 0x7e00f000
40
41/* Clock & Power Controller for mDirac3*/
42#define APLL_LOCK_OFFSET 0x00
43#define MPLL_LOCK_OFFSET 0x04
44#define EPLL_LOCK_OFFSET 0x08
45#define APLL_CON_OFFSET 0x0C
46#define MPLL_CON_OFFSET 0x10
47#define EPLL_CON0_OFFSET 0x14
48#define EPLL_CON1_OFFSET 0x18
49#define CLK_SRC_OFFSET 0x1C
50#define CLK_DIV0_OFFSET 0x20
51#define CLK_DIV1_OFFSET 0x24
52#define CLK_DIV2_OFFSET 0x28
53#define CLK_OUT_OFFSET 0x2C
54#define HCLK_GATE_OFFSET 0x30
55#define PCLK_GATE_OFFSET 0x34
56#define SCLK_GATE_OFFSET 0x38
57#define AHB_CON0_OFFSET 0x100
58#define AHB_CON1_OFFSET 0x104
59#define AHB_CON2_OFFSET 0x108
60#define SELECT_DMA_OFFSET 0x110
61#define SW_RST_OFFSET 0x114
62#define SYS_ID_OFFSET 0x118
63#define MEM_SYS_CFG_OFFSET 0x120
64#define QOS_OVERRIDE0_OFFSET 0x124
65#define QOS_OVERRIDE1_OFFSET 0x128
66#define MEM_CFG_STAT_OFFSET 0x12C
67#define PWR_CFG_OFFSET 0x804
68#define EINT_MASK_OFFSET 0x808
69#define NOR_CFG_OFFSET 0x810
70#define STOP_CFG_OFFSET 0x814
71#define SLEEP_CFG_OFFSET 0x818
72#define OSC_FREQ_OFFSET 0x820
73#define OSC_STABLE_OFFSET 0x824
74#define PWR_STABLE_OFFSET 0x828
75#define FPC_STABLE_OFFSET 0x82C
76#define MTC_STABLE_OFFSET 0x830
77#define OTHERS_OFFSET 0x900
78#define RST_STAT_OFFSET 0x904
79#define WAKEUP_STAT_OFFSET 0x908
80#define BLK_PWR_STAT_OFFSET 0x90C
81#define INF_REG0_OFFSET 0xA00
82#define INF_REG1_OFFSET 0xA04
83#define INF_REG2_OFFSET 0xA08
84#define INF_REG3_OFFSET 0xA0C
85#define INF_REG4_OFFSET 0xA10
86#define INF_REG5_OFFSET 0xA14
87#define INF_REG6_OFFSET 0xA18
88#define INF_REG7_OFFSET 0xA1C
89
90#define OSC_CNT_VAL_OFFSET 0x824
91#define PWR_CNT_VAL_OFFSET 0x828
92#define FPC_CNT_VAL_OFFSET 0x82C
93#define MTC_CNT_VAL_OFFSET 0x830
94
95#define APLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET)
96#define MPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET)
97#define EPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET)
98#define APLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET)
99#define MPLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET)
100#define EPLL_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET)
101#define EPLL_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET)
102#define CLK_SRC_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET)
103#define CLK_DIV0_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET)
104#define CLK_DIV1_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET)
105#define CLK_DIV2_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET)
106#define CLK_OUT_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET)
107#define HCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET)
108#define PCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET)
109#define SCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET)
110#define AHB_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET)
111#define AHB_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET)
112#define AHB_CON2_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET)
113#define SELECT_DMA_REG __REG(ELFIN_CLOCK_POWER_BASE + \
114 SELECT_DMA_OFFSET)
115#define SW_RST_REG __REG(ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET)
116#define SYS_ID_REG __REG(ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET)
117#define MEM_SYS_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + \
118 MEM_SYS_CFG_OFFSET)
119#define QOS_OVERRIDE0_REG __REG(ELFIN_CLOCK_POWER_BASE + \
120 QOS_OVERRIDE0_OFFSET)
121#define QOS_OVERRIDE1_REG __REG(ELFIN_CLOCK_POWER_BASE + \
122 QOS_OVERRIDE1_OFFSET)
123#define MEM_CFG_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \
124 MEM_CFG_STAT_OFFSET)
125#define PWR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET)
126#define EINT_MASK_REG __REG(ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET)
127#define NOR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET)
128#define STOP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET)
129#define SLEEP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET)
130#define OSC_FREQ_REG __REG(ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET)
131#define OSC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
132 OSC_CNT_VAL_OFFSET)
133#define PWR_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
134 PWR_CNT_VAL_OFFSET)
135#define FPC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
136 FPC_CNT_VAL_OFFSET)
137#define MTC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
138 MTC_CNT_VAL_OFFSET)
139#define OTHERS_REG __REG(ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET)
140#define RST_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
141#define WAKEUP_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \
142 WAKEUP_STAT_OFFSET)
143#define BLK_PWR_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \
144 BLK_PWR_STAT_OFFSET)
145#define INF_REG0_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
146#define INF_REG1_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET)
147#define INF_REG2_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET)
148#define INF_REG3_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET)
149#define INF_REG4_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET)
150#define INF_REG5_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET)
151#define INF_REG6_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET)
152#define INF_REG7_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET)
153
154#define APLL_LOCK (ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET)
155#define MPLL_LOCK (ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET)
156#define EPLL_LOCK (ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET)
157#define APLL_CON (ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET)
158#define MPLL_CON (ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET)
159#define EPLL_CON0 (ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET)
160#define EPLL_CON1 (ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET)
161#define CLK_SRC (ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET)
162#define CLK_DIV0 (ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET)
163#define CLK_DIV1 (ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET)
164#define CLK_DIV2 (ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET)
165#define CLK_OUT (ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET)
166#define HCLK_GATE (ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET)
167#define PCLK_GATE (ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET)
168#define SCLK_GATE (ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET)
169#define AHB_CON0 (ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET)
170#define AHB_CON1 (ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET)
171#define AHB_CON2 (ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET)
172#define SELECT_DMA (ELFIN_CLOCK_POWER_BASE + SELECT_DMA_OFFSET)
173#define SW_RST (ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET)
174#define SYS_ID (ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET)
175#define MEM_SYS_CFG (ELFIN_CLOCK_POWER_BASE + MEM_SYS_CFG_OFFSET)
176#define QOS_OVERRIDE0 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE0_OFFSET)
177#define QOS_OVERRIDE1 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE1_OFFSET)
178#define MEM_CFG_STAT (ELFIN_CLOCK_POWER_BASE + MEM_CFG_STAT_OFFSET)
179#define PWR_CFG (ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET)
180#define EINT_MASK (ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET)
181#define NOR_CFG (ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET)
182#define STOP_CFG (ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET)
183#define SLEEP_CFG (ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET)
184#define OSC_FREQ (ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET)
185#define OSC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + OSC_CNT_VAL_OFFSET)
186#define PWR_CNT_VAL (ELFIN_CLOCK_POWER_BASE + PWR_CNT_VAL_OFFSET)
187#define FPC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + FPC_CNT_VAL_OFFSET)
188#define MTC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + MTC_CNT_VAL_OFFSET)
189#define OTHERS (ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET)
190#define RST_STAT (ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
191#define WAKEUP_STAT (ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET)
192#define BLK_PWR_STAT (ELFIN_CLOCK_POWER_BASE + BLK_PWR_STAT_OFFSET)
193#define INF_REG0 (ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
194#define INF_REG1 (ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET)
195#define INF_REG2 (ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET)
196#define INF_REG3 (ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET)
197#define INF_REG4 (ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET)
198#define INF_REG5 (ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET)
199#define INF_REG6 (ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET)
200#define INF_REG7 (ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET)
201
202
203/*
204 * GPIO
205 */
206#define ELFIN_GPIO_BASE 0x7f008000
207
208#define GPACON_OFFSET 0x00
209#define GPADAT_OFFSET 0x04
210#define GPAPUD_OFFSET 0x08
211#define GPACONSLP_OFFSET 0x0C
212#define GPAPUDSLP_OFFSET 0x10
213#define GPBCON_OFFSET 0x20
Minkyu Kang342c1a52009-04-03 09:56:16 +0900214#define GPBDAT_OFFSET 0x24
215#define GPBPUD_OFFSET 0x28
216#define GPBCONSLP_OFFSET 0x2C
Guennadi Liakhovetski9b077732008-08-31 00:39:46 +0200217#define GPBPUDSLP_OFFSET 0x30
218#define GPCCON_OFFSET 0x40
219#define GPCDAT_OFFSET 0x44
220#define GPCPUD_OFFSET 0x48
221#define GPCCONSLP_OFFSET 0x4C
222#define GPCPUDSLP_OFFSET 0x50
223#define GPDCON_OFFSET 0x60
224#define GPDDAT_OFFSET 0x64
225#define GPDPUD_OFFSET 0x68
226#define GPDCONSLP_OFFSET 0x6C
227#define GPDPUDSLP_OFFSET 0x70
228#define GPECON_OFFSET 0x80
229#define GPEDAT_OFFSET 0x84
230#define GPEPUD_OFFSET 0x88
231#define GPECONSLP_OFFSET 0x8C
232#define GPEPUDSLP_OFFSET 0x90
233#define GPFCON_OFFSET 0xA0
234#define GPFDAT_OFFSET 0xA4
235#define GPFPUD_OFFSET 0xA8
236#define GPFCONSLP_OFFSET 0xAC
237#define GPFPUDSLP_OFFSET 0xB0
238#define GPGCON_OFFSET 0xC0
239#define GPGDAT_OFFSET 0xC4
240#define GPGPUD_OFFSET 0xC8
241#define GPGCONSLP_OFFSET 0xCC
242#define GPGPUDSLP_OFFSET 0xD0
243#define GPHCON0_OFFSET 0xE0
244#define GPHCON1_OFFSET 0xE4
245#define GPHDAT_OFFSET 0xE8
246#define GPHPUD_OFFSET 0xEC
247#define GPHCONSLP_OFFSET 0xF0
248#define GPHPUDSLP_OFFSET 0xF4
249#define GPICON_OFFSET 0x100
250#define GPIDAT_OFFSET 0x104
251#define GPIPUD_OFFSET 0x108
252#define GPICONSLP_OFFSET 0x10C
253#define GPIPUDSLP_OFFSET 0x110
254#define GPJCON_OFFSET 0x120
255#define GPJDAT_OFFSET 0x124
256#define GPJPUD_OFFSET 0x128
257#define GPJCONSLP_OFFSET 0x12C
258#define GPJPUDSLP_OFFSET 0x130
259#define MEM0DRVCON_OFFSET 0x1D0
260#define MEM1DRVCON_OFFSET 0x1D4
261#define GPKCON0_OFFSET 0x800
262#define GPKCON1_OFFSET 0x804
263#define GPKDAT_OFFSET 0x808
264#define GPKPUD_OFFSET 0x80C
265#define GPLCON0_OFFSET 0x810
266#define GPLCON1_OFFSET 0x814
267#define GPLDAT_OFFSET 0x818
268#define GPLPUD_OFFSET 0x81C
269#define GPMCON_OFFSET 0x820
270#define GPMDAT_OFFSET 0x824
271#define GPMPUD_OFFSET 0x828
272#define GPNCON_OFFSET 0x830
273#define GPNDAT_OFFSET 0x834
274#define GPNPUD_OFFSET 0x838
275#define GPOCON_OFFSET 0x140
276#define GPODAT_OFFSET 0x144
277#define GPOPUD_OFFSET 0x148
278#define GPOCONSLP_OFFSET 0x14C
279#define GPOPUDSLP_OFFSET 0x150
280#define GPPCON_OFFSET 0x160
281#define GPPDAT_OFFSET 0x164
282#define GPPPUD_OFFSET 0x168
283#define GPPCONSLP_OFFSET 0x16C
284#define GPPPUDSLP_OFFSET 0x170
285#define GPQCON_OFFSET 0x180
286#define GPQDAT_OFFSET 0x184
287#define GPQPUD_OFFSET 0x188
288#define GPQCONSLP_OFFSET 0x18C
289#define GPQPUDSLP_OFFSET 0x190
290
291#define EINTPEND_OFFSET 0x924
292
293#define GPACON_REG __REG(ELFIN_GPIO_BASE + GPACON_OFFSET)
294#define GPADAT_REG __REG(ELFIN_GPIO_BASE + GPADAT_OFFSET)
295#define GPAPUD_REG __REG(ELFIN_GPIO_BASE + GPAPUD_OFFSET)
296#define GPACONSLP_REG __REG(ELFIN_GPIO_BASE + GPACONSLP_OFFSET)
297#define GPAPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET)
298#define GPBCON_REG __REG(ELFIN_GPIO_BASE + GPBCON_OFFSET)
299#define GPBDAT_REG __REG(ELFIN_GPIO_BASE + GPBDAT_OFFSET)
300#define GPBPUD_REG __REG(ELFIN_GPIO_BASE + GPBPUD_OFFSET)
301#define GPBCONSLP_REG __REG(ELFIN_GPIO_BASE + GPBCONSLP_OFFSET)
302#define GPBPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET)
303#define GPCCON_REG __REG(ELFIN_GPIO_BASE + GPCCON_OFFSET)
304#define GPCDAT_REG __REG(ELFIN_GPIO_BASE + GPCDAT_OFFSET)
305#define GPCPUD_REG __REG(ELFIN_GPIO_BASE + GPCPUD_OFFSET)
306#define GPCCONSLP_REG __REG(ELFIN_GPIO_BASE + GPCCONSLP_OFFSET)
307#define GPCPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET)
308#define GPDCON_REG __REG(ELFIN_GPIO_BASE + GPDCON_OFFSET)
309#define GPDDAT_REG __REG(ELFIN_GPIO_BASE + GPDDAT_OFFSET)
310#define GPDPUD_REG __REG(ELFIN_GPIO_BASE + GPDPUD_OFFSET)
311#define GPDCONSLP_REG __REG(ELFIN_GPIO_BASE + GPDCONSLP_OFFSET)
312#define GPDPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET)
313#define GPECON_REG __REG(ELFIN_GPIO_BASE + GPECON_OFFSET)
314#define GPEDAT_REG __REG(ELFIN_GPIO_BASE + GPEDAT_OFFSET)
315#define GPEPUD_REG __REG(ELFIN_GPIO_BASE + GPEPUD_OFFSET)
316#define GPECONSLP_REG __REG(ELFIN_GPIO_BASE + GPECONSLP_OFFSET)
317#define GPEPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET)
318#define GPFCON_REG __REG(ELFIN_GPIO_BASE + GPFCON_OFFSET)
319#define GPFDAT_REG __REG(ELFIN_GPIO_BASE + GPFDAT_OFFSET)
320#define GPFPUD_REG __REG(ELFIN_GPIO_BASE + GPFPUD_OFFSET)
321#define GPFCONSLP_REG __REG(ELFIN_GPIO_BASE + GPFCONSLP_OFFSET)
322#define GPFPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET)
323#define GPGCON_REG __REG(ELFIN_GPIO_BASE + GPGCON_OFFSET)
324#define GPGDAT_REG __REG(ELFIN_GPIO_BASE + GPGDAT_OFFSET)
325#define GPGPUD_REG __REG(ELFIN_GPIO_BASE + GPGPUD_OFFSET)
326#define GPGCONSLP_REG __REG(ELFIN_GPIO_BASE + GPGCONSLP_OFFSET)
327#define GPGPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET)
328#define GPHCON0_REG __REG(ELFIN_GPIO_BASE + GPHCON0_OFFSET)
329#define GPHCON1_REG __REG(ELFIN_GPIO_BASE + GPHCON1_OFFSET)
330#define GPHDAT_REG __REG(ELFIN_GPIO_BASE + GPHDAT_OFFSET)
331#define GPHPUD_REG __REG(ELFIN_GPIO_BASE + GPHPUD_OFFSET)
332#define GPHCONSLP_REG __REG(ELFIN_GPIO_BASE + GPHCONSLP_OFFSET)
333#define GPHPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET)
334#define GPICON_REG __REG(ELFIN_GPIO_BASE + GPICON_OFFSET)
335#define GPIDAT_REG __REG(ELFIN_GPIO_BASE + GPIDAT_OFFSET)
336#define GPIPUD_REG __REG(ELFIN_GPIO_BASE + GPIPUD_OFFSET)
337#define GPICONSLP_REG __REG(ELFIN_GPIO_BASE + GPICONSLP_OFFSET)
338#define GPIPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET)
339#define GPJCON_REG __REG(ELFIN_GPIO_BASE + GPJCON_OFFSET)
340#define GPJDAT_REG __REG(ELFIN_GPIO_BASE + GPJDAT_OFFSET)
341#define GPJPUD_REG __REG(ELFIN_GPIO_BASE + GPJPUD_OFFSET)
342#define GPJCONSLP_REG __REG(ELFIN_GPIO_BASE + GPJCONSLP_OFFSET)
343#define GPJPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET)
344#define GPKCON0_REG __REG(ELFIN_GPIO_BASE + GPKCON0_OFFSET)
345#define GPKCON1_REG __REG(ELFIN_GPIO_BASE + GPKCON1_OFFSET)
346#define GPKDAT_REG __REG(ELFIN_GPIO_BASE + GPKDAT_OFFSET)
347#define GPKPUD_REG __REG(ELFIN_GPIO_BASE + GPKPUD_OFFSET)
348#define GPLCON0_REG __REG(ELFIN_GPIO_BASE + GPLCON0_OFFSET)
349#define GPLCON1_REG __REG(ELFIN_GPIO_BASE + GPLCON1_OFFSET)
350#define GPLDAT_REG __REG(ELFIN_GPIO_BASE + GPLDAT_OFFSET)
351#define GPLPUD_REG __REG(ELFIN_GPIO_BASE + GPLPUD_OFFSET)
352#define GPMCON_REG __REG(ELFIN_GPIO_BASE + GPMCON_OFFSET)
353#define GPMDAT_REG __REG(ELFIN_GPIO_BASE + GPMDAT_OFFSET)
354#define GPMPUD_REG __REG(ELFIN_GPIO_BASE + GPMPUD_OFFSET)
355#define GPNCON_REG __REG(ELFIN_GPIO_BASE + GPNCON_OFFSET)
356#define GPNDAT_REG __REG(ELFIN_GPIO_BASE + GPNDAT_OFFSET)
357#define GPNPUD_REG __REG(ELFIN_GPIO_BASE + GPNPUD_OFFSET)
358#define GPOCON_REG __REG(ELFIN_GPIO_BASE + GPOCON_OFFSET)
359#define GPODAT_REG __REG(ELFIN_GPIO_BASE + GPODAT_OFFSET)
360#define GPOPUD_REG __REG(ELFIN_GPIO_BASE + GPOPUD_OFFSET)
361#define GPOCONSLP_REG __REG(ELFIN_GPIO_BASE + GPOCONSLP_OFFSET)
362#define GPOPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET)
363#define GPPCON_REG __REG(ELFIN_GPIO_BASE + GPPCON_OFFSET)
364#define GPPDAT_REG __REG(ELFIN_GPIO_BASE + GPPDAT_OFFSET)
365#define GPPPUD_REG __REG(ELFIN_GPIO_BASE + GPPPUD_OFFSET)
366#define GPPCONSLP_REG __REG(ELFIN_GPIO_BASE + GPPCONSLP_OFFSET)
367#define GPPPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET)
368#define GPQCON_REG __REG(ELFIN_GPIO_BASE + GPQCON_OFFSET)
369#define GPQDAT_REG __REG(ELFIN_GPIO_BASE + GPQDAT_OFFSET)
370#define GPQPUD_REG __REG(ELFIN_GPIO_BASE + GPQPUD_OFFSET)
371#define GPQCONSLP_REG __REG(ELFIN_GPIO_BASE + GPQCONSLP_OFFSET)
372#define GPQPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET)
373
374/*
375 * Bus Matrix
376 */
377#define ELFIN_MEM_SYS_CFG 0x7e00f120
378
Kyungmin Parkab0689c2008-11-26 10:18:13 +0900379#define S3C64XX_MEM_SYS_CFG_16BIT (1 << 12)
380
381#define S3C64XX_MEM_SYS_CFG_NAND 0x0008
382#define S3C64XX_MEM_SYS_CFG_ONENAND S3C64XX_MEM_SYS_CFG_16BIT
383
Guennadi Liakhovetski9b077732008-08-31 00:39:46 +0200384#define GPACON (ELFIN_GPIO_BASE + GPACON_OFFSET)
385#define GPADAT (ELFIN_GPIO_BASE + GPADAT_OFFSET)
386#define GPAPUD (ELFIN_GPIO_BASE + GPAPUD_OFFSET)
387#define GPACONSLP (ELFIN_GPIO_BASE + GPACONSLP_OFFSET)
388#define GPAPUDSLP (ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET)
389#define GPBCON (ELFIN_GPIO_BASE + GPBCON_OFFSET)
390#define GPBDAT (ELFIN_GPIO_BASE + GPBDAT_OFFSET)
391#define GPBPUD (ELFIN_GPIO_BASE + GPBPUD_OFFSET)
392#define GPBCONSLP (ELFIN_GPIO_BASE + GPBCONSLP_OFFSET)
393#define GPBPUDSLP (ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET)
394#define GPCCON (ELFIN_GPIO_BASE + GPCCON_OFFSET)
395#define GPCDAT (ELFIN_GPIO_BASE + GPCDAT_OFFSET)
396#define GPCPUD (ELFIN_GPIO_BASE + GPCPUD_OFFSET)
397#define GPCCONSLP (ELFIN_GPIO_BASE + GPCCONSLP_OFFSET)
398#define GPCPUDSLP (ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET)
399#define GPDCON (ELFIN_GPIO_BASE + GPDCON_OFFSET)
400#define GPDDAT (ELFIN_GPIO_BASE + GPDDAT_OFFSET)
401#define GPDPUD (ELFIN_GPIO_BASE + GPDPUD_OFFSET)
402#define GPDCONSLP (ELFIN_GPIO_BASE + GPDCONSLP_OFFSET)
403#define GPDPUDSLP (ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET)
404#define GPECON (ELFIN_GPIO_BASE + GPECON_OFFSET)
405#define GPEDAT (ELFIN_GPIO_BASE + GPEDAT_OFFSET)
406#define GPEPUD (ELFIN_GPIO_BASE + GPEPUD_OFFSET)
407#define GPECONSLP (ELFIN_GPIO_BASE + GPECONSLP_OFFSET)
408#define GPEPUDSLP (ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET)
409#define GPFCON (ELFIN_GPIO_BASE + GPFCON_OFFSET)
410#define GPFDAT (ELFIN_GPIO_BASE + GPFDAT_OFFSET)
411#define GPFPUD (ELFIN_GPIO_BASE + GPFPUD_OFFSET)
412#define GPFCONSLP (ELFIN_GPIO_BASE + GPFCONSLP_OFFSET)
413#define GPFPUDSLP (ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET)
414#define GPGCON (ELFIN_GPIO_BASE + GPGCON_OFFSET)
415#define GPGDAT (ELFIN_GPIO_BASE + GPGDAT_OFFSET)
416#define GPGPUD (ELFIN_GPIO_BASE + GPGPUD_OFFSET)
417#define GPGCONSLP (ELFIN_GPIO_BASE + GPGCONSLP_OFFSET)
418#define GPGPUDSLP (ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET)
419#define GPHCON0 (ELFIN_GPIO_BASE + GPHCON0_OFFSET)
420#define GPHCON1 (ELFIN_GPIO_BASE + GPHCON1_OFFSET)
421#define GPHDAT (ELFIN_GPIO_BASE + GPHDAT_OFFSET)
422#define GPHPUD (ELFIN_GPIO_BASE + GPHPUD_OFFSET)
423#define GPHCONSLP (ELFIN_GPIO_BASE + GPHCONSLP_OFFSET)
424#define GPHPUDSLP (ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET)
425#define GPICON (ELFIN_GPIO_BASE + GPICON_OFFSET)
426#define GPIDAT (ELFIN_GPIO_BASE + GPIDAT_OFFSET)
427#define GPIPUD (ELFIN_GPIO_BASE + GPIPUD_OFFSET)
428#define GPICONSLP (ELFIN_GPIO_BASE + GPICONSLP_OFFSET)
429#define GPIPUDSLP (ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET)
430#define GPJCON (ELFIN_GPIO_BASE + GPJCON_OFFSET)
431#define GPJDAT (ELFIN_GPIO_BASE + GPJDAT_OFFSET)
432#define GPJPUD (ELFIN_GPIO_BASE + GPJPUD_OFFSET)
433#define GPJCONSLP (ELFIN_GPIO_BASE + GPJCONSLP_OFFSET)
434#define GPJPUDSLP (ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET)
435#define GPKCON0 (ELFIN_GPIO_BASE + GPKCON0_OFFSET)
436#define GPKCON1 (ELFIN_GPIO_BASE + GPKCON1_OFFSET)
437#define GPKDAT (ELFIN_GPIO_BASE + GPKDAT_OFFSET)
438#define GPKPUD (ELFIN_GPIO_BASE + GPKPUD_OFFSET)
439#define GPLCON0 (ELFIN_GPIO_BASE + GPLCON0_OFFSET)
440#define GPLCON1 (ELFIN_GPIO_BASE + GPLCON1_OFFSET)
441#define GPLDAT (ELFIN_GPIO_BASE + GPLDAT_OFFSET)
442#define GPLPUD (ELFIN_GPIO_BASE + GPLPUD_OFFSET)
443#define GPMCON (ELFIN_GPIO_BASE + GPMCON_OFFSET)
444#define GPMDAT (ELFIN_GPIO_BASE + GPMDAT_OFFSET)
445#define GPMPUD (ELFIN_GPIO_BASE + GPMPUD_OFFSET)
446#define GPNCON (ELFIN_GPIO_BASE + GPNCON_OFFSET)
447#define GPNDAT (ELFIN_GPIO_BASE + GPNDAT_OFFSET)
448#define GPNPUD (ELFIN_GPIO_BASE + GPNPUD_OFFSET)
449#define GPOCON (ELFIN_GPIO_BASE + GPOCON_OFFSET)
450#define GPODAT (ELFIN_GPIO_BASE + GPODAT_OFFSET)
451#define GPOPUD (ELFIN_GPIO_BASE + GPOPUD_OFFSET)
452#define GPOCONSLP (ELFIN_GPIO_BASE + GPOCONSLP_OFFSET)
453#define GPOPUDSLP (ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET)
454#define GPPCON (ELFIN_GPIO_BASE + GPPCON_OFFSET)
455#define GPPDAT (ELFIN_GPIO_BASE + GPPDAT_OFFSET)
456#define GPPPUD (ELFIN_GPIO_BASE + GPPPUD_OFFSET)
457#define GPPCONSLP (ELFIN_GPIO_BASE + GPPCONSLP_OFFSET)
458#define GPPPUDSLP (ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET)
459#define GPQCON (ELFIN_GPIO_BASE + GPQCON_OFFSET)
460#define GPQDAT (ELFIN_GPIO_BASE + GPQDAT_OFFSET)
461#define GPQPUD (ELFIN_GPIO_BASE + GPQPUD_OFFSET)
462#define GPQCONSLP (ELFIN_GPIO_BASE + GPQCONSLP_OFFSET)
463#define GPQPUDSLP (ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET)
464
465/*
466 * Memory controller
467 */
468#define ELFIN_SROM_BASE 0x70000000
469
470#define SROM_BW_REG __REG(ELFIN_SROM_BASE + 0x0)
471#define SROM_BC0_REG __REG(ELFIN_SROM_BASE + 0x4)
472#define SROM_BC1_REG __REG(ELFIN_SROM_BASE + 0x8)
473#define SROM_BC2_REG __REG(ELFIN_SROM_BASE + 0xC)
474#define SROM_BC3_REG __REG(ELFIN_SROM_BASE + 0x10)
475#define SROM_BC4_REG __REG(ELFIN_SROM_BASE + 0x14)
476#define SROM_BC5_REG __REG(ELFIN_SROM_BASE + 0x18)
477
478/*
479 * SDRAM Controller
480 */
481#define ELFIN_DMC0_BASE 0x7e000000
482#define ELFIN_DMC1_BASE 0x7e001000
483
484#define INDEX_DMC_MEMC_STATUS 0x00
485#define INDEX_DMC_MEMC_CMD 0x04
486#define INDEX_DMC_DIRECT_CMD 0x08
487#define INDEX_DMC_MEMORY_CFG 0x0C
488#define INDEX_DMC_REFRESH_PRD 0x10
489#define INDEX_DMC_CAS_LATENCY 0x14
490#define INDEX_DMC_T_DQSS 0x18
491#define INDEX_DMC_T_MRD 0x1C
492#define INDEX_DMC_T_RAS 0x20
493#define INDEX_DMC_T_RC 0x24
494#define INDEX_DMC_T_RCD 0x28
495#define INDEX_DMC_T_RFC 0x2C
496#define INDEX_DMC_T_RP 0x30
497#define INDEX_DMC_T_RRD 0x34
498#define INDEX_DMC_T_WR 0x38
499#define INDEX_DMC_T_WTR 0x3C
500#define INDEX_DMC_T_XP 0x40
501#define INDEX_DMC_T_XSR 0x44
502#define INDEX_DMC_T_ESR 0x48
503#define INDEX_DMC_MEMORY_CFG2 0x4C
504#define INDEX_DMC_CHIP_0_CFG 0x200
505#define INDEX_DMC_CHIP_1_CFG 0x204
506#define INDEX_DMC_CHIP_2_CFG 0x208
507#define INDEX_DMC_CHIP_3_CFG 0x20C
508#define INDEX_DMC_USER_STATUS 0x300
509#define INDEX_DMC_USER_CONFIG 0x304
510
511/*
512 * Memory Chip direct command
513 */
514#define DMC_NOP0 0x0c0000
515#define DMC_NOP1 0x1c0000
516#define DMC_PA0 0x000000 /* Precharge all */
517#define DMC_PA1 0x100000
518#define DMC_AR0 0x040000 /* Autorefresh */
519#define DMC_AR1 0x140000
520#define DMC_SDR_MR0 0x080032 /* MRS, CAS 3, Burst Length 4 */
521#define DMC_SDR_MR1 0x180032
522#define DMC_DDR_MR0 0x080162
523#define DMC_DDR_MR1 0x180162
524#define DMC_mDDR_MR0 0x080032 /* CAS 3, Burst Length 4 */
525#define DMC_mDDR_MR1 0x180032
526#define DMC_mSDR_EMR0 0x0a0000 /* EMRS, DS:Full, PASR:Full Array */
527#define DMC_mSDR_EMR1 0x1a0000
528#define DMC_DDR_EMR0 0x090000
529#define DMC_DDR_EMR1 0x190000
530#define DMC_mDDR_EMR0 0x0a0000 /* DS:Full, PASR:Full Array */
531#define DMC_mDDR_EMR1 0x1a0000
532
533/*
534 * Definitions for memory configuration
535 * Set memory configuration
536 * active_chips = 1'b0 (1 chip)
537 * qos_master_chip = 3'b000(ARID[3:0])
538 * memory burst = 3'b010(burst 4)
539 * stop_mem_clock = 1'b0(disable dynamical stop)
540 * auto_power_down = 1'b0(disable auto power-down mode)
541 * power_down_prd = 6'b00_0000(0 cycle for auto power-down)
542 * ap_bit = 1'b0 (bit position of auto-precharge is 10)
543 * row_bits = 3'b010(# row address 13)
544 * column_bits = 3'b010(# column address 10 )
545 *
546 * Set user configuration
547 * 2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR
548 *
549 * Set chip select for chip [n]
550 * row bank control, bank address 0x3000_0000 ~ 0x37ff_ffff
551 * CHIP_[n]_CFG=0x30F8, 30: ADDR[31:24], F8: Mask[31:24]
552 */
553
554/*
555 * Nand flash controller
556 */
557#define ELFIN_NAND_BASE 0x70200000
558
559#define NFCONF_OFFSET 0x00
560#define NFCONT_OFFSET 0x04
561#define NFCMMD_OFFSET 0x08
562#define NFADDR_OFFSET 0x0c
563#define NFDATA_OFFSET 0x10
564#define NFMECCDATA0_OFFSET 0x14
565#define NFMECCDATA1_OFFSET 0x18
566#define NFSECCDATA0_OFFSET 0x1c
567#define NFSBLK_OFFSET 0x20
568#define NFEBLK_OFFSET 0x24
569#define NFSTAT_OFFSET 0x28
570#define NFESTAT0_OFFSET 0x2c
571#define NFESTAT1_OFFSET 0x30
572#define NFMECC0_OFFSET 0x34
573#define NFMECC1_OFFSET 0x38
574#define NFSECC_OFFSET 0x3c
575#define NFMLCBITPT_OFFSET 0x40
576
577#define NFCONF (ELFIN_NAND_BASE + NFCONF_OFFSET)
578#define NFCONT (ELFIN_NAND_BASE + NFCONT_OFFSET)
579#define NFCMMD (ELFIN_NAND_BASE + NFCMMD_OFFSET)
580#define NFADDR (ELFIN_NAND_BASE + NFADDR_OFFSET)
581#define NFDATA (ELFIN_NAND_BASE + NFDATA_OFFSET)
582#define NFMECCDATA0 (ELFIN_NAND_BASE + NFMECCDATA0_OFFSET)
583#define NFMECCDATA1 (ELFIN_NAND_BASE + NFMECCDATA1_OFFSET)
584#define NFSECCDATA0 (ELFIN_NAND_BASE + NFSECCDATA0_OFFSET)
585#define NFSBLK (ELFIN_NAND_BASE + NFSBLK_OFFSET)
586#define NFEBLK (ELFIN_NAND_BASE + NFEBLK_OFFSET)
587#define NFSTAT (ELFIN_NAND_BASE + NFSTAT_OFFSET)
588#define NFESTAT0 (ELFIN_NAND_BASE + NFESTAT0_OFFSET)
589#define NFESTAT1 (ELFIN_NAND_BASE + NFESTAT1_OFFSET)
590#define NFMECC0 (ELFIN_NAND_BASE + NFMECC0_OFFSET)
591#define NFMECC1 (ELFIN_NAND_BASE + NFMECC1_OFFSET)
592#define NFSECC (ELFIN_NAND_BASE + NFSECC_OFFSET)
593#define NFMLCBITPT (ELFIN_NAND_BASE + NFMLCBITPT_OFFSET)
594
595#define NFCONF_REG __REG(ELFIN_NAND_BASE + NFCONF_OFFSET)
596#define NFCONT_REG __REG(ELFIN_NAND_BASE + NFCONT_OFFSET)
597#define NFCMD_REG __REG(ELFIN_NAND_BASE + NFCMMD_OFFSET)
598#define NFADDR_REG __REG(ELFIN_NAND_BASE + NFADDR_OFFSET)
599#define NFDATA_REG __REG(ELFIN_NAND_BASE + NFDATA_OFFSET)
600#define NFDATA8_REG __REGb(ELFIN_NAND_BASE + NFDATA_OFFSET)
601#define NFMECCDATA0_REG __REG(ELFIN_NAND_BASE + NFMECCDATA0_OFFSET)
602#define NFMECCDATA1_REG __REG(ELFIN_NAND_BASE + NFMECCDATA1_OFFSET)
603#define NFSECCDATA0_REG __REG(ELFIN_NAND_BASE + NFSECCDATA0_OFFSET)
604#define NFSBLK_REG __REG(ELFIN_NAND_BASE + NFSBLK_OFFSET)
605#define NFEBLK_REG __REG(ELFIN_NAND_BASE + NFEBLK_OFFSET)
606#define NFSTAT_REG __REG(ELFIN_NAND_BASE + NFSTAT_OFFSET)
607#define NFESTAT0_REG __REG(ELFIN_NAND_BASE + NFESTAT0_OFFSET)
608#define NFESTAT1_REG __REG(ELFIN_NAND_BASE + NFESTAT1_OFFSET)
609#define NFMECC0_REG __REG(ELFIN_NAND_BASE + NFMECC0_OFFSET)
610#define NFMECC1_REG __REG(ELFIN_NAND_BASE + NFMECC1_OFFSET)
611#define NFSECC_REG __REG(ELFIN_NAND_BASE + NFSECC_OFFSET)
612#define NFMLCBITPT_REG __REG(ELFIN_NAND_BASE + NFMLCBITPT_OFFSET)
613
614#define NFCONF_ECC_4BIT (1<<24)
615
616#define NFCONT_ECC_ENC (1<<18)
617#define NFCONT_WP (1<<16)
618#define NFCONT_MECCLOCK (1<<7)
619#define NFCONT_SECCLOCK (1<<6)
620#define NFCONT_INITMECC (1<<5)
621#define NFCONT_INITSECC (1<<4)
622#define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC)
623#define NFCONT_CS_ALT (1<<2)
624#define NFCONT_CS (1<<1)
625#define NFCONT_ENABLE (1<<0)
626
627#define NFSTAT_ECCENCDONE (1<<7)
628#define NFSTAT_ECCDECDONE (1<<6)
629#define NFSTAT_RnB (1<<0)
630
631#define NFESTAT0_ECCBUSY (1<<31)
632
633/*
634 * Interrupt
635 */
636#define ELFIN_VIC0_BASE_ADDR 0x71200000
637#define ELFIN_VIC1_BASE_ADDR 0x71300000
638#define oINTMOD 0x0C /* VIC INT SELECT (IRQ or FIQ) */
639#define oINTUNMSK 0x10 /* VIC INT EN (write 1 to unmask) */
640#define oINTMSK 0x14 /* VIC INT EN CLEAR (write 1 to mask) */
641#define oINTSUBMSK 0x1C /* VIC SOFT INT CLEAR */
642#define oVECTADDR 0xF00 /* VIC ADDRESS */
643
644/*
645 * Watchdog timer
646 */
647#define ELFIN_WATCHDOG_BASE 0x7E004000
648
649#define WTCON_REG __REG(0x7E004004)
650#define WTDAT_REG __REG(0x7E004008)
651#define WTCNT_REG __REG(0x7E00400C)
652
653
654/*
655 * UART
656 */
657#define ELFIN_UART_BASE 0x7F005000
658
659#define ELFIN_UART0_OFFSET 0x0000
660#define ELFIN_UART1_OFFSET 0x0400
661#define ELFIN_UART2_OFFSET 0x0800
662
663#define ULCON_OFFSET 0x00
664#define UCON_OFFSET 0x04
665#define UFCON_OFFSET 0x08
666#define UMCON_OFFSET 0x0C
667#define UTRSTAT_OFFSET 0x10
668#define UERSTAT_OFFSET 0x14
669#define UFSTAT_OFFSET 0x18
670#define UMSTAT_OFFSET 0x1C
671#define UTXH_OFFSET 0x20
672#define URXH_OFFSET 0x24
673#define UBRDIV_OFFSET 0x28
674#define UDIVSLOT_OFFSET 0x2C
675#define UINTP_OFFSET 0x30
676#define UINTSP_OFFSET 0x34
677#define UINTM_OFFSET 0x38
678
679#define ULCON0_REG __REG(0x7F005000)
680#define UCON0_REG __REG(0x7F005004)
681#define UFCON0_REG __REG(0x7F005008)
682#define UMCON0_REG __REG(0x7F00500C)
683#define UTRSTAT0_REG __REG(0x7F005010)
684#define UERSTAT0_REG __REG(0x7F005014)
685#define UFSTAT0_REG __REG(0x7F005018)
686#define UMSTAT0_REG __REG(0x7F00501c)
687#define UTXH0_REG __REG(0x7F005020)
688#define URXH0_REG __REG(0x7F005024)
689#define UBRDIV0_REG __REG(0x7F005028)
690#define UDIVSLOT0_REG __REG(0x7F00502c)
691#define UINTP0_REG __REG(0x7F005030)
692#define UINTSP0_REG __REG(0x7F005034)
693#define UINTM0_REG __REG(0x7F005038)
694
695#define ULCON1_REG __REG(0x7F005400)
696#define UCON1_REG __REG(0x7F005404)
697#define UFCON1_REG __REG(0x7F005408)
698#define UMCON1_REG __REG(0x7F00540C)
699#define UTRSTAT1_REG __REG(0x7F005410)
700#define UERSTAT1_REG __REG(0x7F005414)
701#define UFSTAT1_REG __REG(0x7F005418)
702#define UMSTAT1_REG __REG(0x7F00541c)
703#define UTXH1_REG __REG(0x7F005420)
704#define URXH1_REG __REG(0x7F005424)
705#define UBRDIV1_REG __REG(0x7F005428)
706#define UDIVSLOT1_REG __REG(0x7F00542c)
707#define UINTP1_REG __REG(0x7F005430)
708#define UINTSP1_REG __REG(0x7F005434)
709#define UINTM1_REG __REG(0x7F005438)
710
711#define UTRSTAT_TX_EMPTY (1 << 2)
712#define UTRSTAT_RX_READY (1 << 0)
713#define UART_ERR_MASK 0xF
714
715/*
716 * PWM timer
717 */
718#define ELFIN_TIMER_BASE 0x7F006000
719
720#define TCFG0_REG __REG(0x7F006000)
721#define TCFG1_REG __REG(0x7F006004)
722#define TCON_REG __REG(0x7F006008)
723#define TCNTB0_REG __REG(0x7F00600c)
724#define TCMPB0_REG __REG(0x7F006010)
725#define TCNTO0_REG __REG(0x7F006014)
726#define TCNTB1_REG __REG(0x7F006018)
727#define TCMPB1_REG __REG(0x7F00601c)
728#define TCNTO1_REG __REG(0x7F006020)
729#define TCNTB2_REG __REG(0x7F006024)
730#define TCMPB2_REG __REG(0x7F006028)
731#define TCNTO2_REG __REG(0x7F00602c)
732#define TCNTB3_REG __REG(0x7F006030)
733#define TCMPB3_REG __REG(0x7F006034)
734#define TCNTO3_REG __REG(0x7F006038)
735#define TCNTB4_REG __REG(0x7F00603c)
736#define TCNTO4_REG __REG(0x7F006040)
737
738/* Fields */
739#define fTCFG0_DZONE Fld(8, 16) /* the dead zone length (=timer 0) */
740#define fTCFG0_PRE1 Fld(8, 8) /* prescaler value for time 2,3,4 */
741#define fTCFG0_PRE0 Fld(8, 0) /* prescaler value for time 0,1 */
742#define fTCFG1_MUX4 Fld(4, 16)
743/* bits */
744#define TCFG0_DZONE(x) FInsrt((x), fTCFG0_DZONE)
745#define TCFG0_PRE1(x) FInsrt((x), fTCFG0_PRE1)
746#define TCFG0_PRE0(x) FInsrt((x), fTCFG0_PRE0)
747#define TCON_4_AUTO (1 << 22) /* auto reload on/off for Timer 4 */
748#define TCON_4_UPDATE (1 << 21) /* manual Update TCNTB4 */
749#define TCON_4_ONOFF (1 << 20) /* 0: Stop, 1: start Timer 4 */
750#define COUNT_4_ON (TCON_4_ONOFF * 1)
751#define COUNT_4_OFF (TCON_4_ONOFF * 0)
752#define TCON_3_AUTO (1 << 19) /* auto reload on/off for Timer 3 */
753#define TIMER3_ATLOAD_ON (TCON_3_AUTO * 1)
754#define TIMER3_ATLAOD_OFF FClrBit(TCON, TCON_3_AUTO)
755#define TCON_3_INVERT (1 << 18) /* 1: Inverter on for TOUT3 */
756#define TIMER3_IVT_ON (TCON_3_INVERT * 1)
757#define TIMER3_IVT_OFF (FClrBit(TCON, TCON_3_INVERT))
758#define TCON_3_MAN (1 << 17) /* manual Update TCNTB3,TCMPB3 */
759#define TIMER3_MANUP (TCON_3_MAN*1)
760#define TIMER3_NOP (FClrBit(TCON, TCON_3_MAN))
761#define TCON_3_ONOFF (1 << 16) /* 0: Stop, 1: start Timer 3 */
762#define TIMER3_ON (TCON_3_ONOFF * 1)
763#define TIMER3_OFF (FClrBit(TCON, TCON_3_ONOFF))
764
765#if defined(CONFIG_CLK_400_100_50)
766#define STARTUP_AMDIV 400
767#define STARTUP_MDIV 400
768#define STARTUP_PDIV 6
769#define STARTUP_SDIV 1
770#elif defined(CONFIG_CLK_400_133_66)
771#define STARTUP_AMDIV 400
772#define STARTUP_MDIV 533
773#define STARTUP_PDIV 6
774#define STARTUP_SDIV 1
775#elif defined(CONFIG_CLK_533_133_66)
776#define STARTUP_AMDIV 533
777#define STARTUP_MDIV 533
778#define STARTUP_PDIV 6
779#define STARTUP_SDIV 1
780#elif defined(CONFIG_CLK_667_133_66)
781#define STARTUP_AMDIV 667
782#define STARTUP_MDIV 533
783#define STARTUP_PDIV 6
784#define STARTUP_SDIV 1
785#endif
786
787#define STARTUP_PCLKDIV 3
788#define STARTUP_HCLKX2DIV 1
789#define STARTUP_HCLKDIV 1
790#define STARTUP_MPLLDIV 1
791#define STARTUP_APLLDIV 0
792
793#define CLK_DIV_VAL ((STARTUP_PCLKDIV << 12) | (STARTUP_HCLKX2DIV << 9) | \
794 (STARTUP_HCLKDIV << 8) | (STARTUP_MPLLDIV<<4) | STARTUP_APLLDIV)
795#define MPLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \
796 (STARTUP_PDIV << 8) | STARTUP_SDIV)
797#define STARTUP_MPLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
798 STARTUP_PDIV) * STARTUP_MDIV)
799
800#if defined(CONFIG_SYNC_MODE)
801#define APLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \
802 (STARTUP_PDIV << 8) | STARTUP_SDIV)
803#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
804 STARTUP_PDIV) * STARTUP_MDIV)
805#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \
806 (STARTUP_HCLKDIV + 1))
807#else
808#define APLL_VAL ((1 << 31) | (STARTUP_AMDIV << 16) | \
809 (STARTUP_PDIV << 8) | STARTUP_SDIV)
810#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
811 STARTUP_PDIV) * STARTUP_AMDIV)
812#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \
813 (STARTUP_HCLKDIV + 1))
814#endif
815
816
817/*-----------------------------------------------------------------------
818 * Physical Memory Map
819 */
820#define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */
821#define DMC1_MEM_CFG2 0xB45
822#define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */
823#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
824
825/* Memory Parameters */
826/* DDR Parameters */
827#define DDR_tREFRESH 7800 /* ns */
828#define DDR_tRAS 45 /* ns (min: 45ns)*/
829#define DDR_tRC 68 /* ns (min: 67.5ns)*/
830#define DDR_tRCD 23 /* ns (min: 22.5ns)*/
831#define DDR_tRFC 80 /* ns (min: 80ns)*/
832#define DDR_tRP 23 /* ns (min: 22.5ns)*/
833#define DDR_tRRD 15 /* ns (min: 15ns)*/
834#define DDR_tWR 15 /* ns (min: 15ns)*/
835#define DDR_tXSR 120 /* ns (min: 120ns)*/
836#define DDR_CASL 3 /* CAS Latency 3 */
837
838/*
839 * mDDR memory configuration
840 */
841
842#define NS_TO_CLK(t) ((STARTUP_HCLK / 1000 * (t) - 1) / 1000000)
843
844#define DMC_DDR_BA_EMRS 2
845#define DMC_DDR_MEM_CASLAT 3
846/* 6 Set Cas Latency to 3 */
847#define DMC_DDR_CAS_LATENCY (DDR_CASL << 1)
848/* Min 0.75 ~ 1.25 */
849#define DMC_DDR_t_DQSS 1
850/* Min 2 tck */
851#define DMC_DDR_t_MRD 2
852/* 7, Min 45ns */
853#define DMC_DDR_t_RAS (NS_TO_CLK(DDR_tRAS) + 1)
854/* 10, Min 67.5ns */
855#define DMC_DDR_t_RC (NS_TO_CLK(DDR_tRC) + 1)
856/* 4,5(TRM), Min 22.5ns */
857#define DMC_DDR_t_RCD (NS_TO_CLK(DDR_tRCD) + 1)
858#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3)
859/* 11,18(TRM) Min 80ns */
860#define DMC_DDR_t_RFC (NS_TO_CLK(DDR_tRFC) + 1)
861#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5)
862/* 4, 5(TRM) Min 22.5ns */
863#define DMC_DDR_t_RP (NS_TO_CLK(DDR_tRP) + 1)
864#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3)
865/* 3, Min 15ns */
866#define DMC_DDR_t_RRD (NS_TO_CLK(DDR_tRRD) + 1)
867/* Min 15ns */
868#define DMC_DDR_t_WR (NS_TO_CLK(DDR_tWR) + 1)
869#define DMC_DDR_t_WTR 2
870/* 1tck + tIS(1.5ns) */
871#define DMC_DDR_t_XP 2
872/* 17, Min 120ns */
873#define DMC_DDR_t_XSR (NS_TO_CLK(DDR_tXSR) + 1)
874#define DMC_DDR_t_ESR DMC_DDR_t_XSR
875/* TRM 2656 */
876#define DMC_DDR_REFRESH_PRD (NS_TO_CLK(DDR_tREFRESH))
877/* 2b01 : mDDR */
878#define DMC_DDR_USER_CONFIG 1
879
880#ifndef __ASSEMBLY__
881enum s3c64xx_uarts_nr {
882 S3C64XX_UART0,
883 S3C64XX_UART1,
884 S3C64XX_UART2,
885};
886
887#include "s3c64x0.h"
888
889static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr)
890{
891 return (s3c64xx_uart *)(ELFIN_UART_BASE + (nr * 0x400));
892}
893#endif
894
895#endif /*__S3C6400_H__*/