blob: 8dd092fc599a2aef91592df5cf82a20aba980be4 [file] [log] [blame]
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +09001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2016-2017 Socionext Inc.
4 */
5#ifndef __CONFIG_H
6#define __CONFIG_H
7
8/* Timers for fasp(TIMCLK) */
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +09009#define CONFIG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */
10
11/*
12 * SDRAM (for initialize)
13 */
14#define CONFIG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */
15#define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */
16
17#define CONFIG_VERY_BIG_RAM /* SynQuacer supports up to 64GB */
18#define CONFIG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE
19
20#define SQ_DRAMINFO_BASE (0x2e00ffc0) /* DRAM info from TF-A */
21
22/*
23 * Boot info
24 */
25#define CONFIG_SYS_INIT_SP_ADDR (0xe0000000) /* stack of init proccess */
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090026
27/*
28 * Hardware drivers support
29 */
30
31/* RTC */
32#define CONFIG_SYS_I2C_RTC_ADDR 0x51
33
34/* Serial (pl011) */
35#define UART_CLK (62500000)
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090036#define CONFIG_PL011_CLOCK UART_CLK
37#define CONFIG_PL01x_PORTS {(void *)(0x2a400000)}
38
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090039/* Support MTD */
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090040#define CONFIG_SYS_FLASH_BASE (0x08000000)
41#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
42
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090043#define CONFIG_SYS_CBSIZE 1024
44#define CONFIG_SYS_MAXARGS 128
45#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
46
47/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090048
Masami Hiramatsu3a373862021-06-04 18:45:31 +090049#define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \
Masami Hiramatsu4d492b02021-11-10 09:40:07 +090050 "mtd nor1=u-boot.bin raw 200000 100000;" \
Masami Hiramatsu3a373862021-06-04 18:45:31 +090051 "fip.bin raw 180000 78000;" \
52 "optee.bin raw 500000 100000\0"
53
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090054/* Distro boot settings */
55#ifndef CONFIG_SPL_BUILD
56#ifdef CONFIG_CMD_USB
57#define BOOT_TARGET_DEVICE_USB(func) func(USB, usb, 0)
58#else
59#define BOOT_TARGET_DEVICE_USB(func)
60#endif
61
62#ifdef CONFIG_CMD_MMC
63#define BOOT_TARGET_DEVICE_MMC(func) func(MMC, mmc, 0)
64#else
65#define BOOT_TARGET_DEVICE_MMC(func)
66#endif
67
68#ifdef CONFIG_CMD_NVME
69#define BOOT_TARGET_DEVICE_NVME(func) func(NVME, nvme, 0)
70#else
71#define BOOT_TARGET_DEVICE_NVME(func)
72#endif
73
74#ifdef CONFIG_CMD_SCSI
75#define BOOT_TARGET_DEVICE_SCSI(func) func(SCSI, scsi, 0) func(SCSI, scsi, 1)
76#else
77#define BOOT_TARGET_DEVICE_SCSI(func)
78#endif
79
80#define BOOT_TARGET_DEVICES(func) \
81 BOOT_TARGET_DEVICE_USB(func) \
82 BOOT_TARGET_DEVICE_MMC(func) \
83 BOOT_TARGET_DEVICE_SCSI(func) \
84 BOOT_TARGET_DEVICE_NVME(func) \
85
86#include <config_distro_bootcmd.h>
87#else /* CONFIG_SPL_BUILD */
88#define BOOTENV
89#endif
90
91#define CONFIG_EXTRA_ENV_SETTINGS \
92 "fdt_addr_r=0x9fe00000\0" \
93 "kernel_addr_r=0x90000000\0" \
94 "ramdisk_addr_r=0xa0000000\0" \
95 "scriptaddr=0x88000000\0" \
96 "pxefile_addr_r=0x88100000\0" \
Masami Hiramatsu3a373862021-06-04 18:45:31 +090097 DEFAULT_DFU_ALT_INFO \
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090098 BOOTENV
99
100#endif /* __CONFIG_H */