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Ajay Bhargav51100cf2011-10-03 14:00:57 +05301/*
2 * (C) Copyright 2011
3 * eInfochips Ltd. <www.einfochips.com>
4 * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
5 *
6 * (C) Copyright 2009
7 * Marvell Semiconductor <www.marvell.com>
8 * Based on SSP driver
9 * Written-by: Lei Wen <leiwen@marvell.com>
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
27 * MA 02110-1301 USA
28 */
29
30
31#include <common.h>
32#include <malloc.h>
33#include <spi.h>
34
35#include <asm/io.h>
36#include <asm/arch/spi.h>
37#include <asm/gpio.h>
38
39#define to_armd_spi_slave(s) container_of(s, struct armd_spi_slave, slave)
40
41struct armd_spi_slave {
42 struct spi_slave slave;
43 struct ssp_reg *spi_reg;
44 u32 cr0, cr1;
45 u32 int_cr1;
46 u32 clear_sr;
47 const void *tx;
48 void *rx;
49 int gpio_cs_inverted;
50};
51
52static int spi_armd_write(struct armd_spi_slave *pss)
53{
54 int wait_timeout = SSP_FLUSH_NUM;
55 while (--wait_timeout && !(readl(&pss->spi_reg->sssr) & SSSR_TNF))
56 ;
57 if (!wait_timeout) {
58 debug("%s: timeout error\n", __func__);
59 return -1;
60 }
61
62 if (pss->tx != NULL) {
63 writel(*(u8 *)pss->tx, &pss->spi_reg->ssdr);
64 ++pss->tx;
65 } else {
66 writel(0, &pss->spi_reg->ssdr);
67 }
68 return 0;
69}
70
71static int spi_armd_read(struct armd_spi_slave *pss)
72{
73 int wait_timeout = SSP_FLUSH_NUM;
74 while (--wait_timeout && !(readl(&pss->spi_reg->sssr) & SSSR_RNE))
75 ;
76 if (!wait_timeout) {
77 debug("%s: timeout error\n", __func__);
78 return -1;
79 }
80
81 if (pss->rx != NULL) {
82 *(u8 *)pss->rx = readl(&pss->spi_reg->ssdr);
83 ++pss->rx;
84 } else {
85 readl(&pss->spi_reg->ssdr);
86 }
87 return 0;
88}
89
90static int spi_armd_flush(struct armd_spi_slave *pss)
91{
92 unsigned long limit = SSP_FLUSH_NUM;
93
94 do {
95 while (readl(&pss->spi_reg->sssr) & SSSR_RNE)
96 readl(&pss->spi_reg->ssdr);
97 } while ((readl(&pss->spi_reg->sssr) & SSSR_BSY) && limit--);
98
99 writel(SSSR_ROR, &pss->spi_reg->sssr);
100
101 return limit;
102}
103
104void spi_cs_activate(struct spi_slave *slave)
105{
106 struct armd_spi_slave *pss = to_armd_spi_slave(slave);
107
108 gpio_set_value(slave->cs, pss->gpio_cs_inverted);
109}
110
111void spi_cs_deactivate(struct spi_slave *slave)
112{
113 struct armd_spi_slave *pss = to_armd_spi_slave(slave);
114
115 gpio_set_value(slave->cs, !pss->gpio_cs_inverted);
116}
117
118struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
119 unsigned int max_hz, unsigned int mode)
120{
121 struct armd_spi_slave *pss;
122
123 pss = malloc(sizeof(*pss));
124 if (!pss)
125 return NULL;
126
127 pss->slave.bus = bus;
128 pss->slave.cs = cs;
129 pss->spi_reg = (struct ssp_reg *)SSP_REG_BASE(CONFIG_SYS_SSP_PORT);
130
131 pss->cr0 = SSCR0_MOTO | SSCR0_DATASIZE(DEFAULT_WORD_LEN) | SSCR0_SSE;
132
133 pss->cr1 = (SSCR1_RXTRESH(RX_THRESH_DEF) & SSCR1_RFT) |
134 (SSCR1_TXTRESH(TX_THRESH_DEF) & SSCR1_TFT);
135 pss->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
136 pss->cr1 |= (((mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
137 | (((mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
138
139 pss->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
140 pss->clear_sr = SSSR_ROR | SSSR_TINT;
141
142 pss->gpio_cs_inverted = mode & SPI_CS_HIGH;
143 gpio_set_value(cs, !pss->gpio_cs_inverted);
144
145 return &pss->slave;
146}
147
148void spi_free_slave(struct spi_slave *slave)
149{
150 struct armd_spi_slave *pss = to_armd_spi_slave(slave);
151
152 free(pss);
153}
154
155int spi_claim_bus(struct spi_slave *slave)
156{
157 struct armd_spi_slave *pss = to_armd_spi_slave(slave);
158
159 debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
160 if (spi_armd_flush(pss) == 0)
161 return -1;
162
163 return 0;
164}
165
166void spi_release_bus(struct spi_slave *slave)
167{
168}
169
170int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
171 void *din, unsigned long flags)
172{
173 struct armd_spi_slave *pss = to_armd_spi_slave(slave);
174 uint bytes = bitlen / 8;
175 unsigned long limit;
176 int ret = 0;
177
178 if (bitlen == 0)
179 goto done;
180
181 /* we can only do 8 bit transfers */
182 if (bitlen % 8) {
183 flags |= SPI_XFER_END;
184 goto done;
185 }
186
187 if (dout)
188 pss->tx = dout;
189 else
190 pss->tx = NULL;
191
192 if (din)
193 pss->rx = din;
194 else
195 pss->rx = NULL;
196
197 if (flags & SPI_XFER_BEGIN) {
198 spi_cs_activate(slave);
199 writel(pss->cr1 | pss->int_cr1, &pss->spi_reg->sscr1);
200 writel(TIMEOUT_DEF, &pss->spi_reg->ssto);
201 writel(pss->cr0, &pss->spi_reg->sscr0);
202 }
203
204 while (bytes--) {
205 limit = SSP_FLUSH_NUM;
206 ret = spi_armd_write(pss);
207 if (ret)
208 break;
209
210 while ((readl(&pss->spi_reg->sssr) & SSSR_BSY) && limit--)
211 udelay(1);
212
213 ret = spi_armd_read(pss);
214 if (ret)
215 break;
216 }
217
218 done:
219 if (flags & SPI_XFER_END) {
220 /* Stop SSP */
221 writel(pss->clear_sr, &pss->spi_reg->sssr);
222 clrbits_le32(&pss->spi_reg->sscr1, pss->int_cr1);
223 writel(0, &pss->spi_reg->ssto);
224 spi_cs_deactivate(slave);
225 }
226
227 return ret;
228}