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wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2001
3 * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenke2211742002-11-02 23:30:20 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
wdenke2211742002-11-02 23:30:20 +000021#define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */
22#define CONFIG_W7OLMC 1 /* ...specifically an LMC */
23
Wolfgang Denk2ae18242010-10-06 09:05:45 +020024#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
25
wdenkc837dcb2004-01-20 23:12:12 +000026#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
27#define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */
Peter Tyser3a8f28d2009-09-16 22:03:07 -050028#define CONFIG_MISC_INIT_R 1 /* and misc_init_r() */
wdenke2211742002-11-02 23:30:20 +000029
30#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
31
32#define CONFIG_BAUDRATE 9600
33#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
34
35#if 1
36#define CONFIG_BOOTCOMMAND "bootvx" /* VxWorks boot command */
37#else
38#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
39#endif
40
41#undef CONFIG_BOOTARGS
42
43#define CONFIG_LOADADDR F0080000
44
45#define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden at boot */
46#define CONFIG_OVERWRITE_ETHADDR_ONCE
47#define CONFIG_IPADDR 192.168.1.1
48#define CONFIG_NETMASK 255.255.255.0
49#define CONFIG_SERVERIP 192.168.1.2
50
51#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* disallow baudrate change */
wdenke2211742002-11-02 23:30:20 +000053
Ben Warren96e21f82008-10-27 23:50:15 -070054#define CONFIG_PPC4xx_EMAC
wdenke2211742002-11-02 23:30:20 +000055#define CONFIG_MII 1 /* MII PHY management */
56#define CONFIG_PHY_ADDR 0 /* PHY address */
57
58#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
59
Jon Loeligera5562902007-07-08 15:31:57 -050060/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050061 * BOOTP options
62 */
63#define CONFIG_BOOTP_BOOTFILESIZE
64#define CONFIG_BOOTP_BOOTPATH
65#define CONFIG_BOOTP_GATEWAY
66#define CONFIG_BOOTP_HOSTNAME
67
68
69/*
Jon Loeligera5562902007-07-08 15:31:57 -050070 * Command line configuration.
71 */
72#include <config_cmd_default.h>
wdenke2211742002-11-02 23:30:20 +000073
Jon Loeligera5562902007-07-08 15:31:57 -050074#define CONFIG_CMD_PCI
75#define CONFIG_CMD_IRQ
76#define CONFIG_CMD_ASKENV
77#define CONFIG_CMD_DHCP
78#define CONFIG_CMD_BEDBUG
79#define CONFIG_CMD_DATE
80#define CONFIG_CMD_I2C
81#define CONFIG_CMD_EEPROM
82#define CONFIG_CMD_ELF
83#define CONFIG_CMD_BSP
84#define CONFIG_CMD_REGINFO
wdenke2211742002-11-02 23:30:20 +000085
86#undef CONFIG_WATCHDOG /* watchdog disabled */
87#define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */
88
89#define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */
wdenkdb2f721f2003-03-06 00:58:30 +000090#define CONFIG_SPDDRAM_SILENT /* No output if spd fails */
wdenke2211742002-11-02 23:30:20 +000091/*
92 * Miscellaneous configurable options
93 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_LONGHELP /* undef to save memory */
95#define CONFIG_SYS_PROMPT "Wave7Optics> " /* Monitor Command Prompt */
96#undef CONFIG_SYS_HUSH_PARSER /* No hush parse for U-Boot */
97#ifdef CONFIG_SYS_HUSH_PARSER
wdenke2211742002-11-02 23:30:20 +000098#endif
Jon Loeligera5562902007-07-08 15:31:57 -050099#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000101#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000103#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
105#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
106#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000107
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
109#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenke2211742002-11-02 23:30:20 +0000110
Stefan Roese550650d2010-09-20 16:05:31 +0200111#define CONFIG_CONS_INDEX 1 /* Use UART0 */
112#define CONFIG_SYS_NS16550
113#define CONFIG_SYS_NS16550_SERIAL
114#define CONFIG_SYS_NS16550_REG_SIZE 1
115#define CONFIG_SYS_NS16550_CLK get_serial_clock()
116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
118#define CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
119#define CONFIG_SYS_BASE_BAUD 384000
wdenke2211742002-11-02 23:30:20 +0000120
121
122/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_BAUDRATE_TABLE {9600}
wdenke2211742002-11-02 23:30:20 +0000124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
126#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info (bd_t) */
wdenke2211742002-11-02 23:30:20 +0000127
wdenke2211742002-11-02 23:30:20 +0000128/*-----------------------------------------------------------------------
129 * PCI stuff
130 *-----------------------------------------------------------------------
131 */
132#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
133#define PCI_HOST_FORCE 1 /* configure as pci host */
134#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
135
136
137#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000138#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
wdenke2211742002-11-02 23:30:20 +0000139#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
140#define CONFIG_PCI_PNP /* pci plug-and-play */
141/* resource configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
143#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */
144#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
145#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
146#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
147#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
148#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
149#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
wdenke2211742002-11-02 23:30:20 +0000150
151/*-----------------------------------------------------------------------
152 * Set up values for external bus controller
153 * used by cpu_init.c
154 *-----------------------------------------------------------------------
155 */
156 /* Don't use PerWE instead of PCI_INT ( these functions share a pin ) */
157#undef CONFIG_USE_PERWE
158
159/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_TEMP_STACK_OCM 1
wdenke2211742002-11-02 23:30:20 +0000161
162/* bank 0 is boot flash */
163/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_W7O_EBC_PB0AP 0x03050440
wdenke2211742002-11-02 23:30:20 +0000165/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_W7O_EBC_PB0CR 0xFFE38000
wdenke2211742002-11-02 23:30:20 +0000167
168/* bank 1 is main flash */
169/* BME=0,TWT=11,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_EBC_PB1AP 0x05850240
wdenke2211742002-11-02 23:30:20 +0000171/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_EBC_PB1CR 0xF00FC000
wdenke2211742002-11-02 23:30:20 +0000173
174/* bank 2 is RTC/NVRAM */
175/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_EBC_PB2AP 0x03000440
wdenke2211742002-11-02 23:30:20 +0000177/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_EBC_PB2CR 0xFC018000
wdenke2211742002-11-02 23:30:20 +0000179
180/* bank 3 is FPGA 0 */
181/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_EBC_PB3AP 0x02000400
wdenke2211742002-11-02 23:30:20 +0000183/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_EBC_PB3CR 0xFD01A000
wdenke2211742002-11-02 23:30:20 +0000185
186/* bank 4 is FPGA 1 */
187/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_EBC_PB4AP 0x02000400
wdenke2211742002-11-02 23:30:20 +0000189/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_EBC_PB4CR 0xFD11A000
wdenke2211742002-11-02 23:30:20 +0000191
192/* bank 5 is FPGA 2 */
193/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_EBC_PB5AP 0x02000400
wdenke2211742002-11-02 23:30:20 +0000195/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_EBC_PB5CR 0xFD21A000
wdenke2211742002-11-02 23:30:20 +0000197
198/* bank 6 is unused */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200199/* PB6AP = 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_EBC_PB6AP 0x00000000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200201/* PB6CR = 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_EBC_PB6CR 0x00000000
wdenke2211742002-11-02 23:30:20 +0000203
204/* bank 7 is LED register */
205/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_W7O_EBC_PB7AP 0x03050440
wdenke2211742002-11-02 23:30:20 +0000207/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_W7O_EBC_PB7CR 0xFE01C000
wdenke2211742002-11-02 23:30:20 +0000209
210/*-----------------------------------------------------------------------
211 * Start addresses for the final memory configuration
212 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenke2211742002-11-02 23:30:20 +0000214 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_SDRAM_BASE 0x00000000
216#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
217#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
218#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
219#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
wdenke2211742002-11-02 23:30:20 +0000220
221/*
222 * For booting Linux, the board info and command line data
223 * have to be in the first 8 MB of memory, since this is
224 * the maximum mapped by the Linux kernel during initialization.
225 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenke2211742002-11-02 23:30:20 +0000227/*-----------------------------------------------------------------------
228 * FLASH organization
229 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
231#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */
wdenke2211742002-11-02 23:30:20 +0000232
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */
234#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */
235#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use real Flash protection */
wdenke2211742002-11-02 23:30:20 +0000236
237#if 1 /* Use NVRAM for environment variables */
238/*-----------------------------------------------------------------------
239 * NVRAM organization
240 */
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200241#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */
243#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200244#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
245/*define CONFIG_ENV_ADDR \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) Env */
247#define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR
wdenke2211742002-11-02 23:30:20 +0000248
249#else /* Use Boot Flash for environment variables */
250/*-----------------------------------------------------------------------
251 * Flash EEPROM for environment
252 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200253#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200254#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
255#define CONFIG_ENV_SIZE 0x10000 /* Total Size of env. sector */
wdenke2211742002-11-02 23:30:20 +0000256
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200257#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */
wdenke2211742002-11-02 23:30:20 +0000258#endif
259
260/*-----------------------------------------------------------------------
261 * I2C EEPROM (CAT24WC08) for environment
262 */
Dirk Eibach880540d2013-04-25 02:40:01 +0000263#define CONFIG_SYS_I2C
264#define CONFIG_SYS_I2C_PPC4XX
265#define CONFIG_SYS_I2C_PPC4XX_CH0
266#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
267#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
wdenke2211742002-11-02 23:30:20 +0000268
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
270#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
wdenke2211742002-11-02 23:30:20 +0000271/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
273#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
wdenke2211742002-11-02 23:30:20 +0000274 /* 16 byte page write mode using*/
275 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_I2C_MULTI_EEPROMS
wdenke2211742002-11-02 23:30:20 +0000277/*-----------------------------------------------------------------------
278 * Definitions for Serial Presence Detect EEPROM address
279 * (to get SDRAM settings)
280 */
281#define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */
282
wdenke2211742002-11-02 23:30:20 +0000283/*
284 * Init Memory Controller:
285 */
286#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
287#define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */
288
289/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
291#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
wdenke2211742002-11-02 23:30:20 +0000292
293/*-----------------------------------------------------------------------
294 * Definitions for initial stack pointer and data area (in RAM)
295 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200297#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200298#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke2211742002-11-02 23:30:20 +0000300
Jon Loeligera5562902007-07-08 15:31:57 -0500301#if defined(CONFIG_CMD_KGDB)
wdenke2211742002-11-02 23:30:20 +0000302#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
wdenke2211742002-11-02 23:30:20 +0000303#endif
304
305/*
306 * FPGA(s) configuration
307 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */
wdenke2211742002-11-02 23:30:20 +0000309#define CONFIG_NUM_FPGAS 3 /* Number of FPGAs on board */
310#define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */
311#define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */
312#define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */
313
314#endif /* __CONFIG_H */