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Helmut Raiger4d86dd02011-10-27 01:31:15 +00001/*
2 * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
3 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
4 *
5 * Configuration settings for the HALE TT-01 board.
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
Helmut Raiger4d86dd02011-10-27 01:31:15 +00008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#include <asm/arch/imx-regs.h>
14
15/* High Level Configuration Options */
16#define CONFIG_ARM1136
17#define CONFIG_MX31
Helmut Raiger4d86dd02011-10-27 01:31:15 +000018
19#define CONFIG_DISPLAY_CPUINFO
20#define CONFIG_DISPLAY_BOARDINFO
21
22#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
23#define CONFIG_SETUP_MEMORY_TAGS
24#define CONFIG_INITRD_TAG
25
26#define CONFIG_MACH_TYPE 3726 /* not yet in mach-types.h */
27#define CONFIG_SYS_TEXT_BASE 0xA0000000
28
29
30/*
31 * Physical Memory Map:
32 * CS settings are defined by i.MX31:
33 * - CSD0 and CDS1 are 256MB each, starting at 0x80000000 and 0x9000000
34 * - CS0 and CS1 are 128MB each, at A0000000 and A8000000
35 * - CS2 to CS5 are 32MB each, at B0.., B2.., B4.., B6..
36 *
37 * HALE set-up of the bluetechnix board for now is:
38 * - 128MB DDR (2x64MB, 2x16bit), connected to 32bit DDR ram interface
39 * - NOR-Flash (Spansion 32MB MCP, Flash+16MB PSRAM), 16bit interface at CS0
40 * - S71WS256ND0BFWYM (and CS1 for 64MB S71WS512ND0 without PSRAM)
41 * the flash chip is a mirrorbit S29WS256N !
42 * - the PSRAM is hooked to CS5 (0xB6000000)
43 * - Intel Strata Flash PF48F2000P0ZB00, 16bit interface at (CS0 or) CS1
44 * - 64Mbit = 8MByte (will go away in the production set-up)
45 * - NAND-Flash NAND01GR3B2BZA6 at NAND-FC:
46 * 1Gbit=128MB, 2048+64 bytes/page, 64pages x 1024 blocks
47 * - Ethernet controller SMC9118 at CS4 via FPGA, 16bit interface
48 *
49 * u-boot will support the 32MB nor flash and the 128MB NAND flash, the PSRAM
50 * is not used right now. We should be able to reduce the SOM to NAND flash
51 * only and boot from there.
52 */
53#define CONFIG_NR_DRAM_BANKS 1
54#define PHYS_SDRAM_1 CSD0_BASE
55#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
56
57#define CONFIG_BOARD_EARLY_INIT_F
58#define CONFIG_BOARD_LATE_INIT
59
60#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
61#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
62#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
63#define CONFIG_SYS_GBL_DATA_OFFSET \
64 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
65#define CONFIG_SYS_INIT_SP_ADDR \
66 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
67
68/* default load address, 1MB up the road */
69#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1+0x100000)
70
Helmut Raiger4d86dd02011-10-27 01:31:15 +000071/* Size of malloc() pool, make sure possible frame buffer fits */
72#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 10*1024*1024)
73
74/* memtest works on all but the last 1MB (u-boot) and malloc area */
75#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
76#define CONFIG_SYS_MEMTEST_END \
77 (PHYS_SDRAM_1+(PHYS_SDRAM_1_SIZE-CONFIG_SYS_MALLOC_LEN-0x100000))
78
79/* CFI FLASH driver setup */
80#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
81#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
82#define CONFIG_FLASH_SPANSION_S29WS_N
83/*
84 * TODO: Bluetechnix (the supplier of the SOM) did define these values
85 * in their original version of u-boot (1.2 or so). This should be
86 * reviewed.
87 *
88 * #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
89 * #define CONFIG_SYS_FLASH_PROTECTION
90 */
91#define CONFIG_SYS_FLASH_BASE CS0_BASE
92#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
93#define CONFIG_SYS_MAX_FLASH_SECT (254+8) /* max number of sectors per chip */
94
95/*
96 * FLASH and environment organization, only the Spansion chip is supported:
97 * - it has 254 * 128kB + 8 * 32kB blocks
98 * - this setup uses 4*32k+3*128k as monitor space = 0xA000 0000 to 0xA00F FFFF
99 * and 2 sectors with 128k as environment =
100 * A010 0000 to 0xA011 FFFF and 0xA012 0000 to 0xA013 FFFF
101 * - this could be less, but this is only for developer versions of the board
102 * and no-one is going to use the NOR flash anyway.
103 *
104 * Monitor is at the beginning of the NOR-Flash, 1MB reserved. Again this is
105 * way to large, but it avoids ENV overwrite (when updating u-boot) in case
106 * size breaks the next boundary (as it has with 128k).
107 */
108#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
109#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
110
111#define CONFIG_ENV_IS_IN_FLASH
112#define CONFIG_ENV_SECT_SIZE (128 * 1024)
Helmut Raiger0b87e012012-01-30 04:21:53 +0000113#define CONFIG_ENV_SIZE (128 * 1024)
Helmut Raiger4d86dd02011-10-27 01:31:15 +0000114
115/* Address and size of Redundant Environment Sector */
116#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
117#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
118
119#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
120
121/* Hardware drivers */
122
123/*
124 * on TT-01 UART1 pins are used by Audio, so we use UART2
125 * TT-01 implements a hardware that turns off components depending on
126 * the power level. In PL=1 the RS232 transceiver is usually off,
127 * make sure that the transceiver is enabled during PL=1 for testing!
128 */
129#define CONFIG_MXC_UART
Stefano Babic40f6fff2011-11-22 15:22:39 +0100130#define CONFIG_MXC_UART_BASE UART2_BASE
Helmut Raiger4d86dd02011-10-27 01:31:15 +0000131
132#define CONFIG_MXC_SPI
133#define CONFIG_MXC_GPIO
134
135/* MC13783 connected to CSPI3 and SS0 */
Ɓukasz Majewskibe3b51a2012-11-13 03:22:14 +0000136#define CONFIG_POWER
137#define CONFIG_POWER_SPI
138#define CONFIG_POWER_FSL
Helmut Raiger4d86dd02011-10-27 01:31:15 +0000139
140#define CONFIG_FSL_PMIC_BUS 2
141#define CONFIG_FSL_PMIC_CS 0
142#define CONFIG_FSL_PMIC_CLK 1000000
143#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
144#define CONFIG_FSL_PMIC_BITLEN 32
145
146#define CONFIG_RTC_MC13XXX
147
148/* allow to overwrite serial and ethaddr */
149#define CONFIG_ENV_OVERWRITE
150/* console is UART2 on TT-01 */
151#define CONFIG_CONS_INDEX 1
152#define CONFIG_BAUDRATE 115200
Helmut Raiger4d86dd02011-10-27 01:31:15 +0000153
154/* ethernet setup for the onboard smc9118 */
155#define CONFIG_MII
156#define CONFIG_SMC911X
157/* 16 bit, onboard ethernet, decoded via MACH-MX0 FPGA at 0x84200000 */
158#define CONFIG_SMC911X_BASE (CS4_BASE+0x200000)
159#define CONFIG_SMC911X_16_BIT
160
Helmut Raigerf3535182012-01-18 21:27:13 +0000161/* mmc driver */
162#define CONFIG_MMC
163#define CONFIG_GENERIC_MMC
164#define CONFIG_MXC_MMC
165#define CONFIG_MXC_MCI_REGS_BASE SDHC1_BASE_ADDR
Helmut Raigerd1300f72012-02-15 22:40:12 +0000166
167/* video support */
168#define CONFIG_VIDEO
169#define CONFIG_VIDEO_MX3
170#define CONFIG_CFB_CONSOLE
171#define CONFIG_VIDEO_LOGO
Helmut Raiger07c80bc2012-01-30 04:21:55 +0000172/* splash image won't work with NAND boot, use preboot script */
Helmut Raigerd1300f72012-02-15 22:40:12 +0000173#define CONFIG_VIDEO_SW_CURSOR
174#define CONFIG_CONSOLE_EXTRA_INFO /* display additional board info */
175#define CONFIG_VGA_AS_SINGLE_DEVICE /* display is an output only device */
Helmut Raiger07c80bc2012-01-30 04:21:55 +0000176
Helmut Raigerd1300f72012-02-15 22:40:12 +0000177/* allow stdin, stdout and stderr variables to redirect output */
178#define CONFIG_SYS_CONSOLE_IS_IN_ENV
Helmut Raiger07c80bc2012-01-30 04:21:55 +0000179#define CONFIG_SILENT_CONSOLE /* UARTs used externally (release) */
180#define CONFIG_SYS_DEVICE_NULLDEV /* allow console to be turned off */
181#define CONFIG_PREBOOT
Helmut Raigerd1300f72012-02-15 22:40:12 +0000182
183/* allow decompressing max. 4MB */
184#define CONFIG_VIDEO_BMP_GZIP
185/* this is not only used by cfb_console.c for the logo, but also in cmd_bmp.c */
186#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4*1024*1024)
187
Helmut Raiger4d86dd02011-10-27 01:31:15 +0000188/*
189 * Command definition
190 */
191
192#include <config_cmd_default.h>
193
194#define CONFIG_CMD_DATE
195#define CONFIG_CMD_PING
196#define CONFIG_CMD_DHCP
197#define CONFIG_CMD_SAVEENV
198#define CONFIG_CMD_NAND
199/*
200 * #define CONFIG_CMD_NAND_LOCK_UNLOCK the NAND01... chip does not support
201 * the NAND_CMD_LOCK_STATUS command, however the NFC of i.MX31 supports
202 * a software locking scheme.
203 */
Helmut Raigerd1300f72012-02-15 22:40:12 +0000204#define CONFIG_CMD_BMP
Helmut Raiger4d86dd02011-10-27 01:31:15 +0000205
206#define CONFIG_BOOTDELAY 3
207
208/*
209 * currently a default setting for booting via script is implemented
210 * set user to login name and serverip to tftp host, define your
211 * boot behaviour in bootscript.loginname
Helmut Raigerd1300f72012-02-15 22:40:12 +0000212 *
213 * TT-01 board specific TFT setup (used by drivers/video/mx3fb.c)
214 *
215 * This set-up is for the L5F30947T04 by Epson, which is
216 * 800x480, 33MHz pixel clock, 60Hz vsync, 31.6kHz hsync
217 * sync must be set to: DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL
Helmut Raiger4d86dd02011-10-27 01:31:15 +0000218 */
219#define CONFIG_EXTRA_ENV_SETTINGS \
Helmut Raigerd1300f72012-02-15 22:40:12 +0000220"videomode=epson\0" \
221"epson=video=ctfb:x:800,y:480,depth:16,mode:0,pclk:30076," \
222 "le:215,ri:1,up:32,lo:13,hs:7,vs:10,sync:100663296,vmode:0\0" \
Helmut Raiger07c80bc2012-01-30 04:21:55 +0000223"bootcmd=dhcp bootscript.${user}; source\0"
Helmut Raiger4d86dd02011-10-27 01:31:15 +0000224
225#define CONFIG_BOOTP_SERVERIP /* tftp serverip not overruled by dhcp server */
226#define CONFIG_BOOTP_SEND_HOSTNAME /* if env-var 'hostname' is set, send it */
227
228/* Miscellaneous configurable options */
Helmut Raiger07c80bc2012-01-30 04:21:55 +0000229#define CONFIG_SYS_HUSH_PARSER
Helmut Raiger4d86dd02011-10-27 01:31:15 +0000230
231#define CONFIG_SYS_LONGHELP /* undef to save memory */
232#define CONFIG_SYS_PROMPT "TT01> "
233#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
234/* Print Buffer Size */
235#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
236 sizeof(CONFIG_SYS_PROMPT)+16)
237/* max number of command args */
238#define CONFIG_SYS_MAXARGS 16
239/* Boot Argument Buffer Size */
240#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
241
Helmut Raiger4d86dd02011-10-27 01:31:15 +0000242#define CONFIG_CMDLINE_EDITING
243
Helmut Raigerf3535182012-01-18 21:27:13 +0000244/* MMC boot support */
245#define CONFIG_CMD_MMC
246#define CONFIG_DOS_PARTITION
247#define CONFIG_EFI_PARTITION
248#define CONFIG_CMD_EXT2
249#define CONFIG_CMD_FAT
250
Helmut Raiger4d86dd02011-10-27 01:31:15 +0000251#define CONFIG_NAND_MXC
252#define CONFIG_SYS_MAX_NAND_DEVICE 1
Helmut Raiger4d86dd02011-10-27 01:31:15 +0000253
254/*
255 * actually this is nothing someone wants to configure!
256 * CONFIG_SYS_NAND_BASE despite being passed to board_nand_init()
257 * is not used by the driver.
258 */
259#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
260#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
261#define CONFIG_MXC_NAND_HWECC
262
263/* the current u-boot driver does not use the nand flash setup! */
264#define CONFIG_SYS_NAND_LARGEPAGE
265/*
266 * it's not 16 bit:
267 * #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
268 * the current u-boot mxc_nand.c tries to auto-detect, but this only
269 * reads the boot settings during reset (which might be wrong)
270 */
271
272#endif /* __CONFIG_H */