blob: 802e4330440e21e6a27fe08acafc58a5876e571a [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
4 *
5 * (C) Copyright 2002
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
8 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +000010 */
11
12/*
13 * PCI routines
14 */
15
16#include <common.h>
Simon Glass0098e172014-04-10 20:01:30 -060017#include <bootretry.h>
Simon Glass18d66532014-04-10 20:01:25 -060018#include <cli.h>
wdenkc6097192002-11-03 00:24:07 +000019#include <command.h>
Simon Glass24b852a2015-11-08 23:47:45 -070020#include <console.h>
wdenkc6097192002-11-03 00:24:07 +000021#include <asm/processor.h>
22#include <asm/io.h>
wdenkc6097192002-11-03 00:24:07 +000023#include <pci.h>
24
wdenkc6097192002-11-03 00:24:07 +000025/*
26 * Follows routines for the output of infos about devices on PCI bus.
27 */
28
29void pci_header_show(pci_dev_t dev);
30void pci_header_show_brief(pci_dev_t dev);
31
32/*
33 * Subroutine: pciinfo
34 *
35 * Description: Show information about devices on PCI bus.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036 * Depending on the define CONFIG_SYS_SHORT_PCI_LISTING
wdenkc6097192002-11-03 00:24:07 +000037 * the output will be more or less exhaustive.
38 *
39 * Inputs: bus_no the number of the bus to be scanned.
40 *
41 * Return: None
42 *
43 */
44void pciinfo(int BusNum, int ShortPCIListing)
45{
Thierry Reding042b83d2014-11-12 18:26:48 -070046 struct pci_controller *hose = pci_bus_to_hose(BusNum);
wdenkc6097192002-11-03 00:24:07 +000047 int Device;
48 int Function;
49 unsigned char HeaderType;
50 unsigned short VendorID;
51 pci_dev_t dev;
Simon Glassff3e0772015-03-05 12:25:25 -070052 int ret;
wdenkc6097192002-11-03 00:24:07 +000053
Thierry Reding042b83d2014-11-12 18:26:48 -070054 if (!hose)
55 return;
56
wdenkc6097192002-11-03 00:24:07 +000057 printf("Scanning PCI devices on bus %d\n", BusNum);
58
59 if (ShortPCIListing) {
60 printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
61 printf("_____________________________________________________________\n");
62 }
63
64 for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) {
65 HeaderType = 0;
66 VendorID = 0;
67 for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) {
68 /*
69 * If this is not a multi-function device, we skip the rest.
70 */
71 if (Function && !(HeaderType & 0x80))
72 break;
73
74 dev = PCI_BDF(BusNum, Device, Function);
75
Thierry Reding4efe52b2014-11-12 18:26:49 -070076 if (pci_skip_dev(hose, dev))
77 continue;
78
Simon Glassff3e0772015-03-05 12:25:25 -070079 ret = pci_read_config_word(dev, PCI_VENDOR_ID,
80 &VendorID);
81 if (ret)
82 goto error;
wdenkc6097192002-11-03 00:24:07 +000083 if ((VendorID == 0xFFFF) || (VendorID == 0x0000))
84 continue;
85
wdenkc7de8292002-11-19 11:04:11 +000086 if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType);
wdenkc6097192002-11-03 00:24:07 +000087
88 if (ShortPCIListing)
89 {
90 printf("%02x.%02x.%02x ", BusNum, Device, Function);
91 pci_header_show_brief(dev);
92 }
93 else
94 {
95 printf("\nFound PCI device %02x.%02x.%02x:\n",
96 BusNum, Device, Function);
97 pci_header_show(dev);
98 }
Simon Glassff3e0772015-03-05 12:25:25 -070099 }
100 }
101
102 return;
103error:
104 printf("Cannot read bus configuration: %d\n", ret);
wdenkc6097192002-11-03 00:24:07 +0000105}
106
wdenkc6097192002-11-03 00:24:07 +0000107
108/*
109 * Subroutine: pci_header_show_brief
110 *
111 * Description: Reads and prints the header of the
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200112 * specified PCI device in short form.
wdenkc6097192002-11-03 00:24:07 +0000113 *
114 * Inputs: dev Bus+Device+Function number
115 *
116 * Return: None
117 *
118 */
119void pci_header_show_brief(pci_dev_t dev)
120{
121 u16 vendor, device;
122 u8 class, subclass;
123
124 pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
125 pci_read_config_word(dev, PCI_DEVICE_ID, &device);
126 pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
127 pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);
128
wdenk5d232d02003-05-22 22:52:13 +0000129 printf("0x%.4x 0x%.4x %-23s 0x%.2x\n",
wdenkc6097192002-11-03 00:24:07 +0000130 vendor, device,
Peter Tyser983eb9d2010-10-29 17:59:27 -0500131 pci_class_str(class), subclass);
wdenkc6097192002-11-03 00:24:07 +0000132}
133
134/*
135 * Subroutine: PCI_Header_Show
136 *
137 * Description: Reads the header of the specified PCI device.
138 *
139 * Inputs: BusDevFunc Bus+Device+Function number
140 *
141 * Return: None
142 *
143 */
144void pci_header_show(pci_dev_t dev)
145{
146 u8 _byte, header_type;
147 u16 _word;
148 u32 _dword;
149
150#define PRINT(msg, type, reg) \
151 pci_read_config_##type(dev, reg, &_##type); \
152 printf(msg, _##type)
153
154#define PRINT2(msg, type, reg, func) \
155 pci_read_config_##type(dev, reg, &_##type); \
156 printf(msg, _##type, func(_##type))
157
158 pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
159
160 PRINT (" vendor ID = 0x%.4x\n", word, PCI_VENDOR_ID);
161 PRINT (" device ID = 0x%.4x\n", word, PCI_DEVICE_ID);
162 PRINT (" command register = 0x%.4x\n", word, PCI_COMMAND);
163 PRINT (" status register = 0x%.4x\n", word, PCI_STATUS);
164 PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID);
165 PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE,
Peter Tyser983eb9d2010-10-29 17:59:27 -0500166 pci_class_str);
wdenkc6097192002-11-03 00:24:07 +0000167 PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE);
168 PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG);
169 PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE);
170 PRINT (" latency time = 0x%.2x\n", byte, PCI_LATENCY_TIMER);
171 PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE);
172 PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST);
173 PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0);
wdenkc6097192002-11-03 00:24:07 +0000174
wdenk7c7a23b2002-12-07 00:20:59 +0000175 switch (header_type & 0x03) {
176 case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
177 PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
178 PRINT (" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
179 PRINT (" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
180 PRINT (" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
181 PRINT (" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
182 PRINT (" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS);
183 PRINT (" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
184 PRINT (" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID);
185 PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS);
186 PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
187 PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
188 PRINT (" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT);
189 PRINT (" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT);
190 break;
wdenk8bde7f72003-06-27 21:31:46 +0000191
wdenk7c7a23b2002-12-07 00:20:59 +0000192 case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
193
194 PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
wdenkc6097192002-11-03 00:24:07 +0000195 PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS);
196 PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS);
197 PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS);
198 PRINT (" secondary latency timer = 0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER);
199 PRINT (" IO base = 0x%.2x\n", byte, PCI_IO_BASE);
200 PRINT (" IO limit = 0x%.2x\n", byte, PCI_IO_LIMIT);
201 PRINT (" secondary status = 0x%.4x\n", word, PCI_SEC_STATUS);
202 PRINT (" memory base = 0x%.4x\n", word, PCI_MEMORY_BASE);
203 PRINT (" memory limit = 0x%.4x\n", word, PCI_MEMORY_LIMIT);
204 PRINT (" prefetch memory base = 0x%.4x\n", word, PCI_PREF_MEMORY_BASE);
205 PRINT (" prefetch memory limit = 0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT);
206 PRINT (" prefetch memory base upper = 0x%.8x\n", dword, PCI_PREF_BASE_UPPER32);
207 PRINT (" prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32);
208 PRINT (" IO base upper 16 bits = 0x%.4x\n", word, PCI_IO_BASE_UPPER16);
209 PRINT (" IO limit upper 16 bits = 0x%.4x\n", word, PCI_IO_LIMIT_UPPER16);
210 PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS1);
211 PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
212 PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
213 PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL);
wdenk7c7a23b2002-12-07 00:20:59 +0000214 break;
215
216 case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
217
218 PRINT (" capabilities = 0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST);
219 PRINT (" secondary status = 0x%.4x\n", word, PCI_CB_SEC_STATUS);
220 PRINT (" primary bus number = 0x%.2x\n", byte, PCI_CB_PRIMARY_BUS);
221 PRINT (" CardBus number = 0x%.2x\n", byte, PCI_CB_CARD_BUS);
222 PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS);
wdenk8bde7f72003-06-27 21:31:46 +0000223 PRINT (" CardBus latency timer = 0x%.2x\n", byte, PCI_CB_LATENCY_TIMER);
wdenk7c7a23b2002-12-07 00:20:59 +0000224 PRINT (" CardBus memory base 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0);
225 PRINT (" CardBus memory limit 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0);
226 PRINT (" CardBus memory base 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1);
227 PRINT (" CardBus memory limit 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1);
228 PRINT (" CardBus IO base 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0);
229 PRINT (" CardBus IO base high 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0_HI);
230 PRINT (" CardBus IO limit 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0);
231 PRINT (" CardBus IO limit high 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI);
232 PRINT (" CardBus IO base 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1);
233 PRINT (" CardBus IO base high 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1_HI);
234 PRINT (" CardBus IO limit 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1);
235 PRINT (" CardBus IO limit high 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI);
236 PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
237 PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
238 PRINT (" bridge control = 0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL);
239 PRINT (" subvendor ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID);
240 PRINT (" subdevice ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID);
241 PRINT (" PC Card 16bit base address = 0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE);
242 break;
wdenk8bde7f72003-06-27 21:31:46 +0000243
wdenk7c7a23b2002-12-07 00:20:59 +0000244 default:
245 printf("unknown header\n");
wdenk8bde7f72003-06-27 21:31:46 +0000246 break;
wdenkc6097192002-11-03 00:24:07 +0000247 }
248
249#undef PRINT
250#undef PRINT2
251}
252
253/* Convert the "bus.device.function" identifier into a number.
254 */
255static pci_dev_t get_pci_dev(char* name)
256{
257 char cnum[12];
258 int len, i, iold, n;
259 int bdfs[3] = {0,0,0};
260
261 len = strlen(name);
262 if (len > 8)
263 return -1;
264 for (i = 0, iold = 0, n = 0; i < len; i++) {
265 if (name[i] == '.') {
266 memcpy(cnum, &name[iold], i - iold);
267 cnum[i - iold] = '\0';
268 bdfs[n++] = simple_strtoul(cnum, NULL, 16);
269 iold = i + 1;
270 }
271 }
272 strcpy(cnum, &name[iold]);
273 if (n == 0)
274 n = 1;
275 bdfs[n] = simple_strtoul(cnum, NULL, 16);
276 return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
277}
278
279static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length)
280{
281#define DISP_LINE_LEN 16
282 ulong i, nbytes, linebytes;
283 int rc = 0;
284
285 if (length == 0)
286 length = 0x40 / size; /* Standard PCI configuration space */
287
288 /* Print the lines.
289 * once, and all accesses are with the specified bus width.
290 */
291 nbytes = length * size;
292 do {
293 uint val4;
294 ushort val2;
295 u_char val1;
296
297 printf("%08lx:", addr);
298 linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes;
299 for (i=0; i<linebytes; i+= size) {
300 if (size == 4) {
301 pci_read_config_dword(bdf, addr, &val4);
302 printf(" %08x", val4);
303 } else if (size == 2) {
304 pci_read_config_word(bdf, addr, &val2);
305 printf(" %04x", val2);
306 } else {
307 pci_read_config_byte(bdf, addr, &val1);
308 printf(" %02x", val1);
309 }
310 addr += size;
311 }
312 printf("\n");
313 nbytes -= linebytes;
314 if (ctrlc()) {
315 rc = 1;
316 break;
317 }
318 } while (nbytes > 0);
319
320 return (rc);
321}
322
323static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
324{
325 if (size == 4) {
326 pci_write_config_dword(bdf, addr, value);
327 }
328 else if (size == 2) {
329 ushort val = value & 0xffff;
330 pci_write_config_word(bdf, addr, val);
331 }
332 else {
333 u_char val = value & 0xff;
334 pci_write_config_byte(bdf, addr, val);
335 }
336 return 0;
337}
338
339static int
340pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag)
341{
342 ulong i;
343 int nbytes;
wdenkc6097192002-11-03 00:24:07 +0000344 uint val4;
345 ushort val2;
346 u_char val1;
347
348 /* Print the address, followed by value. Then accept input for
349 * the next value. A non-converted value exits.
350 */
351 do {
352 printf("%08lx:", addr);
353 if (size == 4) {
354 pci_read_config_dword(bdf, addr, &val4);
355 printf(" %08x", val4);
356 }
357 else if (size == 2) {
358 pci_read_config_word(bdf, addr, &val2);
359 printf(" %04x", val2);
360 }
361 else {
362 pci_read_config_byte(bdf, addr, &val1);
363 printf(" %02x", val1);
364 }
365
Simon Glasse1bf8242014-04-10 20:01:27 -0600366 nbytes = cli_readline(" ? ");
wdenkc6097192002-11-03 00:24:07 +0000367 if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
368 /* <CR> pressed as only input, don't modify current
369 * location and move to next. "-" pressed will go back.
370 */
371 if (incrflag)
372 addr += nbytes ? -size : size;
373 nbytes = 1;
Simon Glassb26440f2014-04-10 20:01:31 -0600374 /* good enough to not time out */
375 bootretry_reset_cmd_timeout();
wdenkc6097192002-11-03 00:24:07 +0000376 }
377#ifdef CONFIG_BOOT_RETRY_TIME
378 else if (nbytes == -2) {
379 break; /* timed out, exit the command */
380 }
381#endif
382 else {
383 char *endp;
384 i = simple_strtoul(console_buffer, &endp, 16);
385 nbytes = endp - console_buffer;
386 if (nbytes) {
wdenkc6097192002-11-03 00:24:07 +0000387 /* good enough to not time out
388 */
Simon Glassb26440f2014-04-10 20:01:31 -0600389 bootretry_reset_cmd_timeout();
wdenkc6097192002-11-03 00:24:07 +0000390 pci_cfg_write (bdf, addr, size, i);
391 if (incrflag)
392 addr += size;
393 }
394 }
395 } while (nbytes);
396
397 return 0;
398}
399
400/* PCI Configuration Space access commands
401 *
402 * Syntax:
403 * pci display[.b, .w, .l] bus.device.function} [addr] [len]
404 * pci next[.b, .w, .l] bus.device.function [addr]
405 * pci modify[.b, .w, .l] bus.device.function [addr]
406 * pci write[.b, .w, .l] bus.device.function addr value
407 */
Kim Phillips088f1b12012-10-29 13:34:31 +0000408static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
wdenkc6097192002-11-03 00:24:07 +0000409{
410 ulong addr = 0, value = 0, size = 0;
411 pci_dev_t bdf = 0;
412 char cmd = 's';
413
414 if (argc > 1)
415 cmd = argv[1][0];
416
417 switch (cmd) {
418 case 'd': /* display */
419 case 'n': /* next */
420 case 'm': /* modify */
421 case 'w': /* write */
422 /* Check for a size specification. */
423 size = cmd_get_data_size(argv[1], 4);
424 if (argc > 3)
425 addr = simple_strtoul(argv[3], NULL, 16);
426 if (argc > 4)
427 value = simple_strtoul(argv[4], NULL, 16);
428 case 'h': /* header */
429 if (argc < 3)
430 goto usage;
431 if ((bdf = get_pci_dev(argv[2])) == -1)
432 return 1;
433 break;
John Schmoller96d61602010-10-22 00:20:23 -0500434#ifdef CONFIG_CMD_PCI_ENUM
435 case 'e':
436 break;
437#endif
wdenkc6097192002-11-03 00:24:07 +0000438 default: /* scan bus */
439 value = 1; /* short listing */
440 bdf = 0; /* bus number */
441 if (argc > 1) {
442 if (argv[argc-1][0] == 'l') {
443 value = 0;
444 argc--;
445 }
446 if (argc > 1)
447 bdf = simple_strtoul(argv[1], NULL, 16);
448 }
449 pciinfo(bdf, value);
450 return 0;
451 }
452
453 switch (argv[1][0]) {
454 case 'h': /* header */
455 pci_header_show(bdf);
456 return 0;
457 case 'd': /* display */
458 return pci_cfg_display(bdf, addr, size, value);
John Schmoller96d61602010-10-22 00:20:23 -0500459#ifdef CONFIG_CMD_PCI_ENUM
460 case 'e':
461 pci_init();
462 return 0;
463#endif
wdenkc6097192002-11-03 00:24:07 +0000464 case 'n': /* next */
465 if (argc < 4)
466 goto usage;
467 return pci_cfg_modify(bdf, addr, size, value, 0);
468 case 'm': /* modify */
469 if (argc < 4)
470 goto usage;
471 return pci_cfg_modify(bdf, addr, size, value, 1);
472 case 'w': /* write */
473 if (argc < 5)
474 goto usage;
475 return pci_cfg_write(bdf, addr, size, value);
476 }
477
478 return 1;
479 usage:
Simon Glass4c12eeb2011-12-10 08:44:01 +0000480 return CMD_RET_USAGE;
wdenkc6097192002-11-03 00:24:07 +0000481}
482
wdenk8bde7f72003-06-27 21:31:46 +0000483/***************************************************/
484
Kim Phillips088f1b12012-10-29 13:34:31 +0000485#ifdef CONFIG_SYS_LONGHELP
486static char pci_help_text[] =
wdenk8bde7f72003-06-27 21:31:46 +0000487 "[bus] [long]\n"
488 " - short or long list of PCI devices on bus 'bus'\n"
John Schmoller96d61602010-10-22 00:20:23 -0500489#ifdef CONFIG_CMD_PCI_ENUM
490 "pci enum\n"
491 " - re-enumerate PCI buses\n"
492#endif
wdenk8bde7f72003-06-27 21:31:46 +0000493 "pci header b.d.f\n"
494 " - show header of PCI device 'bus.device.function'\n"
495 "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
496 " - display PCI configuration space (CFG)\n"
497 "pci next[.b, .w, .l] b.d.f address\n"
498 " - modify, read and keep CFG address\n"
499 "pci modify[.b, .w, .l] b.d.f address\n"
500 " - modify, auto increment CFG address\n"
501 "pci write[.b, .w, .l] b.d.f address value\n"
Kim Phillips088f1b12012-10-29 13:34:31 +0000502 " - write to CFG address";
503#endif
504
505U_BOOT_CMD(
506 pci, 5, 1, do_pci,
507 "list and access PCI Configuration Space", pci_help_text
wdenk8bde7f72003-06-27 21:31:46 +0000508);