Masahiro Yamada | 6e7e929 | 2014-11-07 18:48:31 +0900 | [diff] [blame] | 1 | # |
| 2 | # USB Host Controller Drivers |
| 3 | # |
| 4 | comment "USB Host Controller Drivers" |
| 5 | |
Masahiro Yamada | 2b58e1b | 2016-08-01 00:16:34 +0900 | [diff] [blame] | 6 | config USB_HOST |
| 7 | bool |
| 8 | |
Masahiro Yamada | 6e7e929 | 2014-11-07 18:48:31 +0900 | [diff] [blame] | 9 | config USB_XHCI_HCD |
| 10 | bool "xHCI HCD (USB 3.0) support" |
Masahiro Yamada | 2b58e1b | 2016-08-01 00:16:34 +0900 | [diff] [blame] | 11 | select USB_HOST |
Masahiro Yamada | 6e7e929 | 2014-11-07 18:48:31 +0900 | [diff] [blame] | 12 | ---help--- |
| 13 | The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0 |
| 14 | "SuperSpeed" host controller hardware. |
| 15 | |
Masahiro Yamada | 6e7e929 | 2014-11-07 18:48:31 +0900 | [diff] [blame] | 16 | if USB_XHCI_HCD |
| 17 | |
Masahiro Yamada | 10db750 | 2016-06-04 07:35:04 +0900 | [diff] [blame] | 18 | config USB_XHCI_DWC3 |
| 19 | bool "DesignWare USB3 DRD Core Support" |
| 20 | help |
| 21 | Say Y or if your system has a Dual Role SuperSpeed |
| 22 | USB controller based on the DesignWare USB3 IP Core. |
| 23 | |
Neil Armstrong | ca7fdc8 | 2018-04-11 17:08:00 +0200 | [diff] [blame] | 24 | config USB_XHCI_DWC3_OF_SIMPLE |
| 25 | bool "DesignWare USB3 DRD Generic OF Simple Glue Layer" |
Jean-Jacques Hiblot | 103774b | 2018-04-12 10:41:10 +0200 | [diff] [blame] | 26 | depends on DM_USB |
Jean-Jacques Hiblot | cc73ba9 | 2018-04-12 10:41:11 +0200 | [diff] [blame] | 27 | default y if DRA7XX |
Neil Armstrong | ca7fdc8 | 2018-04-11 17:08:00 +0200 | [diff] [blame] | 28 | help |
| 29 | Support USB2/3 functionality in simple SoC integrations with |
| 30 | USB controller based on the DesignWare USB3 IP Core. |
| 31 | |
Stefan Roese | 81c1f6f | 2016-07-14 11:39:20 +0200 | [diff] [blame] | 32 | config USB_XHCI_MVEBU |
| 33 | bool "MVEBU USB 3.0 support" |
| 34 | default y |
| 35 | depends on ARCH_MVEBU |
Konstantin Porotchkin | 81192b7 | 2017-02-12 11:10:30 +0200 | [diff] [blame] | 36 | select DM_REGULATOR |
Stefan Roese | 81c1f6f | 2016-07-14 11:39:20 +0200 | [diff] [blame] | 37 | help |
| 38 | Choose this option to add support for USB 3.0 driver on mvebu |
| 39 | SoCs, which includes Armada8K, Armada3700 and other Armada |
| 40 | family SoCs. |
| 41 | |
Bin Meng | d7cde28 | 2017-07-19 21:50:08 +0800 | [diff] [blame] | 42 | config USB_XHCI_PCI |
| 43 | bool "Support for PCI-based xHCI USB controller" |
Bin Meng | 978f6a3 | 2017-07-19 21:51:07 +0800 | [diff] [blame] | 44 | depends on DM_USB |
Bin Meng | d7cde28 | 2017-07-19 21:50:08 +0800 | [diff] [blame] | 45 | default y if X86 |
| 46 | help |
| 47 | Enables support for the PCI-based xHCI controller. |
| 48 | |
Kever Yang | f7bb27a | 2016-09-21 11:35:42 +0800 | [diff] [blame] | 49 | config USB_XHCI_ROCKCHIP |
| 50 | bool "Support for Rockchip on-chip xHCI USB controller" |
| 51 | depends on ARCH_ROCKCHIP |
Meng Dongyang | e85f00a | 2017-06-28 19:22:39 +0800 | [diff] [blame] | 52 | depends on DM_REGULATOR |
| 53 | depends on DM_USB |
Kever Yang | f7bb27a | 2016-09-21 11:35:42 +0800 | [diff] [blame] | 54 | default y |
| 55 | help |
| 56 | Enables support for the on-chip xHCI controller on Rockchip SoCs. |
| 57 | |
Marek Vasut | e1cc60c | 2017-10-15 15:01:29 +0200 | [diff] [blame] | 58 | config USB_XHCI_RCAR |
| 59 | bool "Renesas RCar USB 3.0 support" |
| 60 | default y |
| 61 | depends on ARCH_RMOBILE |
| 62 | help |
| 63 | Choose this option to add support for USB 3.0 driver on Renesas |
| 64 | RCar Gen3 SoCs. |
| 65 | |
Patrice Chotard | 40d1a31 | 2017-09-05 11:04:24 +0200 | [diff] [blame] | 66 | config USB_XHCI_STI |
| 67 | bool "Support for STMicroelectronics STiH407 family on-chip xHCI USB controller" |
| 68 | depends on ARCH_STI |
| 69 | default y |
| 70 | help |
| 71 | Enables support for the on-chip xHCI controller on STMicroelectronics |
| 72 | STiH407 family SoCs. This is a driver for the dwc3 to provide the glue logic |
| 73 | to configure the controller. |
| 74 | |
Michal Simek | 63d7474 | 2016-12-21 14:18:31 +0100 | [diff] [blame] | 75 | config USB_XHCI_ZYNQMP |
| 76 | bool "Support for Xilinx ZynqMP on-chip xHCI USB controller" |
| 77 | depends on ARCH_ZYNQMP |
Michal Simek | d067624 | 2018-05-18 13:15:09 +0200 | [diff] [blame] | 78 | depends on DM_USB |
Michal Simek | 63d7474 | 2016-12-21 14:18:31 +0100 | [diff] [blame] | 79 | help |
| 80 | Enables support for the on-chip xHCI controller on Xilinx ZynqMP SoCs. |
| 81 | |
Uri Mashiach | ef3f3b8 | 2017-02-23 15:39:36 +0200 | [diff] [blame] | 82 | config USB_XHCI_DRA7XX_INDEX |
| 83 | int "DRA7XX xHCI USB index" |
| 84 | range 0 1 |
| 85 | default 0 |
| 86 | depends on DRA7XX |
| 87 | help |
| 88 | Select the DRA7XX xHCI USB index. |
| 89 | Current supported values: 0, 1. |
| 90 | |
Ran Wang | 420b0eb | 2017-10-23 10:09:22 +0800 | [diff] [blame] | 91 | config USB_XHCI_FSL |
| 92 | bool "Support for NXP Layerscape on-chip xHCI USB controller" |
| 93 | default y if ARCH_LS1021A || FSL_LSCH3 || FSL_LSCH2 |
| 94 | depends on !SPL_NO_USB |
| 95 | help |
| 96 | Enables support for the on-chip xHCI controller on NXP Layerscape SoCs. |
Masahiro Yamada | 93cb824 | 2016-08-01 00:16:32 +0900 | [diff] [blame] | 97 | endif # USB_XHCI_HCD |
Alexey Brodkin | fee331f | 2015-12-14 17:18:50 +0300 | [diff] [blame] | 98 | |
Masahiro Yamada | 6e7e929 | 2014-11-07 18:48:31 +0900 | [diff] [blame] | 99 | config USB_EHCI_HCD |
| 100 | bool "EHCI HCD (USB 2.0) support" |
Tom Rini | 64d6ac5 | 2017-05-12 22:33:28 -0400 | [diff] [blame] | 101 | default y if ARCH_MX5 || ARCH_MX6 |
Masahiro Yamada | 2b58e1b | 2016-08-01 00:16:34 +0900 | [diff] [blame] | 102 | select USB_HOST |
Masahiro Yamada | 6e7e929 | 2014-11-07 18:48:31 +0900 | [diff] [blame] | 103 | ---help--- |
| 104 | The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0 |
| 105 | "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware. |
| 106 | If your USB host controller supports USB 2.0, you will likely want to |
| 107 | configure this Host Controller Driver. |
| 108 | |
| 109 | EHCI controllers are packaged with "companion" host controllers (OHCI |
| 110 | or UHCI) to handle USB 1.1 devices connected to root hub ports. Ports |
| 111 | will connect to EHCI if the device is high speed, otherwise they |
| 112 | connect to a companion controller. If you configure EHCI, you should |
| 113 | probably configure the OHCI (for NEC and some other vendors) USB Host |
| 114 | Controller Driver or UHCI (for Via motherboards) Host Controller |
| 115 | Driver too. |
| 116 | |
| 117 | You may want to read <file:Documentation/usb/ehci.txt>. |
| 118 | |
Masahiro Yamada | 6e7e929 | 2014-11-07 18:48:31 +0900 | [diff] [blame] | 119 | if USB_EHCI_HCD |
| 120 | |
Wenyou Yang | 17b68b5 | 2016-08-05 08:57:35 +0800 | [diff] [blame] | 121 | config USB_EHCI_ATMEL |
| 122 | bool "Support for Atmel on-chip EHCI USB controller" |
| 123 | depends on ARCH_AT91 |
| 124 | default y |
| 125 | ---help--- |
| 126 | Enables support for the on-chip EHCI controller on Atmel chips. |
| 127 | |
Stefan Roese | cd48225 | 2015-09-01 11:39:44 +0200 | [diff] [blame] | 128 | config USB_EHCI_MARVELL |
Tom Rini | 80f1f32 | 2017-05-12 22:33:29 -0400 | [diff] [blame] | 129 | bool "Support for Marvell on-chip EHCI USB controller" |
| 130 | depends on ARCH_MVEBU || KIRKWOOD || ORION5X |
Stefan Roese | cd48225 | 2015-09-01 11:39:44 +0200 | [diff] [blame] | 131 | default y |
| 132 | ---help--- |
| 133 | Enables support for the on-chip EHCI controller on MVEBU SoCs. |
| 134 | |
Nikita Kiryanov | 919e802 | 2015-07-23 17:19:35 +0300 | [diff] [blame] | 135 | config USB_EHCI_MX6 |
| 136 | bool "Support for i.MX6 on-chip EHCI USB controller" |
| 137 | depends on ARCH_MX6 |
| 138 | default y |
| 139 | ---help--- |
| 140 | Enables support for the on-chip EHCI controller on i.MX6 SoCs. |
| 141 | |
Stefan Agner | 2deebe2 | 2016-07-13 00:25:36 -0700 | [diff] [blame] | 142 | config USB_EHCI_MX7 |
| 143 | bool "Support for i.MX7 on-chip EHCI USB controller" |
| 144 | depends on ARCH_MX7 |
| 145 | default y |
| 146 | ---help--- |
| 147 | Enables support for the on-chip EHCI controller on i.MX7 SoCs. |
| 148 | |
Tom Rini | 1d1ab61 | 2017-05-12 22:33:30 -0400 | [diff] [blame] | 149 | config USB_EHCI_OMAP |
| 150 | bool "Support for OMAP3+ on-chip EHCI USB controller" |
| 151 | depends on ARCH_OMAP2PLUS |
| 152 | default y |
| 153 | ---help--- |
| 154 | Enables support for the on-chip EHCI controller on OMAP3 and later |
| 155 | SoCs. |
| 156 | |
Stefan Agner | c448309 | 2016-07-13 00:25:38 -0700 | [diff] [blame] | 157 | if USB_EHCI_MX7 |
| 158 | |
| 159 | config MXC_USB_OTG_HACTIVE |
| 160 | bool "USB Power pin high active" |
| 161 | ---help--- |
| 162 | Set the USB Power pin polarity to be high active (PWR_POL) |
| 163 | |
| 164 | endif |
| 165 | |
Mateusz Kulikowski | 5a82211 | 2016-03-31 23:12:26 +0200 | [diff] [blame] | 166 | config USB_EHCI_MSM |
| 167 | bool "Support for Qualcomm on-chip EHCI USB controller" |
| 168 | depends on DM_USB |
| 169 | select USB_ULPI_VIEWPORT |
Ramon Fried | 0ac0b6e | 2018-09-21 13:35:50 +0300 | [diff] [blame] | 170 | select MSM8916_USB_PHY |
Mateusz Kulikowski | 5a82211 | 2016-03-31 23:12:26 +0200 | [diff] [blame] | 171 | default n |
| 172 | ---help--- |
| 173 | Enables support for the on-chip EHCI controller on Qualcomm |
| 174 | Snapdragon SoCs. |
Mateusz Kulikowski | 5a82211 | 2016-03-31 23:12:26 +0200 | [diff] [blame] | 175 | |
Bin Meng | a11a5b8 | 2017-08-09 00:21:54 -0700 | [diff] [blame] | 176 | config USB_EHCI_PCI |
| 177 | bool "Support for PCI-based EHCI USB controller" |
| 178 | default y if X86 |
| 179 | help |
| 180 | Enables support for the PCI-based EHCI controller. |
| 181 | |
Siva Durga Prasad Paladugu | 2cdc778 | 2016-07-22 14:51:51 +0530 | [diff] [blame] | 182 | config USB_EHCI_ZYNQ |
| 183 | bool "Support for Xilinx Zynq on-chip EHCI USB controller" |
| 184 | depends on ARCH_ZYNQ |
| 185 | default y |
| 186 | ---help--- |
| 187 | Enable support for Zynq on-chip EHCI USB controller |
| 188 | |
Alexey Brodkin | 90fbb28 | 2015-12-02 12:32:02 +0300 | [diff] [blame] | 189 | config USB_EHCI_GENERIC |
| 190 | bool "Support for generic EHCI USB controller" |
| 191 | depends on OF_CONTROL |
| 192 | depends on DM_USB |
Jagan Teki | 29d280c | 2018-12-22 18:18:10 +0530 | [diff] [blame] | 193 | default ARCH_SUNXI |
Alexey Brodkin | 90fbb28 | 2015-12-02 12:32:02 +0300 | [diff] [blame] | 194 | default n |
| 195 | ---help--- |
| 196 | Enables support for generic EHCI controller. |
| 197 | |
Ran Wang | 91f4fb9 | 2017-12-20 10:34:20 +0800 | [diff] [blame] | 198 | config USB_EHCI_FSL |
| 199 | bool "Support for FSL on-chip EHCI USB controller" |
| 200 | default n |
| 201 | select CONFIG_EHCI_HCD_INIT_AFTER_RESET |
| 202 | ---help--- |
| 203 | Enables support for the on-chip EHCI controller on FSL chips. |
Masahiro Yamada | 93cb824 | 2016-08-01 00:16:32 +0900 | [diff] [blame] | 204 | endif # USB_EHCI_HCD |
| 205 | |
| 206 | config USB_OHCI_HCD |
| 207 | bool "OHCI HCD (USB 1.1) support" |
| 208 | ---help--- |
| 209 | The Open Host Controller Interface (OHCI) is a standard for accessing |
| 210 | USB 1.1 host controller hardware. It does more in hardware than Intel's |
| 211 | UHCI specification. If your USB host controller follows the OHCI spec, |
| 212 | say Y. On most non-x86 systems, and on x86 hardware that's not using a |
| 213 | USB controller from Intel or VIA, this is appropriate. If your host |
| 214 | controller doesn't use PCI, this is probably appropriate. For a PCI |
| 215 | based system where you're not sure, the "lspci -v" entry will list the |
| 216 | right "prog-if" for your USB controller(s): EHCI, OHCI, or UHCI. |
| 217 | |
| 218 | if USB_OHCI_HCD |
| 219 | |
| 220 | config USB_OHCI_GENERIC |
| 221 | bool "Support for generic OHCI USB controller" |
| 222 | depends on OF_CONTROL |
| 223 | depends on DM_USB |
Jagan Teki | 29d280c | 2018-12-22 18:18:10 +0530 | [diff] [blame] | 224 | default ARCH_SUNXI |
Masahiro Yamada | 2b58e1b | 2016-08-01 00:16:34 +0900 | [diff] [blame] | 225 | select USB_HOST |
Masahiro Yamada | 93cb824 | 2016-08-01 00:16:32 +0900 | [diff] [blame] | 226 | ---help--- |
| 227 | Enables support for generic OHCI controller. |
| 228 | |
| 229 | endif # USB_OHCI_HCD |
Masahiro Yamada | 96d8284 | 2016-08-01 00:16:33 +0900 | [diff] [blame] | 230 | |
| 231 | config USB_UHCI_HCD |
| 232 | bool "UHCI HCD (most Intel and VIA) support" |
Masahiro Yamada | 2b58e1b | 2016-08-01 00:16:34 +0900 | [diff] [blame] | 233 | select USB_HOST |
Masahiro Yamada | 96d8284 | 2016-08-01 00:16:33 +0900 | [diff] [blame] | 234 | ---help--- |
| 235 | The Universal Host Controller Interface is a standard by Intel for |
| 236 | accessing the USB hardware in the PC (which is also called the USB |
| 237 | host controller). If your USB host controller conforms to this |
| 238 | standard, you may want to say Y, but see below. All recent boards |
| 239 | with Intel PCI chipsets (like intel 430TX, 440FX, 440LX, 440BX, |
| 240 | i810, i820) conform to this standard. Also all VIA PCI chipsets |
| 241 | (like VIA VP2, VP3, MVP3, Apollo Pro, Apollo Pro II or Apollo Pro |
| 242 | 133) and LEON/GRLIB SoCs with the GRUSBHC controller. |
| 243 | If unsure, say Y. |
| 244 | |
| 245 | if USB_UHCI_HCD |
| 246 | |
| 247 | endif # USB_UHCI_HCD |
Philipp Tomsich | 4ac72f5 | 2017-07-03 18:30:06 +0200 | [diff] [blame] | 248 | |
| 249 | config USB_DWC2 |
| 250 | bool "DesignWare USB2 Core support" |
| 251 | select USB_HOST |
| 252 | ---help--- |
| 253 | The DesignWare USB 2.0 controller is compliant with the |
| 254 | USB-Implementers Forum (USB-IF) USB 2.0 specifications. |
| 255 | Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low-Speed (1.5 Mbps) |
| 256 | operation is compliant to the controller Supplement. If you want to |
| 257 | enable this controller in host mode, say Y. |
Alexey Brodkin | 42637fd | 2018-02-28 16:16:58 +0300 | [diff] [blame] | 258 | |
| 259 | if USB_DWC2 |
| 260 | config USB_DWC2_BUFFER_SIZE |
| 261 | int "Data buffer size in kB" |
| 262 | default 64 |
| 263 | ---help--- |
| 264 | By default 64 kB buffer is used but if amount of RAM avaialble on |
| 265 | the target is not enough to accommodate allocation of buffer of |
| 266 | that size it is possible to shrink it. Smaller sizes should be fine |
| 267 | because larger transactions could be split in smaller ones. |
| 268 | |
| 269 | endif # USB_DWC2 |