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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +01002/*
3 * Copyright (C) 2005-2006 Atmel Corporation
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +01004 */
5#ifndef __DRIVERS_MACB_H__
6#define __DRIVERS_MACB_H__
7
8/* MACB register offsets */
9#define MACB_NCR 0x0000
10#define MACB_NCFGR 0x0004
11#define MACB_NSR 0x0008
Bo Shend256be22013-04-24 15:59:28 +080012#define GEM_UR 0x000c
Wilson Lee4bf56912017-08-22 20:25:07 -070013#define MACB_DMACFG 0x0010
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010014#define MACB_TSR 0x0014
15#define MACB_RBQP 0x0018
16#define MACB_TBQP 0x001c
17#define MACB_RSR 0x0020
18#define MACB_ISR 0x0024
19#define MACB_IER 0x0028
20#define MACB_IDR 0x002c
21#define MACB_IMR 0x0030
22#define MACB_MAN 0x0034
23#define MACB_PTR 0x0038
24#define MACB_PFR 0x003c
25#define MACB_FTO 0x0040
26#define MACB_SCF 0x0044
27#define MACB_MCF 0x0048
28#define MACB_FRO 0x004c
29#define MACB_FCSE 0x0050
30#define MACB_ALE 0x0054
31#define MACB_DTF 0x0058
32#define MACB_LCOL 0x005c
33#define MACB_EXCOL 0x0060
34#define MACB_TUND 0x0064
35#define MACB_CSE 0x0068
36#define MACB_RRE 0x006c
37#define MACB_ROVR 0x0070
38#define MACB_RSE 0x0074
39#define MACB_ELE 0x0078
40#define MACB_RJA 0x007c
41#define MACB_USF 0x0080
42#define MACB_STE 0x0084
43#define MACB_RLE 0x0088
44#define MACB_TPF 0x008c
45#define MACB_HRB 0x0090
46#define MACB_HRT 0x0094
47#define MACB_SA1B 0x0098
48#define MACB_SA1T 0x009c
49#define MACB_SA2B 0x00a0
50#define MACB_SA2T 0x00a4
51#define MACB_SA3B 0x00a8
52#define MACB_SA3T 0x00ac
53#define MACB_SA4B 0x00b0
54#define MACB_SA4T 0x00b4
55#define MACB_TID 0x00b8
56#define MACB_TPQ 0x00bc
57#define MACB_USRIO 0x00c0
58#define MACB_WOL 0x00c4
Bo Shend256be22013-04-24 15:59:28 +080059#define MACB_MID 0x00fc
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010060
Bo Shen32e4f6b2013-09-18 15:07:44 +080061/* GEM specific register offsets */
62#define GEM_DCFG1 0x0280
Wu, Joshade4ea42015-06-03 16:45:44 +080063#define GEM_DCFG6 0x0294
64
65#define MACB_MAX_QUEUES 8
66
67/* GEM specific multi queues register offset */
68/* hw_q can be 0~7 */
69#define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
Bo Shen32e4f6b2013-09-18 15:07:44 +080070
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010071/* Bitfields in NCR */
72#define MACB_LB_OFFSET 0
73#define MACB_LB_SIZE 1
74#define MACB_LLB_OFFSET 1
75#define MACB_LLB_SIZE 1
76#define MACB_RE_OFFSET 2
77#define MACB_RE_SIZE 1
78#define MACB_TE_OFFSET 3
79#define MACB_TE_SIZE 1
80#define MACB_MPE_OFFSET 4
81#define MACB_MPE_SIZE 1
82#define MACB_CLRSTAT_OFFSET 5
83#define MACB_CLRSTAT_SIZE 1
84#define MACB_INCSTAT_OFFSET 6
85#define MACB_INCSTAT_SIZE 1
86#define MACB_WESTAT_OFFSET 7
87#define MACB_WESTAT_SIZE 1
88#define MACB_BP_OFFSET 8
89#define MACB_BP_SIZE 1
90#define MACB_TSTART_OFFSET 9
91#define MACB_TSTART_SIZE 1
92#define MACB_THALT_OFFSET 10
93#define MACB_THALT_SIZE 1
94#define MACB_NCR_TPF_OFFSET 11
95#define MACB_NCR_TPF_SIZE 1
96#define MACB_TZQ_OFFSET 12
97#define MACB_TZQ_SIZE 1
98
99/* Bitfields in NCFGR */
100#define MACB_SPD_OFFSET 0
101#define MACB_SPD_SIZE 1
102#define MACB_FD_OFFSET 1
103#define MACB_FD_SIZE 1
104#define MACB_BIT_RATE_OFFSET 2
105#define MACB_BIT_RATE_SIZE 1
106#define MACB_JFRAME_OFFSET 3
107#define MACB_JFRAME_SIZE 1
108#define MACB_CAF_OFFSET 4
109#define MACB_CAF_SIZE 1
110#define MACB_NBC_OFFSET 5
111#define MACB_NBC_SIZE 1
112#define MACB_NCFGR_MTI_OFFSET 6
113#define MACB_NCFGR_MTI_SIZE 1
114#define MACB_UNI_OFFSET 7
115#define MACB_UNI_SIZE 1
116#define MACB_BIG_OFFSET 8
117#define MACB_BIG_SIZE 1
118#define MACB_EAE_OFFSET 9
119#define MACB_EAE_SIZE 1
120#define MACB_CLK_OFFSET 10
121#define MACB_CLK_SIZE 2
122#define MACB_RTY_OFFSET 12
123#define MACB_RTY_SIZE 1
124#define MACB_PAE_OFFSET 13
125#define MACB_PAE_SIZE 1
126#define MACB_RBOF_OFFSET 14
127#define MACB_RBOF_SIZE 2
128#define MACB_RLCE_OFFSET 16
129#define MACB_RLCE_SIZE 1
130#define MACB_DRFCS_OFFSET 17
131#define MACB_DRFCS_SIZE 1
132#define MACB_EFRHD_OFFSET 18
133#define MACB_EFRHD_SIZE 1
134#define MACB_IRXFCS_OFFSET 19
135#define MACB_IRXFCS_SIZE 1
136
Bo Shend256be22013-04-24 15:59:28 +0800137#define GEM_GBE_OFFSET 10
138#define GEM_GBE_SIZE 1
139#define GEM_CLK_OFFSET 18
140#define GEM_CLK_SIZE 3
141#define GEM_DBW_OFFSET 21
142#define GEM_DBW_SIZE 2
143
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100144/* Bitfields in NSR */
145#define MACB_NSR_LINK_OFFSET 0
146#define MACB_NSR_LINK_SIZE 1
147#define MACB_MDIO_OFFSET 1
148#define MACB_MDIO_SIZE 1
149#define MACB_IDLE_OFFSET 2
150#define MACB_IDLE_SIZE 1
151
Bo Shend256be22013-04-24 15:59:28 +0800152/* Bitfields in UR */
153#define GEM_RGMII_OFFSET 0
154#define GEM_RGMII_SIZE 1
155
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100156/* Bitfields in TSR */
157#define MACB_UBR_OFFSET 0
158#define MACB_UBR_SIZE 1
159#define MACB_COL_OFFSET 1
160#define MACB_COL_SIZE 1
161#define MACB_TSR_RLE_OFFSET 2
162#define MACB_TSR_RLE_SIZE 1
163#define MACB_TGO_OFFSET 3
164#define MACB_TGO_SIZE 1
165#define MACB_BEX_OFFSET 4
166#define MACB_BEX_SIZE 1
167#define MACB_COMP_OFFSET 5
168#define MACB_COMP_SIZE 1
169#define MACB_UND_OFFSET 6
170#define MACB_UND_SIZE 1
171
172/* Bitfields in RSR */
173#define MACB_BNA_OFFSET 0
174#define MACB_BNA_SIZE 1
175#define MACB_REC_OFFSET 1
176#define MACB_REC_SIZE 1
177#define MACB_OVR_OFFSET 2
178#define MACB_OVR_SIZE 1
179
180/* Bitfields in ISR/IER/IDR/IMR */
181#define MACB_MFD_OFFSET 0
182#define MACB_MFD_SIZE 1
183#define MACB_RCOMP_OFFSET 1
184#define MACB_RCOMP_SIZE 1
185#define MACB_RXUBR_OFFSET 2
186#define MACB_RXUBR_SIZE 1
187#define MACB_TXUBR_OFFSET 3
188#define MACB_TXUBR_SIZE 1
189#define MACB_ISR_TUND_OFFSET 4
190#define MACB_ISR_TUND_SIZE 1
191#define MACB_ISR_RLE_OFFSET 5
192#define MACB_ISR_RLE_SIZE 1
193#define MACB_TXERR_OFFSET 6
194#define MACB_TXERR_SIZE 1
195#define MACB_TCOMP_OFFSET 7
196#define MACB_TCOMP_SIZE 1
197#define MACB_ISR_LINK_OFFSET 9
198#define MACB_ISR_LINK_SIZE 1
199#define MACB_ISR_ROVR_OFFSET 10
200#define MACB_ISR_ROVR_SIZE 1
201#define MACB_HRESP_OFFSET 11
202#define MACB_HRESP_SIZE 1
203#define MACB_PFR_OFFSET 12
204#define MACB_PFR_SIZE 1
205#define MACB_PTZ_OFFSET 13
206#define MACB_PTZ_SIZE 1
207
208/* Bitfields in MAN */
209#define MACB_DATA_OFFSET 0
210#define MACB_DATA_SIZE 16
211#define MACB_CODE_OFFSET 16
212#define MACB_CODE_SIZE 2
213#define MACB_REGA_OFFSET 18
214#define MACB_REGA_SIZE 5
215#define MACB_PHYA_OFFSET 23
216#define MACB_PHYA_SIZE 5
217#define MACB_RW_OFFSET 28
218#define MACB_RW_SIZE 2
219#define MACB_SOF_OFFSET 30
220#define MACB_SOF_SIZE 2
221
222/* Bitfields in USRIO */
223#define MACB_MII_OFFSET 0
224#define MACB_MII_SIZE 1
225#define MACB_EAM_OFFSET 1
226#define MACB_EAM_SIZE 1
227#define MACB_TX_PAUSE_OFFSET 2
228#define MACB_TX_PAUSE_SIZE 1
229#define MACB_TX_PAUSE_ZERO_OFFSET 3
230#define MACB_TX_PAUSE_ZERO_SIZE 1
231
Stelian Pop7263ef12008-01-03 21:15:56 +0000232/* Bitfields in USRIO (AT91) */
233#define MACB_RMII_OFFSET 0
234#define MACB_RMII_SIZE 1
235#define MACB_CLKEN_OFFSET 1
236#define MACB_CLKEN_SIZE 1
237
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100238/* Bitfields in WOL */
239#define MACB_IP_OFFSET 0
240#define MACB_IP_SIZE 16
241#define MACB_MAG_OFFSET 16
242#define MACB_MAG_SIZE 1
243#define MACB_ARP_OFFSET 17
244#define MACB_ARP_SIZE 1
245#define MACB_SA1_OFFSET 18
246#define MACB_SA1_SIZE 1
247#define MACB_WOL_MTI_OFFSET 19
248#define MACB_WOL_MTI_SIZE 1
249
Bo Shend256be22013-04-24 15:59:28 +0800250/* Bitfields in MID */
251#define MACB_IDNUM_OFFSET 16
252#define MACB_IDNUM_SIZE 16
253
254/* Bitfields in DCFG1 */
Bo Shen32e4f6b2013-09-18 15:07:44 +0800255#define GEM_DBWDEF_OFFSET 25
256#define GEM_DBWDEF_SIZE 3
257
258/* constants for data bus width */
259#define GEM_DBW32 0
260#define GEM_DBW64 1
261#define GEM_DBW128 2
262
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100263/* Constants for CLK */
264#define MACB_CLK_DIV8 0
265#define MACB_CLK_DIV16 1
266#define MACB_CLK_DIV32 2
267#define MACB_CLK_DIV64 3
268
Bo Shend256be22013-04-24 15:59:28 +0800269/* GEM specific constants for CLK */
270#define GEM_CLK_DIV8 0
271#define GEM_CLK_DIV16 1
272#define GEM_CLK_DIV32 2
273#define GEM_CLK_DIV48 3
274#define GEM_CLK_DIV64 4
275#define GEM_CLK_DIV96 5
276
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100277/* Constants for MAN register */
278#define MACB_MAN_SOF 1
279#define MACB_MAN_WRITE 1
280#define MACB_MAN_READ 2
281#define MACB_MAN_CODE 2
282
283/* Bit manipulation macros */
284#define MACB_BIT(name) \
285 (1 << MACB_##name##_OFFSET)
Bo Shend256be22013-04-24 15:59:28 +0800286#define MACB_BF(name, value) \
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100287 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \
288 << MACB_##name##_OFFSET)
Bo Shend256be22013-04-24 15:59:28 +0800289#define MACB_BFEXT(name, value)\
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100290 (((value) >> MACB_##name##_OFFSET) \
291 & ((1 << MACB_##name##_SIZE) - 1))
Bo Shend256be22013-04-24 15:59:28 +0800292#define MACB_BFINS(name, value, old) \
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100293 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
294 << MACB_##name##_OFFSET)) \
Bo Shend256be22013-04-24 15:59:28 +0800295 | MACB_BF(name, value))
296
297#define GEM_BIT(name) \
298 (1 << GEM_##name##_OFFSET)
299#define GEM_BF(name, value) \
300 (((value) & ((1 << GEM_##name##_SIZE) - 1)) \
301 << GEM_##name##_OFFSET)
302#define GEM_BFEXT(name, value)\
303 (((value) >> GEM_##name##_OFFSET) \
304 & ((1 << GEM_##name##_SIZE) - 1))
305#define GEM_BFINS(name, value, old) \
306 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \
307 << GEM_##name##_OFFSET)) \
308 | GEM_BF(name, value))
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100309
310/* Register access macros */
Bo Shend256be22013-04-24 15:59:28 +0800311#define macb_readl(port, reg) \
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100312 readl((port)->regs + MACB_##reg)
Bo Shend256be22013-04-24 15:59:28 +0800313#define macb_writel(port, reg, value) \
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100314 writel((value), (port)->regs + MACB_##reg)
Bo Shend256be22013-04-24 15:59:28 +0800315#define gem_readl(port, reg) \
316 readl((port)->regs + GEM_##reg)
317#define gem_writel(port, reg, value) \
318 writel((value), (port)->regs + GEM_##reg)
Wu, Joshade4ea42015-06-03 16:45:44 +0800319#define gem_writel_queue_TBQP(port, value, queue_num) \
320 writel((value), (port)->regs + GEM_TBQP(queue_num))
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100321
322#endif /* __DRIVERS_MACB_H__ */