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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Hideyuki Sano1a31ca42012-06-27 10:35:35 +09002/*
3 * Configuation settings for the bonito board
4 *
5 * Copyright (C) 2012 Renesas Solutions Corp.
Hideyuki Sano1a31ca42012-06-27 10:35:35 +09006 */
7
8#ifndef __ARMADILLO_800EVA_H
9#define __ARMADILLO_800EVA_H
10
Hideyuki Sano1a31ca42012-06-27 10:35:35 +090011#define CONFIG_SH_GPIO_PFC
12
13#include <asm/arch/rmobile.h>
14
Hideyuki Sano1a31ca42012-06-27 10:35:35 +090015#define BOARD_LATE_INIT
16
Hideyuki Sano1a31ca42012-06-27 10:35:35 +090017#undef CONFIG_SHOW_BOOT_PROGRESS
18
19#define CONFIG_ARCH_CPU_INIT
Hideyuki Sano1a31ca42012-06-27 10:35:35 +090020#define CONFIG_TMU_TIMER
21#define CONFIG_SYS_DCACHE_OFF
22
23/* STACK */
24#define CONFIG_SYS_INIT_SP_ADDR 0xE8083000
25#define STACK_AREA_SIZE 0xC000
26#define LOW_LEVEL_MERAM_STACK \
27 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
28
29/* MEMORY */
30#define ARMADILLO_800EVA_SDRAM_BASE 0x40000000
31#define ARMADILLO_800EVA_SDRAM_SIZE (512 * 1024 * 1024)
32
Hideyuki Sano1a31ca42012-06-27 10:35:35 +090033#define CONFIG_SYS_PBSIZE 256
Hideyuki Sano1a31ca42012-06-27 10:35:35 +090034#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
35
36/* SCIF */
Hideyuki Sano1a31ca42012-06-27 10:35:35 +090037#define CONFIG_CONS_SCIF1
38#define SCIF0_BASE 0xe6c40000
39#define SCIF1_BASE 0xe6c50000
40#define SCIF2_BASE 0xe6c60000
41#define SCIF4_BASE 0xe6c80000
42#define CONFIG_SCIF_A
Hideyuki Sano1a31ca42012-06-27 10:35:35 +090043
44#define CONFIG_SYS_MEMTEST_START (ARMADILLO_800EVA_SDRAM_BASE)
45#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
46 504 * 1024 * 1024)
Hideyuki Sano1a31ca42012-06-27 10:35:35 +090047#undef CONFIG_SYS_MEMTEST_SCRATCH
48#undef CONFIG_SYS_LOADS_BAUD_CHANGE
49
50#define CONFIG_SYS_SDRAM_BASE (ARMADILLO_800EVA_SDRAM_BASE)
51#define CONFIG_SYS_SDRAM_SIZE (ARMADILLO_800EVA_SDRAM_SIZE)
52#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
53 64 * 1024 * 1024)
54#define CONFIG_NR_DRAM_BANKS 1
55
56#define CONFIG_SYS_MONITOR_BASE 0x00000000
57#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
58#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
Hideyuki Sano1a31ca42012-06-27 10:35:35 +090059#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
Hideyuki Sano1a31ca42012-06-27 10:35:35 +090060
61/* FLASH */
Hideyuki Sano1a31ca42012-06-27 10:35:35 +090062#define CONFIG_SYS_FLASH_CFI
63#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
64#define CONFIG_SYS_FLASH_BASE 0x00000000
65#define CONFIG_SYS_MAX_FLASH_SECT 512
66#define CONFIG_SYS_MAX_FLASH_BANKS 1
67#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
68
69#define CONFIG_SYS_FLASH_ERASE_TOUT 3000
70#define CONFIG_SYS_FLASH_WRITE_TOUT 3000
71#define CONFIG_SYS_FLASH_LOCK_TOUT 3000
72#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000
73
74/* ENV setting */
Hideyuki Sano1a31ca42012-06-27 10:35:35 +090075#define CONFIG_ENV_OVERWRITE 1
76#define CONFIG_ENV_SECT_SIZE (128 * 1024)
77#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
78 CONFIG_SYS_MONITOR_LEN)
79#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
80#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
81#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
82
83/* SH Ether */
Hideyuki Sano1a31ca42012-06-27 10:35:35 +090084#define CONFIG_SH_ETHER_USE_PORT 0
85#define CONFIG_SH_ETHER_PHY_ADDR 0x0
86#define CONFIG_SH_ETHER_BASE_ADDR 0xe9a00000
87#define CONFIG_SH_ETHER_SH7734_MII (0x01)
88#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
Hideyuki Sano1a31ca42012-06-27 10:35:35 +090089#define CONFIG_PHY_SMSC
90#define CONFIG_BITBANGMII
91#define CONFIG_BITBANGMII_MULTI
92
93/* Board Clock */
94#define CONFIG_SYS_CLK_FREQ 50000000
Nobuhiro Iwamatsu717ceb62013-09-30 10:30:41 +090095#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
96#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Hideyuki Sano1a31ca42012-06-27 10:35:35 +090097#define CONFIG_SYS_TMU_CLK_DIV 4
Hideyuki Sano1a31ca42012-06-27 10:35:35 +090098
99#endif /* __ARMADILLO_800EVA_H */