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Wolfgang Denkde26ef92009-05-16 10:47:38 +02001/*
2 * (C) Copyright 2007-2009 DENX Software Engineering
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Wolfgang Denkde26ef92009-05-16 10:47:38 +02005 */
6
7#include <common.h>
8#include <command.h>
Wolfgang Denk843efb12009-05-16 10:47:43 +02009#include <asm/io.h>
Wolfgang Denkde26ef92009-05-16 10:47:38 +020010#include <asm/processor.h>
11
12DECLARE_GLOBAL_DATA_PTR;
13
14#if defined(CONFIG_IDE_RESET)
15
Wolfgang Denk843efb12009-05-16 10:47:43 +020016void ide_set_reset (int idereset)
17{
18 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
19 debug ("ide_set_reset(%d)\n", idereset);
20
21 if (idereset) {
22 out_be32(&im->pata.pata_ata_control, 0);
23 } else {
24 out_be32(&im->pata.pata_ata_control, FSL_ATA_CTRL_ATA_RST_B);
25 }
26 udelay(100);
27}
28
Wolfgang Denkde26ef92009-05-16 10:47:38 +020029void init_ide_reset (void)
30{
Wolfgang Denkde26ef92009-05-16 10:47:38 +020031 debug ("init_ide_reset\n");
32
33 /*
34 * Clear the reset bit to reset the interface
35 * cf. RefMan MPC5121EE: 28.4.1 Resetting the ATA Bus
36 */
Wolfgang Denk843efb12009-05-16 10:47:43 +020037 ide_set_reset(1);
38
Wolfgang Denkde26ef92009-05-16 10:47:38 +020039 /* Assert the reset bit to enable the interface */
Wolfgang Denk843efb12009-05-16 10:47:43 +020040 ide_set_reset(0);
Wolfgang Denkde26ef92009-05-16 10:47:38 +020041
Wolfgang Denkde26ef92009-05-16 10:47:38 +020042}
43
44#define CALC_TIMING(t) (t + period - 1) / period
45
46int ide_preinit (void)
47{
Wolfgang Denk843efb12009-05-16 10:47:43 +020048 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
Wolfgang Denkde26ef92009-05-16 10:47:38 +020049 long t;
50 const struct {
51 short t0;
52 short t1;
53 short t2_8;
54 short t2_16;
55 short t2i;
56 short t4;
57 short t9;
58 short tA;
59 } pio_specs = {
60 .t0 = 600,
61 .t1 = 70,
62 .t2_8 = 290,
63 .t2_16 = 165,
64 .t2i = 0,
65 .t4 = 30,
66 .t9 = 20,
67 .tA = 50,
68 };
69 union {
70 u32 config;
71 struct {
72 u8 field1;
73 u8 field2;
74 u8 field3;
75 u8 field4;
76 }bytes;
Wolfgang Denk843efb12009-05-16 10:47:43 +020077 } cfg;
Wolfgang Denkde26ef92009-05-16 10:47:38 +020078
79 debug ("IDE preinit using PATA peripheral at IMMR-ADDR %08x\n",
Wolfgang Denk843efb12009-05-16 10:47:43 +020080 (u32)&im->pata);
Wolfgang Denkde26ef92009-05-16 10:47:38 +020081
82 /* Set the reset bit to 1 to enable the interface */
Wolfgang Denk843efb12009-05-16 10:47:43 +020083 ide_set_reset(0);
Wolfgang Denkde26ef92009-05-16 10:47:38 +020084
85 /* Init timings : we use PIO mode 0 timings */
Simon Glassfefb0982012-12-13 20:48:54 +000086 t = 1000000000 / gd->arch.ips_clk; /* period in ns */
Wolfgang Denkde26ef92009-05-16 10:47:38 +020087 cfg.bytes.field1 = 3;
88 cfg.bytes.field2 = 3;
89 cfg.bytes.field3 = (pio_specs.t1 + t) / t;
90 cfg.bytes.field4 = (pio_specs.t2_8 + t) / t;
91
Wolfgang Denk843efb12009-05-16 10:47:43 +020092 out_be32(&im->pata.pata_time1, cfg.config);
Wolfgang Denkde26ef92009-05-16 10:47:38 +020093
94 cfg.bytes.field1 = (pio_specs.t2_8 + t) / t;
95 cfg.bytes.field2 = (pio_specs.tA + t) / t + 2;
96 cfg.bytes.field3 = 1;
97 cfg.bytes.field4 = (pio_specs.t4 + t) / t;
98
Wolfgang Denk843efb12009-05-16 10:47:43 +020099 out_be32(&im->pata.pata_time2, cfg.config);
Wolfgang Denkde26ef92009-05-16 10:47:38 +0200100
Wolfgang Denk843efb12009-05-16 10:47:43 +0200101 cfg.config = in_be32(&im->pata.pata_time3);
Wolfgang Denkde26ef92009-05-16 10:47:38 +0200102 cfg.bytes.field1 = (pio_specs.t9 + t) / t;
103
Wolfgang Denk843efb12009-05-16 10:47:43 +0200104 out_be32(&im->pata.pata_time3, cfg.config);
105
Wolfgang Denkde26ef92009-05-16 10:47:38 +0200106 debug ("PATA preinit complete.\n");
107
108 return 0;
109}
110
111#endif /* defined(CONFIG_IDE_RESET) */