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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / c609719b8d1b2dca590e0ed499016d041203e403 / . / include / configs / PCI405.h
blob: 3f9b8d40a9fb94b4b23c3cbc49ccde0cfc17d4f4 [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame^]1/*
2 * (C) Copyright 2001
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405 CPU */
37#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_PCI405 1 /* ...on a PCI405 board */
39
40#define CONFIG_BOARD_PRE_INIT 1 /* call board_pre_init() */
41#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */
42
43#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
44
45#define CONFIG_BAUDRATE 9600
46#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
47
48#if 0
49#define CONFIG_PREBOOT \
50 "crc32 f0207004 ffc 0;" \
51 "if cmp 0 f0207000 1;" \
52 "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;" \
53 "else;echo Old CRC is bad;fi"
54#endif
55
56#undef CONFIG_BOOTARGS
57#if 1
58#define CONFIG_BOOTCOMMAND \
59 "bootm fffc0000"
60#else
61#define CONFIG_BOOTCOMMAND \
62 "mw.l 0 ffffffff; mw.l 4 ffffffff;" \
63 "while cmp 0 4 1; do echo Waiting for Host...;done;" \
64 "bootm 400000"
65#endif
66
67#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
68#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
69
70#define CONFIG_MII 1 /* MII PHY management */
71#define CONFIG_PHY_ADDR 0 /* PHY address */
72
73#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
74
75#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
76 CFG_CMD_PCI | \
77 CFG_CMD_IRQ | \
78 CFG_CMD_ELF | \
79 CFG_CMD_DATE | \
80 CFG_CMD_I2C | \
81 CFG_CMD_EEPROM )
82
83/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
84#include <cmd_confdefs.h>
85
86#undef CONFIG_WATCHDOG /* watchdog disabled */
87
88#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
89
90/*
91 * Miscellaneous configurable options
92 */
93#define CFG_LONGHELP /* undef to save memory */
94#define CFG_PROMPT "=> " /* Monitor Command Prompt */
95
96#define CFG_HUSH_PARSER /* use "hush" command parser */
97#ifdef CFG_HUSH_PARSER
98#define CFG_PROMPT_HUSH_PS2 "> "
99#endif
100
101#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
102#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
103#else
104#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
105#endif
106#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
107#define CFG_MAXARGS 16 /* max number of command args */
108#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
109
110#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
111
112#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
113
114#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
115#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
116
117#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
118#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
119#define CFG_BASE_BAUD 691200
120
121/* The following table includes the supported baudrates */
122#define CFG_BAUDRATE_TABLE \
123 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
124 57600, 115200, 230400, 460800, 921600 }
125
126#define CFG_LOAD_ADDR 0x100000 /* default load address */
127#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
128
129#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
130
131#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
132
133/*-----------------------------------------------------------------------
134 * PCI stuff
135 *-----------------------------------------------------------------------
136 */
137#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
138#define PCI_HOST_FORCE 1 /* configure as pci host */
139#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
140
141#define CONFIG_PCI /* include pci support */
142#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function */
143#undef CONFIG_PCI_PNP /* no pci plug-and-play */
144 /* resource configuration */
145
146#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
147
148#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
149#define CFG_PCI_SUBSYS_DEVICEID 0x0407 /* PCI Device ID: PCI-405 */
150#define CFG_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/
151#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
152#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
153#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
154
155#if 0 /* test-only */
156#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
157#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
158#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
159#else
160#define CFG_PCI_PTM2LA 0xef600000 /* point to internal regs */
161#define CFG_PCI_PTM2MS 0xef600001 /* 4MB, enable */
162#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
163#endif
164
165/*-----------------------------------------------------------------------
166 * Start addresses for the final memory configuration
167 * (Set up by the startup code)
168 * Please note that CFG_SDRAM_BASE _must_ start at 0
169 */
170#define CFG_SDRAM_BASE 0x00000000
171#define CFG_FLASH_BASE 0xFFFD0000
172#define CFG_MONITOR_BASE CFG_FLASH_BASE
173#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
174#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
175
176/*
177 * For booting Linux, the board info and command line data
178 * have to be in the first 8 MB of memory, since this is
179 * the maximum mapped by the Linux kernel during initialization.
180 */
181#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
182/*-----------------------------------------------------------------------
183 * FLASH organization
184 */
185#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
186#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
187
188#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
189#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
190
191#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
192#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
193#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
194/*
195 * The following defines are added for buggy IOP480 byte interface.
196 * All other boards should use the standard values (CPCI405 etc.)
197 */
198#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
199#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
200#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
201
202#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
203
204#if 0 /* Use NVRAM for environment variables */
205/*-----------------------------------------------------------------------
206 * NVRAM organization
207 */
208#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
209#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
210#define CFG_ENV_ADDR \
211 (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8)) /* Env */
212
213#else /* Use EEPROM for environment variables */
214
215#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
216#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
217#define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars*/
218 /* total size of a CAT24WC08 is 1024 bytes */
219#endif
220
221#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
222#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */
223
224/*-----------------------------------------------------------------------
225 * I2C EEPROM (CAT24WC16) for environment
226 */
227#define CONFIG_HARD_I2C /* I2c with hardware support */
228#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
229#define CFG_I2C_SLAVE 0x7F
230
231#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
232#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
233/* mask of address bits that overflow into the "EEPROM chip address" */
234#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
235#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
236 /* 16 byte page write mode using*/
237 /* last 4 bits of the address */
238#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
239#define CFG_EEPROM_PAGE_WRITE_ENABLE
240
241/*-----------------------------------------------------------------------
242 * Cache Configuration
243 */
244#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
245#define CFG_CACHELINE_SIZE 32 /* ... */
246#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
247#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
248#endif
249
250/*
251 * Init Memory Controller:
252 *
253 * BR0/1 and OR0/1 (FLASH)
254 */
255
256#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
257
258/*-----------------------------------------------------------------------
259 * External Bus Controller (EBC) Setup
260 */
261
262/* Memory Bank 0 (Flash Bank 0) initialization */
263#define CFG_EBC_PB0AP 0x92015480
264#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
265
266/* Memory Bank 1 (NVRAM/RTC) initialization */
267#define CFG_EBC_PB1AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */
268#define CFG_EBC_PB1CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
269
270/* Memory Bank 2 (CAN0, 1) initialization */
271#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
272#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
273
274/* Memory Bank 3 (FPGA internal) initialization */
275#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
276#define CFG_EBC_PB3CR 0xF041C000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
277#define CFG_FPGA_BASE_ADDR 0xF0400000
278
279/*-----------------------------------------------------------------------
280 * FPGA stuff
281 */
282/* FPGA internal regs */
283#define CFG_FPGA_MODE 0x00
284#define CFG_FPGA_STATUS 0x02
285#define CFG_FPGA_TS 0x04
286#define CFG_FPGA_TS_LOW 0x06
287#define CFG_FPGA_TS_CAP0 0x10
288#define CFG_FPGA_TS_CAP0_LOW 0x12
289#define CFG_FPGA_TS_CAP1 0x14
290#define CFG_FPGA_TS_CAP1_LOW 0x16
291#define CFG_FPGA_TS_CAP2 0x18
292#define CFG_FPGA_TS_CAP2_LOW 0x1a
293#define CFG_FPGA_TS_CAP3 0x1c
294#define CFG_FPGA_TS_CAP3_LOW 0x1e
295
296/* FPGA Mode Reg */
297#define CFG_FPGA_MODE_CF_RESET 0x0001
298#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
299#define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000
300#define CFG_FPGA_MODE_TS_CLEAR 0x2000
301
302/* FPGA Status Reg */
303#define CFG_FPGA_STATUS_DIP0 0x0001
304#define CFG_FPGA_STATUS_DIP1 0x0002
305#define CFG_FPGA_STATUS_DIP2 0x0004
306#define CFG_FPGA_STATUS_FLASH 0x0008
307#define CFG_FPGA_STATUS_TS_IRQ 0x1000
308
309#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
310#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */
311
312/* FPGA program pin configuration */
313#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
314#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
315#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
316#define CFG_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
317#define CFG_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
318
319/*-----------------------------------------------------------------------
320 * Definitions for initial stack pointer and data area (in data cache)
321 */
322#if 1 /* test-only */
323#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
324
325#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
326#else
327#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
328#endif
329#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
330#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
331#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
332#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
333
334
335/*
336 * Internal Definitions
337 *
338 * Boot Flags
339 */
340#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
341#define BOOTFLAG_WARM 0x02 /* Software reboot */
342
343#endif /* __CONFIG_H */