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wdenk2d24a3a2004-06-09 21:50:45 +00001/*
Wolfgang Denk5797b822006-03-12 01:43:03 +01002 * Copyright (C) 2004-2005 Arabella Software Ltd.
wdenk2d24a3a2004-06-09 21:50:45 +00003 * Yuli Barcohen <yuli@arabellasw.com>
4 *
5 * Support for Analogue&Micro Adder boards family.
6 * Tested on AdderII and Adder87x.
7 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02008 * SPDX-License-Identifier: GPL-2.0+
wdenk2d24a3a2004-06-09 21:50:45 +00009 */
10
11#include <common.h>
12#include <mpc8xx.h>
Bryan O'Donoghuea6f5f312008-02-15 01:05:58 +000013#if defined(CONFIG_OF_LIBFDT)
14 #include <libfdt.h>
15#endif
wdenk2d24a3a2004-06-09 21:50:45 +000016
17/*
Wolfgang Denk5797b822006-03-12 01:43:03 +010018 * SDRAM is single Samsung K4S643232F-T70 chip (8MB)
19 * or single Micron MT48LC4M32B2TG-7 chip (16MB).
wdenk2d24a3a2004-06-09 21:50:45 +000020 * Minimal CPU frequency is 40MHz.
21 */
22static uint sdram_table[] = {
23 /* Single read (offset 0x00 in UPM RAM) */
24 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00,
25 0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04,
26
27 /* Burst read (offset 0x08 in UPM RAM) */
28 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00,
29 0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44,
30 0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35,
31 0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35,
32
33 /* Single write (offset 0x18 in UPM RAM) */
34 0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47,
35 0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
36
37 /* Burst write (offset 0x20 in UPM RAM) */
38 0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
39 0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04,
40 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
41 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
42
43 /* Refresh (offset 0x30 in UPM RAM) */
Wolfgang Denk5797b822006-03-12 01:43:03 +010044 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
wdenk2d24a3a2004-06-09 21:50:45 +000045 0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
46 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
47
48 /* Exception (offset 0x3C in UPM RAM) */
49 0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
50};
51
Becky Bruce9973e3c2008-06-09 16:03:40 -050052phys_size_t initdram (int board_type)
wdenk2d24a3a2004-06-09 21:50:45 +000053{
Wolfgang Denk5797b822006-03-12 01:43:03 +010054 long int msize;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055 volatile immap_t *immap = (volatile immap_t *)CONFIG_SYS_IMMR;
wdenk2d24a3a2004-06-09 21:50:45 +000056 volatile memctl8xx_t *memctl = &immap->im_memctl;
57
58 upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
59
60 /* Configure SDRAM refresh */
61 memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */
62
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063 memctl->memc_mamr = (94 << 24) | CONFIG_SYS_MAMR; /* No refresh */
wdenk2d24a3a2004-06-09 21:50:45 +000064 udelay(200);
65
66 /* Run precharge from location 0x15 */
Wolfgang Denk5797b822006-03-12 01:43:03 +010067 memctl->memc_mar = 0x0;
wdenk2d24a3a2004-06-09 21:50:45 +000068 memctl->memc_mcr = 0x80002115;
69 udelay(200);
70
71 /* Run 8 refresh cycles */
72 memctl->memc_mcr = 0x80002830;
73 udelay(200);
74
wdenk2d24a3a2004-06-09 21:50:45 +000075 /* Run MRS pattern from location 0x16 */
Wolfgang Denk5797b822006-03-12 01:43:03 +010076 memctl->memc_mar = 0x88;
wdenk2d24a3a2004-06-09 21:50:45 +000077 memctl->memc_mcr = 0x80002116;
78 udelay(200);
79
Wolfgang Denk5797b822006-03-12 01:43:03 +010080 memctl->memc_mamr |= MAMR_PTAE; /* Enable refresh */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081 memctl->memc_or1 = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
82 memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
Wolfgang Denk5797b822006-03-12 01:43:03 +010083
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084 msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE);
Wolfgang Denk5797b822006-03-12 01:43:03 +010085 memctl->memc_or1 |= ~(msize - 1);
86
wdenk2d24a3a2004-06-09 21:50:45 +000087 return msize;
88}
89
90int checkboard( void )
91{
92 puts("Board: Adder");
93#if defined(CONFIG_MPC885_FAMILY)
94 puts("87x\n");
95#elif defined(CONFIG_MPC866_FAMILY)
96 puts("II\n");
97#endif
98
99 return 0;
100}
Bryan O'Donoghuea6f5f312008-02-15 01:05:58 +0000101
102#if defined(CONFIG_OF_BOARD_SETUP)
103void ft_board_setup(void *blob, bd_t *bd)
104{
105 ft_cpu_setup(blob, bd);
106
107}
108#endif