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Marian Balakowicz991425f2006-03-14 16:24:38 +01001/*
Wolfgang Denk2ae18242010-10-06 09:05:45 +02002 * (C) Copyright 2006-2010
Marian Balakowicz991425f2006-03-14 16:24:38 +01003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Marian Balakowicz991425f2006-03-14 16:24:38 +01006 */
7
8/*
9 * mpc8349emds board configuration file
10 *
11 */
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
Marian Balakowicz991425f2006-03-14 16:24:38 +010016/*
17 * High Level Configuration Options
18 */
19#define CONFIG_E300 1 /* E300 Family */
Peter Tyser2c7920a2009-05-22 17:23:25 -050020#define CONFIG_MPC834x 1 /* MPC834x family */
Marian Balakowicz991425f2006-03-14 16:24:38 +010021#define CONFIG_MPC8349 1 /* MPC8349 specific */
22#define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */
23
Wolfgang Denk2ae18242010-10-06 09:05:45 +020024#define CONFIG_SYS_TEXT_BASE 0xFE000000
25
26#define CONFIG_PCI_66M
27#ifdef CONFIG_PCI_66M
Marian Balakowicz991425f2006-03-14 16:24:38 +010028#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
29#else
30#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
31#endif
32
Ira W. Snyder447ad572008-08-22 11:00:15 -070033#ifdef CONFIG_PCISLAVE
Ira W. Snyder447ad572008-08-22 11:00:15 -070034#define CONFIG_83XX_PCICLK 66666666 /* in Hz */
35#endif /* CONFIG_PCISLAVE */
36
Marian Balakowicz991425f2006-03-14 16:24:38 +010037#ifndef CONFIG_SYS_CLK_FREQ
Wolfgang Denk2ae18242010-10-06 09:05:45 +020038#ifdef CONFIG_PCI_66M
Marian Balakowicz991425f2006-03-14 16:24:38 +010039#define CONFIG_SYS_CLK_FREQ 66000000
Kumar Gala8fe9bf62006-04-20 13:45:32 -050040#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
Marian Balakowicz991425f2006-03-14 16:24:38 +010041#else
42#define CONFIG_SYS_CLK_FREQ 33000000
Kumar Gala8fe9bf62006-04-20 13:45:32 -050043#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
Marian Balakowicz991425f2006-03-14 16:24:38 +010044#endif
45#endif
46
47#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
48
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define CONFIG_SYS_IMMR 0xE0000000
Marian Balakowicz991425f2006-03-14 16:24:38 +010050
Joe Hershberger32795ec2011-10-11 23:57:14 -050051#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
53#define CONFIG_SYS_MEMTEST_END 0x00100000
Marian Balakowicz991425f2006-03-14 16:24:38 +010054
55/*
56 * DDR Setup
57 */
Xie Xiaobo8d172c02007-02-14 18:26:44 +080058#define CONFIG_DDR_ECC /* support DDR ECC function */
Marian Balakowiczd326f4a2006-03-16 15:19:35 +010059#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
Marian Balakowicz991425f2006-03-14 16:24:38 +010060#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
61
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +010062/*
York Sund26e34c2016-12-28 08:43:40 -080063 * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
64 * unselect it to use old spd_sdram.c
York Sund4b91062011-08-26 11:32:45 -070065 */
York Sund4b91062011-08-26 11:32:45 -070066#define CONFIG_SYS_SPD_BUS_NUM 0
67#define SPD_EEPROM_ADDRESS1 0x52
68#define SPD_EEPROM_ADDRESS2 0x51
York Sund4b91062011-08-26 11:32:45 -070069#define CONFIG_DIMM_SLOTS_PER_CTLR 2
70#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
71#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
72#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
York Sund4b91062011-08-26 11:32:45 -070073
74/*
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +010075 * 32-bit data path mode.
Wolfgang Denkcf48eb92006-04-16 10:51:58 +020076 *
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +010077 * Please note that using this mode for devices with the real density of 64-bit
78 * effectively reduces the amount of available memory due to the effect of
79 * wrapping around while translating address to row/columns, for example in the
80 * 256MB module the upper 128MB get aliased with contents of the lower
81 * 128MB); normally this define should be used for devices with real 32-bit
Wolfgang Denkcf48eb92006-04-16 10:51:58 +020082 * data path.
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +010083 */
84#undef CONFIG_DDR_32BIT
85
Joe Hershberger32795ec2011-10-11 23:57:14 -050086#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
87#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
Joe Hershberger32795ec2011-10-11 23:57:14 -050089#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
90 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
Marian Balakowicz991425f2006-03-14 16:24:38 +010091#undef CONFIG_DDR_2T_TIMING
92
Xie Xiaobo8d172c02007-02-14 18:26:44 +080093/*
94 * DDRCDR - DDR Control Driver Register
95 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
Xie Xiaobo8d172c02007-02-14 18:26:44 +080097
Marian Balakowicz991425f2006-03-14 16:24:38 +010098#if defined(CONFIG_SPD_EEPROM)
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +010099/*
100 * Determine DDR configuration from I2C interface.
101 */
102#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100103#else
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100104/*
105 * Manually set up DDR parameters
106 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_DDR_SIZE 256 /* MB */
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800108#if defined(CONFIG_DDR_II)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_DDRCDR 0x80080001
Joe Hershberger32795ec2011-10-11 23:57:14 -0500110#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
Joe Hershberger32795ec2011-10-11 23:57:14 -0500112#define CONFIG_SYS_DDR_TIMING_0 0x00220802
113#define CONFIG_SYS_DDR_TIMING_1 0x38357322
114#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
115#define CONFIG_SYS_DDR_TIMING_3 0x00000000
116#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_DDR_MODE 0x47d00432
118#define CONFIG_SYS_DDR_MODE2 0x8000c000
Joe Hershberger32795ec2011-10-11 23:57:14 -0500119#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
121#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800122#else
Joe Hershberger2e651b22011-10-11 23:57:31 -0500123#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500124 | CSCONFIG_ROW_BIT_13 \
125 | CSCONFIG_COL_BIT_10)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_DDR_TIMING_1 0x36332321
127#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500128#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100130
131#if defined(CONFIG_DDR_32BIT)
132/* set burst length to 8 for 32-bit data path */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500133 /* DLL,normal,seq,4/2.5, 8 burst len */
134#define CONFIG_SYS_DDR_MODE 0x00000023
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100135#else
136/* the default burst length is 4 - for 64-bit data path */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500137 /* DLL,normal,seq,4/2.5, 4 burst len */
138#define CONFIG_SYS_DDR_MODE 0x00000022
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100139#endif
Marian Balakowicz991425f2006-03-14 16:24:38 +0100140#endif
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800141#endif
Marian Balakowicz991425f2006-03-14 16:24:38 +0100142
143/*
144 * SDRAM on the Local Bus
145 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
147#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100148
149/*
150 * FLASH on the Local Bus
151 */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500152#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
153#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500155#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
156#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100158
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500159#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
160 | BR_PS_16 /* 16 bit port */ \
161 | BR_MS_GPCM /* MSEL = GPCM */ \
162 | BR_V) /* valid */
163#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500164 | OR_UPM_XAM \
165 | OR_GPCM_CSNT \
166 | OR_GPCM_ACS_DIV2 \
167 | OR_GPCM_XACS \
168 | OR_GPCM_SCY_15 \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500169 | OR_GPCM_TRLX_SET \
170 | OR_GPCM_EHTR_SET \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500171 | OR_GPCM_EAD)
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500172
Joe Hershberger32795ec2011-10-11 23:57:14 -0500173 /* window base at flash base */
174#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500175#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100176
Joe Hershberger32795ec2011-10-11 23:57:14 -0500177#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
178#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100179
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#undef CONFIG_SYS_FLASH_CHECKSUM
181#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
182#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100183
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200184#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100185
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
187#define CONFIG_SYS_RAMBOOT
Marian Balakowicz991425f2006-03-14 16:24:38 +0100188#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#undef CONFIG_SYS_RAMBOOT
Marian Balakowicz991425f2006-03-14 16:24:38 +0100190#endif
191
192/*
193 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
194 */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500195#define CONFIG_SYS_BCSR 0xE2400000
196 /* Access window base at BCSR base */
197#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500198#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
199#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
200 | BR_PS_8 \
201 | BR_MS_GPCM \
202 | BR_V)
203 /* 0x00000801 */
204#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
205 | OR_GPCM_XAM \
206 | OR_GPCM_CSNT \
207 | OR_GPCM_SCY_15 \
208 | OR_GPCM_TRLX_CLEAR \
209 | OR_GPCM_EHTR_CLEAR)
210 /* 0xFFFFE8F0 */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100211
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_INIT_RAM_LOCK 1
Joe Hershberger32795ec2011-10-11 23:57:14 -0500213#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
214#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
Marian Balakowicz991425f2006-03-14 16:24:38 +0100215
Joe Hershberger32795ec2011-10-11 23:57:14 -0500216#define CONFIG_SYS_GBL_DATA_OFFSET \
217 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Marian Balakowicz991425f2006-03-14 16:24:38 +0100219
Kevin Hao16c8c172016-07-08 11:25:14 +0800220#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
Kim Phillipsc8a90642012-06-30 18:29:20 -0500221#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100222
223/*
224 * Local Bus LCRR and LBCR regs
225 * LCRR: DLL bypass, Clock divider is 4
226 * External Local Bus rate is
227 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
228 */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500229#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
230#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_LBC_LBCR 0x00000000
Marian Balakowicz991425f2006-03-14 16:24:38 +0100232
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800233/*
234 * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235 * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800236 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#undef CONFIG_SYS_LB_SDRAM
Marian Balakowicz991425f2006-03-14 16:24:38 +0100238
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#ifdef CONFIG_SYS_LB_SDRAM
Marian Balakowicz991425f2006-03-14 16:24:38 +0100240/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
241/*
242 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
Marian Balakowicz991425f2006-03-14 16:24:38 +0100244 *
245 * For BR2, need:
246 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
247 * port-size = 32-bits = BR2[19:20] = 11
248 * no parity checking = BR2[21:22] = 00
249 * SDRAM for MSEL = BR2[24:26] = 011
250 * Valid = BR[31] = 1
251 *
252 * 0 4 8 12 16 20 24 28
253 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
Marian Balakowicz991425f2006-03-14 16:24:38 +0100254 */
255
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500256#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
257 | BR_PS_32 /* 32-bit port */ \
258 | BR_MS_SDRAM /* MSEL = SDRAM */ \
259 | BR_V) /* Valid */
260 /* 0xF0001861 */
261#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
262#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100263
264/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
Marian Balakowicz991425f2006-03-14 16:24:38 +0100266 *
267 * For OR2, need:
268 * 64MB mask for AM, OR2[0:7] = 1111 1100
269 * XAM, OR2[17:18] = 11
270 * 9 columns OR2[19-21] = 010
271 * 13 rows OR2[23-25] = 100
272 * EAD set for extra time OR[31] = 1
273 *
274 * 0 4 8 12 16 20 24 28
275 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
276 */
277
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500278#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \
279 | OR_SDRAM_XAM \
280 | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
281 | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
282 | OR_SDRAM_EAD)
283 /* 0xFC006901 */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100284
Joe Hershberger32795ec2011-10-11 23:57:14 -0500285 /* LB sdram refresh timer, about 6us */
286#define CONFIG_SYS_LBC_LSRT 0x32000000
287 /* LB refresh timer prescal, 266MHz/32 */
288#define CONFIG_SYS_LBC_MRTPR 0x20000000
Marian Balakowicz991425f2006-03-14 16:24:38 +0100289
Joe Hershberger32795ec2011-10-11 23:57:14 -0500290#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
Kumar Gala540dcf12009-03-26 01:34:39 -0500291 | LSDMR_BSMA1516 \
292 | LSDMR_RFCR8 \
293 | LSDMR_PRETOACT6 \
294 | LSDMR_ACTTORW3 \
295 | LSDMR_BL8 \
296 | LSDMR_WRC3 \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500297 | LSDMR_CL3)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100298
299/*
300 * SDRAM Controller configuration sequence.
301 */
Kumar Gala540dcf12009-03-26 01:34:39 -0500302#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
303#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
304#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
305#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
306#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100307#endif
308
309/*
310 * Serial Port
311 */
312#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_NS16550_SERIAL
314#define CONFIG_SYS_NS16550_REG_SIZE 1
315#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100316
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500318 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Marian Balakowicz991425f2006-03-14 16:24:38 +0100319
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
321#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100322
Kim Phillips22d71a72007-02-27 18:41:08 -0600323#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillipsa059e902010-04-15 17:36:05 -0500324#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100325
326/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200327#define CONFIG_SYS_I2C
328#define CONFIG_SYS_I2C_FSL
329#define CONFIG_SYS_FSL_I2C_SPEED 400000
330#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
331#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
332#define CONFIG_SYS_FSL_I2C2_SPEED 400000
333#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
334#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
335#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Marian Balakowicz991425f2006-03-14 16:24:38 +0100336
Ben Warren80ddd222008-01-16 22:37:42 -0500337/* SPI */
Ben Warren8931ab12008-01-26 23:41:19 -0500338#define CONFIG_MPC8XXX_SPI
Ben Warren80ddd222008-01-16 22:37:42 -0500339#undef CONFIG_SOFT_SPI /* SPI bit-banged */
Ben Warren80ddd222008-01-16 22:37:42 -0500340
341/* GPIOs. Used as SPI chip selects */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_GPIO1_PRELIM
343#define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
344#define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
Ben Warren80ddd222008-01-16 22:37:42 -0500345
Marian Balakowicz991425f2006-03-14 16:24:38 +0100346/* TSEC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Joe Hershberger32795ec2011-10-11 23:57:14 -0500348#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Joe Hershberger32795ec2011-10-11 23:57:14 -0500350#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100351
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500352/* USB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100354
355/*
356 * General PCI
357 * Addresses are mapped 1-1.
358 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
360#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
361#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
362#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
363#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
364#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500365#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
366#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
367#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100368
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
370#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
371#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
372#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
373#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
374#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500375#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
376#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
377#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100378
379#if defined(CONFIG_PCI)
380
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500381#define PCI_ONE_PCI1
Marian Balakowicz991425f2006-03-14 16:24:38 +0100382#if defined(PCI_64BIT)
383#undef PCI_ALL_PCI1
384#undef PCI_TWO_PCI1
385#undef PCI_ONE_PCI1
386#endif
387
Ira W. Snyder162338e2008-08-22 11:00:13 -0700388#define CONFIG_83XX_PCI_STREAMING
Marian Balakowicz991425f2006-03-14 16:24:38 +0100389
390#undef CONFIG_EEPRO100
391#undef CONFIG_TULIP
392
393#if !defined(CONFIG_PCI_PNP)
394 #define PCI_ENET0_IOADDR 0xFIXME
395 #define PCI_ENET0_MEMADDR 0xFIXME
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200396 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100397#endif
398
399#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100401
402#endif /* CONFIG_PCI */
403
404/*
405 * TSEC configuration
406 */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500407#define CONFIG_TSEC_ENET /* TSEC ethernet support */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100408
409#if defined(CONFIG_TSEC_ENET)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100410
411#define CONFIG_GMII 1 /* MII PHY management */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500412#define CONFIG_TSEC1 1
Kim Phillips255a35772007-05-16 16:52:19 -0500413#define CONFIG_TSEC1_NAME "TSEC0"
Joe Hershberger32795ec2011-10-11 23:57:14 -0500414#define CONFIG_TSEC2 1
Kim Phillips255a35772007-05-16 16:52:19 -0500415#define CONFIG_TSEC2_NAME "TSEC1"
Marian Balakowicz991425f2006-03-14 16:24:38 +0100416#define TSEC1_PHY_ADDR 0
417#define TSEC2_PHY_ADDR 1
418#define TSEC1_PHYIDX 0
419#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500420#define TSEC1_FLAGS TSEC_GIGABIT
421#define TSEC2_FLAGS TSEC_GIGABIT
Marian Balakowicz991425f2006-03-14 16:24:38 +0100422
423/* Options are: TSEC[0-1] */
424#define CONFIG_ETHPRIME "TSEC0"
425
426#endif /* CONFIG_TSEC_ENET */
427
428/*
429 * Configure on-board RTC
430 */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500431#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
432#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100433
434/*
435 * Environment
436 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200437#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200438 #define CONFIG_ENV_IS_IN_FLASH 1
Joe Hershberger32795ec2011-10-11 23:57:14 -0500439 #define CONFIG_ENV_ADDR \
440 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200441 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
442 #define CONFIG_ENV_SIZE 0x2000
Marian Balakowicz991425f2006-03-14 16:24:38 +0100443
444/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200445#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
446#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100447
448#else
Joe Hershberger32795ec2011-10-11 23:57:14 -0500449 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200450 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200451 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200452 #define CONFIG_ENV_SIZE 0x2000
Marian Balakowicz991425f2006-03-14 16:24:38 +0100453#endif
454
455#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200456#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100457
Jon Loeliger8ea54992007-07-04 22:30:06 -0500458/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500459 * BOOTP options
460 */
461#define CONFIG_BOOTP_BOOTFILESIZE
462#define CONFIG_BOOTP_BOOTPATH
463#define CONFIG_BOOTP_GATEWAY
464#define CONFIG_BOOTP_HOSTNAME
465
Jon Loeliger659e2f62007-07-10 09:10:49 -0500466/*
Jon Loeliger8ea54992007-07-04 22:30:06 -0500467 * Command line configuration.
468 */
Jon Loeliger8ea54992007-07-04 22:30:06 -0500469#define CONFIG_CMD_DATE
Jon Loeliger8ea54992007-07-04 22:30:06 -0500470
Marian Balakowicz991425f2006-03-14 16:24:38 +0100471#if defined(CONFIG_PCI)
Jon Loeliger8ea54992007-07-04 22:30:06 -0500472 #define CONFIG_CMD_PCI
Marian Balakowicz991425f2006-03-14 16:24:38 +0100473#endif
474
Marian Balakowicz991425f2006-03-14 16:24:38 +0100475#undef CONFIG_WATCHDOG /* watchdog disabled */
476
477/*
478 * Miscellaneous configurable options
479 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200480#define CONFIG_SYS_LONGHELP /* undef to save memory */
481#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100482
Jon Loeliger8ea54992007-07-04 22:30:06 -0500483#if defined(CONFIG_CMD_KGDB)
Joe Hershberger32795ec2011-10-11 23:57:14 -0500484 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100485#else
Joe Hershberger32795ec2011-10-11 23:57:14 -0500486 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100487#endif
488
Joe Hershberger32795ec2011-10-11 23:57:14 -0500489 /* Print Buffer Size */
490#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
491#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
492 /* Boot Argument Buffer Size */
493#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Marian Balakowicz991425f2006-03-14 16:24:38 +0100494
495/*
496 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700497 * have to be in the first 256 MB of memory, since this is
Marian Balakowicz991425f2006-03-14 16:24:38 +0100498 * the maximum mapped by the Linux kernel during initialization.
499 */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500500 /* Initial Memory map for Linux*/
501#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Kevin Hao63865272016-07-08 11:25:15 +0800502#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100503
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200504#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100505
506#if 1 /*528/264*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200507#define CONFIG_SYS_HRCW_LOW (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100508 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
509 HRCWL_DDR_TO_SCB_CLK_1X1 |\
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500510 HRCWL_CSB_TO_CLKIN |\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100511 HRCWL_VCO_1X2 |\
512 HRCWL_CORE_TO_CSB_2X1)
513#elif 0 /*396/132*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200514#define CONFIG_SYS_HRCW_LOW (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100515 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
516 HRCWL_DDR_TO_SCB_CLK_1X1 |\
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500517 HRCWL_CSB_TO_CLKIN |\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100518 HRCWL_VCO_1X4 |\
519 HRCWL_CORE_TO_CSB_3X1)
520#elif 0 /*264/132*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200521#define CONFIG_SYS_HRCW_LOW (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100522 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
523 HRCWL_DDR_TO_SCB_CLK_1X1 |\
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500524 HRCWL_CSB_TO_CLKIN |\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100525 HRCWL_VCO_1X4 |\
526 HRCWL_CORE_TO_CSB_2X1)
527#elif 0 /*132/132*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200528#define CONFIG_SYS_HRCW_LOW (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100529 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
530 HRCWL_DDR_TO_SCB_CLK_1X1 |\
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500531 HRCWL_CSB_TO_CLKIN |\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100532 HRCWL_VCO_1X4 |\
533 HRCWL_CORE_TO_CSB_1X1)
534#elif 0 /*264/264 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200535#define CONFIG_SYS_HRCW_LOW (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100536 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
537 HRCWL_DDR_TO_SCB_CLK_1X1 |\
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500538 HRCWL_CSB_TO_CLKIN |\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100539 HRCWL_VCO_1X4 |\
540 HRCWL_CORE_TO_CSB_1X1)
541#endif
542
Ira W. Snyder447ad572008-08-22 11:00:15 -0700543#ifdef CONFIG_PCISLAVE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200544#define CONFIG_SYS_HRCW_HIGH (\
Ira W. Snyder447ad572008-08-22 11:00:15 -0700545 HRCWH_PCI_AGENT |\
546 HRCWH_64_BIT_PCI |\
547 HRCWH_PCI1_ARBITER_DISABLE |\
548 HRCWH_PCI2_ARBITER_DISABLE |\
549 HRCWH_CORE_ENABLE |\
550 HRCWH_FROM_0X00000100 |\
551 HRCWH_BOOTSEQ_DISABLE |\
552 HRCWH_SW_WATCHDOG_DISABLE |\
553 HRCWH_ROM_LOC_LOCAL_16BIT |\
554 HRCWH_TSEC1M_IN_GMII |\
Joe Hershberger32795ec2011-10-11 23:57:14 -0500555 HRCWH_TSEC2M_IN_GMII)
Ira W. Snyder447ad572008-08-22 11:00:15 -0700556#else
Marian Balakowicz991425f2006-03-14 16:24:38 +0100557#if defined(PCI_64BIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200558#define CONFIG_SYS_HRCW_HIGH (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100559 HRCWH_PCI_HOST |\
560 HRCWH_64_BIT_PCI |\
561 HRCWH_PCI1_ARBITER_ENABLE |\
562 HRCWH_PCI2_ARBITER_DISABLE |\
563 HRCWH_CORE_ENABLE |\
564 HRCWH_FROM_0X00000100 |\
565 HRCWH_BOOTSEQ_DISABLE |\
566 HRCWH_SW_WATCHDOG_DISABLE |\
567 HRCWH_ROM_LOC_LOCAL_16BIT |\
568 HRCWH_TSEC1M_IN_GMII |\
Joe Hershberger32795ec2011-10-11 23:57:14 -0500569 HRCWH_TSEC2M_IN_GMII)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100570#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200571#define CONFIG_SYS_HRCW_HIGH (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100572 HRCWH_PCI_HOST |\
573 HRCWH_32_BIT_PCI |\
574 HRCWH_PCI1_ARBITER_ENABLE |\
575 HRCWH_PCI2_ARBITER_ENABLE |\
576 HRCWH_CORE_ENABLE |\
577 HRCWH_FROM_0X00000100 |\
578 HRCWH_BOOTSEQ_DISABLE |\
579 HRCWH_SW_WATCHDOG_DISABLE |\
580 HRCWH_ROM_LOC_LOCAL_16BIT |\
581 HRCWH_TSEC1M_IN_GMII |\
Joe Hershberger32795ec2011-10-11 23:57:14 -0500582 HRCWH_TSEC2M_IN_GMII)
Ira W. Snyder447ad572008-08-22 11:00:15 -0700583#endif /* PCI_64BIT */
584#endif /* CONFIG_PCISLAVE */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100585
Lee Nippera5fe5142008-04-25 15:44:45 -0500586/*
587 * System performance
588 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200589#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500590#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200591#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
592#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
593#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
594#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
Lee Nippera5fe5142008-04-25 15:44:45 -0500595
Marian Balakowicz991425f2006-03-14 16:24:38 +0100596/* System IO Config */
Kim Phillips3c9b1ee2009-06-05 14:11:33 -0500597#define CONFIG_SYS_SICRH 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200598#define CONFIG_SYS_SICRL SICRL_LDP_A
Marian Balakowicz991425f2006-03-14 16:24:38 +0100599
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200600#define CONFIG_SYS_HID0_INIT 0x000000000
Joe Hershberger32795ec2011-10-11 23:57:14 -0500601#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
602 | HID0_ENABLE_INSTRUCTION_CACHE)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100603
Joe Hershberger32795ec2011-10-11 23:57:14 -0500604/* #define CONFIG_SYS_HID0_FINAL (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100605 HID0_ENABLE_INSTRUCTION_CACHE |\
606 HID0_ENABLE_M_BIT |\
Joe Hershberger32795ec2011-10-11 23:57:14 -0500607 HID0_ENABLE_ADDRESS_BROADCAST) */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100608
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200609#define CONFIG_SYS_HID2 HID2_HBE
Becky Bruce31d82672008-05-08 19:02:12 -0500610#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100611
612/* DDR @ 0x00000000 */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500613#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500614 | BATL_PP_RW \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500615 | BATL_MEMCOHERENCE)
616#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
617 | BATU_BL_256M \
618 | BATU_VS \
619 | BATU_VP)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100620
621/* PCI @ 0x80000000 */
622#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000623#define CONFIG_PCI_INDIRECT_BRIDGE
Joe Hershberger32795ec2011-10-11 23:57:14 -0500624#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500625 | BATL_PP_RW \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500626 | BATL_MEMCOHERENCE)
627#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
628 | BATU_BL_256M \
629 | BATU_VS \
630 | BATU_VP)
631#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500632 | BATL_PP_RW \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500633 | BATL_CACHEINHIBIT \
634 | BATL_GUARDEDSTORAGE)
635#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
636 | BATU_BL_256M \
637 | BATU_VS \
638 | BATU_VP)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100639#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200640#define CONFIG_SYS_IBAT1L (0)
641#define CONFIG_SYS_IBAT1U (0)
642#define CONFIG_SYS_IBAT2L (0)
643#define CONFIG_SYS_IBAT2U (0)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100644#endif
645
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500646#ifdef CONFIG_MPC83XX_PCI2
Joe Hershberger32795ec2011-10-11 23:57:14 -0500647#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500648 | BATL_PP_RW \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500649 | BATL_MEMCOHERENCE)
650#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
651 | BATU_BL_256M \
652 | BATU_VS \
653 | BATU_VP)
654#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500655 | BATL_PP_RW \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500656 | BATL_CACHEINHIBIT \
657 | BATL_GUARDEDSTORAGE)
658#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
659 | BATU_BL_256M \
660 | BATU_VS \
661 | BATU_VP)
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500662#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200663#define CONFIG_SYS_IBAT3L (0)
664#define CONFIG_SYS_IBAT3U (0)
665#define CONFIG_SYS_IBAT4L (0)
666#define CONFIG_SYS_IBAT4U (0)
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500667#endif
Marian Balakowicz991425f2006-03-14 16:24:38 +0100668
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500669/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500670#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500671 | BATL_PP_RW \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500672 | BATL_CACHEINHIBIT \
673 | BATL_GUARDEDSTORAGE)
674#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
675 | BATU_BL_256M \
676 | BATU_VS \
677 | BATU_VP)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100678
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500679/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500680#define CONFIG_SYS_IBAT6L (0xF0000000 \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500681 | BATL_PP_RW \
682 | BATL_MEMCOHERENCE \
683 | BATL_GUARDEDSTORAGE)
Joe Hershberger32795ec2011-10-11 23:57:14 -0500684#define CONFIG_SYS_IBAT6U (0xF0000000 \
685 | BATU_BL_256M \
686 | BATU_VS \
687 | BATU_VP)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100688
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200689#define CONFIG_SYS_IBAT7L (0)
690#define CONFIG_SYS_IBAT7U (0)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100691
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200692#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
693#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
694#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
695#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
696#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
697#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
698#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
699#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
700#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
701#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
702#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
703#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
704#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
705#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
706#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
707#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Marian Balakowicz991425f2006-03-14 16:24:38 +0100708
Jon Loeliger8ea54992007-07-04 22:30:06 -0500709#if defined(CONFIG_CMD_KGDB)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100710#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100711#endif
712
713/*
714 * Environment Configuration
715 */
716#define CONFIG_ENV_OVERWRITE
717
718#if defined(CONFIG_TSEC_ENET)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100719#define CONFIG_HAS_ETH1
Andy Fleming10327dc2007-08-16 16:35:02 -0500720#define CONFIG_HAS_ETH0
Marian Balakowicz991425f2006-03-14 16:24:38 +0100721#endif
722
Marian Balakowicz991425f2006-03-14 16:24:38 +0100723#define CONFIG_HOSTNAME mpc8349emds
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000724#define CONFIG_ROOTPATH "/nfsroot/rootfs"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000725#define CONFIG_BOOTFILE "uImage"
Marian Balakowicz991425f2006-03-14 16:24:38 +0100726
Joe Hershberger32795ec2011-10-11 23:57:14 -0500727#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100728
Joe Hershberger32795ec2011-10-11 23:57:14 -0500729#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100730
731#define CONFIG_BAUDRATE 115200
732
733#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100734 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Marian Balakowicz991425f2006-03-14 16:24:38 +0100735 "echo"
736
737#define CONFIG_EXTRA_ENV_SETTINGS \
738 "netdev=eth0\0" \
739 "hostname=mpc8349emds\0" \
740 "nfsargs=setenv bootargs root=/dev/nfs rw " \
741 "nfsroot=${serverip}:${rootpath}\0" \
742 "ramargs=setenv bootargs root=/dev/ram rw\0" \
743 "addip=setenv bootargs ${bootargs} " \
744 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
745 ":${hostname}:${netdev}:off panic=1\0" \
746 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
747 "flash_nfs=run nfsargs addip addtty;" \
748 "bootm ${kernel_addr}\0" \
749 "flash_self=run ramargs addip addtty;" \
750 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
751 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
752 "bootm\0" \
Marian Balakowicz991425f2006-03-14 16:24:38 +0100753 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
754 "update=protect off fe000000 fe03ffff; " \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500755 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
Detlev Zundeld8ab58b2008-03-06 16:45:53 +0100756 "upd=run load update\0" \
Kim Phillips79f516b2009-08-21 16:34:38 -0500757 "fdtaddr=780000\0" \
Kim Phillipscc861f72009-08-26 21:25:46 -0500758 "fdtfile=mpc834x_mds.dtb\0" \
Marian Balakowicz991425f2006-03-14 16:24:38 +0100759 ""
760
Joe Hershberger32795ec2011-10-11 23:57:14 -0500761#define CONFIG_NFSBOOTCOMMAND \
762 "setenv bootargs root=/dev/nfs rw " \
763 "nfsroot=$serverip:$rootpath " \
764 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
765 "$netdev:off " \
766 "console=$consoledev,$baudrate $othbootargs;" \
767 "tftp $loadaddr $bootfile;" \
768 "tftp $fdtaddr $fdtfile;" \
769 "bootm $loadaddr - $fdtaddr"
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600770
771#define CONFIG_RAMBOOTCOMMAND \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500772 "setenv bootargs root=/dev/ram rw " \
773 "console=$consoledev,$baudrate $othbootargs;" \
774 "tftp $ramdiskaddr $ramdiskfile;" \
775 "tftp $loadaddr $bootfile;" \
776 "tftp $fdtaddr $fdtfile;" \
777 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600778
Marian Balakowicz991425f2006-03-14 16:24:38 +0100779#define CONFIG_BOOTCOMMAND "run flash_self"
780
781#endif /* __CONFIG_H */