blob: d7af4e008cc63f16885ecb92eb14be9d8473b39d [file] [log] [blame]
Matthias Fuchs99d8b232009-07-22 13:56:21 +02001/*
2 * (C) Copyright 2009
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Matthias Fuchs99d8b232009-07-22 13:56:21 +02006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#define CONFIG_405EP 1 /* This is a PPC405 CPU */
Matthias Fuchs99d8b232009-07-22 13:56:21 +020012#define CONFIG_PMC405DE 1 /* ...on a PMC405DE board */
13
Wolfgang Denk2ae18242010-10-06 09:05:45 +020014#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
15
Matthias Fuchs99d8b232009-07-22 13:56:21 +020016#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
17#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
18#define CONFIG_BOARD_TYPES 1 /* support board types */
19
20#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
21
22#define CONFIG_BAUDRATE 115200
Matthias Fuchs99d8b232009-07-22 13:56:21 +020023
24#undef CONFIG_BOOTARGS
25#undef CONFIG_BOOTCOMMAND
26
27#define CONFIG_PREBOOT /* enable preboot variable */
28
29#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change*/
30
Matthias Fuchs99d8b232009-07-22 13:56:21 +020031#define CONFIG_HAS_ETH1
32
33#define CONFIG_PPC4xx_EMAC
34#define CONFIG_MII 1 /* MII PHY management */
35#define CONFIG_PHY_ADDR 1 /* PHY address */
36#define CONFIG_PHY1_ADDR 2 /* 2nd PHY address */
37
38#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
39
40/*
41 * BOOTP options
42 */
43#define CONFIG_BOOTP_SUBNETMASK
44#define CONFIG_BOOTP_GATEWAY
45#define CONFIG_BOOTP_HOSTNAME
46#define CONFIG_BOOTP_BOOTPATH
47#define CONFIG_BOOTP_DNS
48#define CONFIG_BOOTP_DNS2
49#define CONFIG_BOOTP_SEND_HOSTNAME
50
51/*
52 * Command line configuration.
53 */
Matthias Fuchs99d8b232009-07-22 13:56:21 +020054#define CONFIG_CMD_BSP
55#define CONFIG_CMD_CHIP_CONFIG
56#define CONFIG_CMD_DATE
Matthias Fuchs99d8b232009-07-22 13:56:21 +020057#define CONFIG_CMD_EEPROM
Matthias Fuchs99d8b232009-07-22 13:56:21 +020058#define CONFIG_CMD_IRQ
Matthias Fuchs99d8b232009-07-22 13:56:21 +020059#define CONFIG_CMD_PCI
Matthias Fuchs99d8b232009-07-22 13:56:21 +020060
Matthias Fuchs99d8b232009-07-22 13:56:21 +020061#undef CONFIG_WATCHDOG /* watchdog disabled */
62#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
63#define CONFIG_PRAM 0
64
65/*
66 * Miscellaneous configurable options
67 */
68#define CONFIG_SYS_LONGHELP
Matthias Fuchs99d8b232009-07-22 13:56:21 +020069
70#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
71#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
72#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
73#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
74
75#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
Matthias Fuchs99d8b232009-07-22 13:56:21 +020076
77#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
78#define CONFIG_SYS_MEMTEST_END 0x3000000 /* 1 ... 48 MB in DRAM */
79
Stefan Roese550650d2010-09-20 16:05:31 +020080#define CONFIG_CONS_INDEX 2 /* Use UART1 */
Stefan Roese550650d2010-09-20 16:05:31 +020081#define CONFIG_SYS_NS16550_SERIAL
82#define CONFIG_SYS_NS16550_REG_SIZE 1
83#define CONFIG_SYS_NS16550_CLK get_serial_clock()
84
Matthias Fuchs99d8b232009-07-22 13:56:21 +020085#undef CONFIG_SYS_EXT_SERIAL_CLOCK
86#define CONFIG_SYS_BASE_BAUD 691200
Matthias Fuchs99d8b232009-07-22 13:56:21 +020087
Matthias Fuchs99d8b232009-07-22 13:56:21 +020088#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
89#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
90
Matthias Fuchs99d8b232009-07-22 13:56:21 +020091#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Matthias Fuchs99d8b232009-07-22 13:56:21 +020092#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
Matthias Fuchs99d8b232009-07-22 13:56:21 +020093
Matthias Fuchs99d8b232009-07-22 13:56:21 +020094/*
95 * PCI stuff
96 */
97#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
98#define PCI_HOST_FORCE 1 /* configure as pci host */
99#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
100
Gabor Juhos842033e2013-05-30 07:06:12 +0000101#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Matthias Fuchs99d8b232009-07-22 13:56:21 +0200102#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
Matthias Fuchs99d8b232009-07-22 13:56:21 +0200103
104#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
105
106/*
107 * PCI identification
108 */
109#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH
110#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x040e /* Dev ID: Non-Monarch */
111#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x040f /* Dev ID: Monarch */
112#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC
113#define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST
114
115#define CONFIG_SYS_PCI_CLASSCODE CONFIG_SYS_PCI_CLASSCODE_MONARCH
116#define CONFIG_SYS_PCI_SUBSYS_DEVICEID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
117
118#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
119#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable=1 */
120#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
121#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to CPLD, GPIO */
122#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable=1 */
123#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
124
Matthias Fuchs82379b52009-09-07 17:00:41 +0200125#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
126
Matthias Fuchs99d8b232009-07-22 13:56:21 +0200127/*
128 * For booting Linux, the board info and command line data
129 * have to be in the first 8 MB of memory, since this is
130 * the maximum mapped by the Linux kernel during initialization.
131 */
132#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
133/*
134 * FLASH organization
135 */
136#define CONFIG_SYS_FLASH_CFI 1 /* CFI compatible */
137#define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */
138
139#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
140
141#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max. no. memory banks */
142#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per chip */
143
144#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* erase timeout (in ms) */
145#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* write timeout (in ms) */
146
147#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* buffered writes (faster) */
148#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */
149
150#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* 'E' for empty sector (flinfo) */
151#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
152
Matthias Fuchs99d8b232009-07-22 13:56:21 +0200153/*
154 * Start addresses for the final memory configuration
155 * (Set up by the startup code)
156 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
157 */
158#define CONFIG_SYS_SDRAM_BASE 0x00000000
159#define CONFIG_SYS_FLASH_BASE 0xfe000000
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200160#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
161#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
Matthias Fuchs99d8b232009-07-22 13:56:21 +0200162#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
163
164/*
165 * Environment in EEPROM setup
166 */
167#define CONFIG_ENV_IS_IN_EEPROM 1
168#define CONFIG_ENV_OFFSET 0x100
169#define CONFIG_ENV_SIZE 0x700
170
171/*
172 * I2C EEPROM (24W16) for environment
173 */
Dirk Eibach880540d2013-04-25 02:40:01 +0000174#define CONFIG_SYS_I2C
175#define CONFIG_SYS_I2C_PPC4XX
176#define CONFIG_SYS_I2C_PPC4XX_CH0
177#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
178#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
Matthias Fuchs99d8b232009-07-22 13:56:21 +0200179
180#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24W16 */
181#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
182/* mask of address bits that overflow into the "EEPROM chip address" */
183#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
184#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
185 /* 16 byte page write mode using*/
186 /* last 4 bits of the address */
187#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
188#define CONFIG_SYS_EEPROM_WREN 1
189
190#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50
191#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0x40
192#define CONFIG_4xx_CONFIG_BLOCKSIZE 0x20
193
194/*
195 * RTC
196 */
197#define CONFIG_RTC_RX8025
198
199/*
200 * External Bus Controller (EBC) Setup
201 * (max. 55MHZ EBC clock)
202 */
203/* Memory Bank 0 (NOR flash) BAS=0xFE0,BS=32MB,BU=R/W,BW=16bit */
204#define CONFIG_SYS_EBC_PB0AP 0x03017200
205#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xba000)
206
207/* Memory Bank 1 (CPLD) BAS=0xEF0,BS=16MB,BU=R/W,BW=16bit */
208#define CONFIG_SYS_CPLD_BASE 0xef000000
209#define CONFIG_SYS_EBC_PB1AP 0x00800000
210#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_CPLD_BASE | 0x18000)
211
212/*
213 * Definitions for initial stack pointer and data area (in data cache)
214 */
215/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
216#define CONFIG_SYS_TEMP_STACK_OCM 1
217
218/* On Chip Memory location */
219#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
220#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
221/* inside SDRAM */
222#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
223/* End of used area in RAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200224#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
Matthias Fuchs99d8b232009-07-22 13:56:21 +0200225
Wolfgang Denk553f0982010-10-26 13:32:32 +0200226#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200227 GENERATED_GBL_DATA_SIZE)
Matthias Fuchs99d8b232009-07-22 13:56:21 +0200228#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
229
230/*
231 * GPIO Configuration
232 */
233#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alt1 */ \
234{ \
235/* GPIO Core 0 */ \
236{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
237{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
238{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
239{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
240{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
241{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
242{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO6 TS4 */ \
243{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
244{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
245{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO9 TrcClk */ \
246{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
247{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
248{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
249{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
250{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
251{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
252{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
253{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
254{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
255{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
256{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
257{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
258{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
259{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
260{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
261{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
262{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
263{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
264{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
265{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
266{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
267{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
268} \
269}
270
271#define CONFIG_SYS_GPIO_HWREV_MASK (0xf0000000 >> 1) /* GPIO1..4 */
272#define CONFIG_SYS_GPIO_HWREV_SHIFT 27
273#define CONFIG_SYS_GPIO_LEDRUN_N (0x80000000 >> 5) /* GPIO5 */
274#define CONFIG_SYS_GPIO_LEDA_N (0x80000000 >> 6) /* GPIO6 */
275#define CONFIG_SYS_GPIO_LEDB_N (0x80000000 >> 7) /* GPIO7 */
276#define CONFIG_SYS_GPIO_SELFRST_N (0x80000000 >> 8) /* GPIO8 */
277#define CONFIG_SYS_GPIO_EEPROM_WP (0x80000000 >> 9) /* GPIO9 */
278#define CONFIG_SYS_GPIO_MONARCH_N (0x80000000 >> 11) /* GPIO11 */
279#define CONFIG_SYS_GPIO_EREADY (0x80000000 >> 12) /* GPIO12 */
280#define CONFIG_SYS_GPIO_M66EN (0x80000000 >> 13) /* GPIO13 */
281
282/*
283 * Default speed selection (cpu_plb_opb_ebc) in mhz.
284 * This value will be set if iic boot eprom is disabled.
285 */
286#undef CONFIG_SYS_FCPU333MHZ
287#define CONFIG_SYS_FCPU266MHZ
288#undef CONFIG_SYS_FCPU133MHZ
289
290#if defined(CONFIG_SYS_FCPU333MHZ)
291/*
292 * CPU: 333MHz
293 * PLB/SDRAM/MAL: 111MHz
294 * OPB: 55MHz
295 * EBC: 55MHz
296 * PCI: 55MHz (111MHz on M66EN=1)
297 */
298#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
299 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
300 PLL_MALDIV_1 | PLL_PCIDIV_2)
301#define PLLMR1_DEFAULT (PLL_FBKDIV_10 | \
302 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
303 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
304#endif
305
306#if defined(CONFIG_SYS_FCPU266MHZ)
307/*
308 * CPU: 266MHz
309 * PLB/SDRAM/MAL: 133MHz
310 * OPB: 66MHz
311 * EBC: 44MHz
312 * PCI: 44MHz (66MHz on M66EN=1)
313 */
314#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
315 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
316 PLL_MALDIV_1 | PLL_PCIDIV_3)
317#define PLLMR1_DEFAULT (PLL_FBKDIV_8 | \
318 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
319 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
320#endif
321
322#if defined(CONFIG_SYS_FCPU133MHZ)
323/*
324 * CPU: 133MHz
325 * PLB/SDRAM/MAL: 133MHz
326 * OPB: 66MHz
327 * EBC: 44MHz
328 * PCI: 44MHz (66MHz on M66EN=1)
329 */
330#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
331 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
332 PLL_MALDIV_1 | PLL_PCIDIV_3)
333#define PLLMR1_DEFAULT (PLL_FBKDIV_4 | \
334 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
335 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
336#endif
337
338#endif /* __CONFIG_H */