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wdenk5da627a2003-10-09 20:09:04 +00001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk5da627a2003-10-09 20:09:04 +00006 */
7
8/*
9 * This file contains the configuration parameters for the dbau1x00 board.
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
wdenk5da627a2003-10-09 20:09:04 +000015#define CONFIG_DBAU1X00 1
Shinya Kuribayashi8bde63e2008-06-07 20:51:56 +090016#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
wdenk5da627a2003-10-09 20:09:04 +000017
wdenka2663ea2003-12-07 18:32:37 +000018#ifdef CONFIG_DBAU1000
wdenk5da627a2003-10-09 20:09:04 +000019/* Also known as Merlot */
Shinya Kuribayashi8bde63e2008-06-07 20:51:56 +090020#define CONFIG_SOC_AU1000 1
wdenka2663ea2003-12-07 18:32:37 +000021#else
22#ifdef CONFIG_DBAU1100
Shinya Kuribayashi8bde63e2008-06-07 20:51:56 +090023#define CONFIG_SOC_AU1100 1
wdenka2663ea2003-12-07 18:32:37 +000024#else
25#ifdef CONFIG_DBAU1500
Shinya Kuribayashi8bde63e2008-06-07 20:51:56 +090026#define CONFIG_SOC_AU1500 1
wdenkd4ca31c2004-01-02 14:00:00 +000027#else
wdenkff36fd82005-01-09 22:28:56 +000028#ifdef CONFIG_DBAU1550
29/* Cabernet */
Shinya Kuribayashi8bde63e2008-06-07 20:51:56 +090030#define CONFIG_SOC_AU1550 1
wdenkff36fd82005-01-09 22:28:56 +000031#else
wdenka2663ea2003-12-07 18:32:37 +000032#error "No valid board set"
33#endif
34#endif
35#endif
wdenkff36fd82005-01-09 22:28:56 +000036#endif
wdenk5da627a2003-10-09 20:09:04 +000037
wdenk5da627a2003-10-09 20:09:04 +000038
39#define CONFIG_BAUDRATE 115200
40
41/* valid baudrates */
wdenk5da627a2003-10-09 20:09:04 +000042
43#define CONFIG_TIMESTAMP /* Print image info with timestamp */
44#undef CONFIG_BOOTARGS
45
46#define CONFIG_EXTRA_ENV_SETTINGS \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010047 "addmisc=setenv bootargs ${bootargs} " \
48 "console=ttyS0,${baudrate} " \
wdenk5da627a2003-10-09 20:09:04 +000049 "panic=1\0" \
50 "bootfile=/tftpboot/vmlinux.srec\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010051 "load=tftp 80500000 ${u-boot}\0" \
wdenk5da627a2003-10-09 20:09:04 +000052 ""
wdenkff36fd82005-01-09 22:28:56 +000053
54#ifdef CONFIG_DBAU1550
55/* Boot from flash by default, revert to bootp */
56#define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
wdenkff36fd82005-01-09 22:28:56 +000057#else /* CONFIG_DBAU1550 */
Heiko Schocherad882972006-04-11 14:53:29 +020058#define CONFIG_BOOTCOMMAND "bootp;bootm"
wdenkff36fd82005-01-09 22:28:56 +000059#endif /* CONFIG_DBAU1550 */
60
Jon Loeligerab999ba2007-07-04 22:32:03 -050061/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -050062 * BOOTP options
63 */
64#define CONFIG_BOOTP_BOOTFILESIZE
65#define CONFIG_BOOTP_BOOTPATH
66#define CONFIG_BOOTP_GATEWAY
67#define CONFIG_BOOTP_HOSTNAME
68
Jon Loeliger80ff4f92007-07-10 09:29:01 -050069/*
Jon Loeligerab999ba2007-07-04 22:32:03 -050070 * Command line configuration.
71 */
Jon Loeligerab999ba2007-07-04 22:32:03 -050072#undef CONFIG_CMD_BEDBUG
Jon Loeligerab999ba2007-07-04 22:32:03 -050073
74#ifdef CONFIG_DBAU1550
75
Jon Loeligerab999ba2007-07-04 22:32:03 -050076#undef CONFIG_CMD_IDE
Jon Loeligerab999ba2007-07-04 22:32:03 -050077#undef CONFIG_CMD_PCMCIA
78
79#else
80
81#define CONFIG_CMD_IDE
Jon Loeligerab999ba2007-07-04 22:32:03 -050082
Jon Loeligerab999ba2007-07-04 22:32:03 -050083#endif
84
wdenk5da627a2003-10-09 20:09:04 +000085/*
86 * Miscellaneous configurable options
87 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenkff36fd82005-01-09 22:28:56 +000089
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
91#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
92#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
wdenk5da627a2003-10-09 20:09:04 +000093
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_MALLOC_LEN 128*1024
wdenk5da627a2003-10-09 20:09:04 +000095
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
wdenk5da627a2003-10-09 20:09:04 +000097
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_MHZ 396
wdenkff36fd82005-01-09 22:28:56 +000099
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#if (CONFIG_SYS_MHZ % 12) != 0
wdenkff36fd82005-01-09 22:28:56 +0000101#error "Invalid CPU frequency - must be multiple of 12!"
102#endif
103
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
Shinya Kuribayashia55d4812008-06-05 22:29:00 +0900105
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
wdenk5da627a2003-10-09 20:09:04 +0000107
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
wdenk5da627a2003-10-09 20:09:04 +0000109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_MEMTEST_START 0x80100000
111#define CONFIG_SYS_MEMTEST_END 0x80800000
wdenk5da627a2003-10-09 20:09:04 +0000112
113/*-----------------------------------------------------------------------
114 * FLASH and environment organization
115 */
wdenkff36fd82005-01-09 22:28:56 +0000116#ifdef CONFIG_DBAU1550
117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
119#define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
wdenkff36fd82005-01-09 22:28:56 +0000120
121#define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
122#define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
123
wdenkff36fd82005-01-09 22:28:56 +0000124#else /* CONFIG_DBAU1550 */
125
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
127#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
wdenk5da627a2003-10-09 20:09:04 +0000128
129#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
130#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
131
wdenkff36fd82005-01-09 22:28:56 +0000132#endif /* CONFIG_DBAU1550 */
133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
Heiko Schocherad882972006-04-11 14:53:29 +0200135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_FLASH_CFI 1
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200137#define CONFIG_FLASH_CFI_DRIVER 1
wdenkff36fd82005-01-09 22:28:56 +0000138
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200139#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_MONITOR_LEN (192 << 10)
wdenk5da627a2003-10-09 20:09:04 +0000141
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
wdenk5da627a2003-10-09 20:09:04 +0000143
144/* We boot from this flash, selected with dip switch */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
wdenk5da627a2003-10-09 20:09:04 +0000146
147/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
149#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenk5da627a2003-10-09 20:09:04 +0000150
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200151#define CONFIG_ENV_IS_NOWHERE 1
wdenk5da627a2003-10-09 20:09:04 +0000152
153/* Address and size of Primary Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200154#define CONFIG_ENV_ADDR 0xB0030000
155#define CONFIG_ENV_SIZE 0x10000
wdenk5da627a2003-10-09 20:09:04 +0000156
157#define CONFIG_FLASH_16BIT
158
159#define CONFIG_NR_DRAM_BANKS 2
160
wdenkff36fd82005-01-09 22:28:56 +0000161#ifdef CONFIG_DBAU1550
162#define MEM_SIZE 192
163#else
164#define MEM_SIZE 64
165#endif
166
wdenk5da627a2003-10-09 20:09:04 +0000167#define CONFIG_MEMSIZE_IN_BYTES
168
wdenkff36fd82005-01-09 22:28:56 +0000169#ifndef CONFIG_DBAU1550
wdenk5da627a2003-10-09 20:09:04 +0000170/*---ATA PCMCIA ------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
172#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
wdenk5da627a2003-10-09 20:09:04 +0000173#define CONFIG_PCMCIA_SLOT_A
174
175#define CONFIG_ATAPI 1
176#define CONFIG_MAC_PARTITION 1
177
178/* We run CF in "true ide" mode or a harddrive via pcmcia */
179#define CONFIG_IDE_PCMCIA 1
180
181/* We only support one slot for now */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
183#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenk5da627a2003-10-09 20:09:04 +0000184
185#undef CONFIG_IDE_LED /* LED for ide not supported */
186#undef CONFIG_IDE_RESET /* reset for ide not supported */
187
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenk5da627a2003-10-09 20:09:04 +0000189
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenk5da627a2003-10-09 20:09:04 +0000191
wdenkd4ca31c2004-01-02 14:00:00 +0000192/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_ATA_DATA_OFFSET 8
wdenk5da627a2003-10-09 20:09:04 +0000194
195/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_ATA_REG_OFFSET 0
wdenk5da627a2003-10-09 20:09:04 +0000197
198/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkff36fd82005-01-09 22:28:56 +0000200#endif /* CONFIG_DBAU1550 */
wdenk5da627a2003-10-09 20:09:04 +0000201
wdenk5da627a2003-10-09 20:09:04 +0000202#endif /* __CONFIG_H */