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Stefan Roese995b72d2012-05-30 22:59:08 +00001/*
2 * (C) Copyright 2009
3 * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
4 *
Stefan Roese2fbdbda2015-08-18 09:27:17 +02005 * Copyright (C) 2012, 2015 Stefan Roese <sr@denx.de>
Stefan Roese995b72d2012-05-30 22:59:08 +00006 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese995b72d2012-05-30 22:59:08 +00008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/*
14 * High Level Configuration Options
15 * (easy to change)
16 */
17#define CONFIG_SPEAR600 /* SPEAr600 SoC */
18#define CONFIG_X600 /* on X600 board */
Stefan Roese9b6aa002015-09-02 11:11:00 +020019#define CONFIG_SYS_THUMB_BUILD
Stefan Roese995b72d2012-05-30 22:59:08 +000020
21#include <asm/arch/hardware.h>
22
23/* Timer, HZ specific defines */
Stefan Roese995b72d2012-05-30 22:59:08 +000024#define CONFIG_SYS_HZ_CLOCK 8300000
25
26#define CONFIG_SYS_TEXT_BASE 0x00800040
27#define CONFIG_SYS_FLASH_BASE 0xf8000000
28/* Reserve 8KiB for SPL */
29#define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */
30#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
31#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \
32 CONFIG_SYS_SPL_LEN)
Stefan Roese285e2662015-08-18 09:27:20 +020033#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
Stefan Roese995b72d2012-05-30 22:59:08 +000034#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
35#define CONFIG_SYS_MONITOR_LEN 0x60000
36
37#define CONFIG_ENV_IS_IN_FLASH
38
39/* Serial Configuration (PL011) */
40#define CONFIG_SYS_SERIAL0 0xD0000000
41#define CONFIG_SYS_SERIAL1 0xD0080000
42#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \
43 (void *)CONFIG_SYS_SERIAL1 }
44#define CONFIG_PL011_SERIAL
45#define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
46#define CONFIG_CONS_INDEX 0
47#define CONFIG_BAUDRATE 115200
48#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
49 57600, 115200 }
50#define CONFIG_SYS_LOADS_BAUD_CHANGE
51
52/* NOR FLASH config options */
53#define CONFIG_ST_SMI
54#define CONFIG_SYS_MAX_FLASH_BANKS 1
55#define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000
56#define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE }
57#define CONFIG_SYS_MAX_FLASH_SECT 128
58#define CONFIG_SYS_FLASH_EMPTY_INFO
59#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ)
60#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ)
61
62/* NAND FLASH config options */
63#define CONFIG_NAND_FSMC
64#define CONFIG_SYS_NAND_SELF_INIT
65#define CONFIG_SYS_MAX_NAND_DEVICE 1
66#define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE
67#define CONFIG_MTD_ECC_SOFT
68#define CONFIG_SYS_FSMC_NAND_8BIT
69#define CONFIG_SYS_NAND_ONFI_DETECTION
Stefan Roese0ddc5a22015-09-02 11:10:59 +020070#define CONFIG_NAND_ECC_BCH
71#define CONFIG_BCH
Stefan Roese995b72d2012-05-30 22:59:08 +000072
73/* UBI/UBI config options */
74#define CONFIG_MTD_DEVICE
75#define CONFIG_MTD_PARTITIONS
76#define CONFIG_RBTREE
77
78/* Ethernet config options */
79#define CONFIG_MII
Stefan Roese995b72d2012-05-30 22:59:08 +000080#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
Stefan Roese995b72d2012-05-30 22:59:08 +000081#define CONFIG_PHY_ADDR 0 /* PHY address */
82#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
Stefan Roesef7c32e82016-04-27 09:10:42 +020083#define CONFIG_PHY_MICREL
84#define CONFIG_PHY_MICREL_KSZ9031
Stefan Roese995b72d2012-05-30 22:59:08 +000085
86#define CONFIG_SPEAR_GPIO
87
88/* I2C config options */
Stefan Roese678398b2014-10-28 12:12:00 +010089#define CONFIG_SYS_I2C
Alexey Brodkinf93f5892014-02-10 12:20:11 +040090#define CONFIG_SYS_I2C_BASE 0xD0200000
Stefan Roese995b72d2012-05-30 22:59:08 +000091#define CONFIG_SYS_I2C_SPEED 400000
92#define CONFIG_SYS_I2C_SLAVE 0x02
93#define CONFIG_I2C_CHIPADDRESS 0x50
94
95#define CONFIG_RTC_M41T62 1
96#define CONFIG_SYS_I2C_RTC_ADDR 0x68
97
98/* FPGA config options */
99#define CONFIG_FPGA
100#define CONFIG_FPGA_XILINX
101#define CONFIG_FPGA_SPARTAN3
102#define CONFIG_FPGA_COUNT 1
103
Stefan Roese285e2662015-08-18 09:27:20 +0200104/* USB EHCI options */
105#define CONFIG_USB_EHCI
106#define CONFIG_USB_EHCI_SPEAR
Stefan Roese285e2662015-08-18 09:27:20 +0200107#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
108
Stefan Roese995b72d2012-05-30 22:59:08 +0000109/*
110 * Command support defines
111 */
Stefan Roese995b72d2012-05-30 22:59:08 +0000112#define CONFIG_CMD_DATE
Stefan Roese995b72d2012-05-30 22:59:08 +0000113#define CONFIG_CMD_ENV
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530114#define CONFIG_CMD_FPGA_LOADMK
Stefan Roese995b72d2012-05-30 22:59:08 +0000115#define CONFIG_CMD_MTDPARTS
116#define CONFIG_CMD_NAND
Stefan Roese995b72d2012-05-30 22:59:08 +0000117#define CONFIG_CMD_SAVES
Stefan Roese995b72d2012-05-30 22:59:08 +0000118#define CONFIG_CMD_UBIFS
119#define CONFIG_LZO
120
Stefan Roese285e2662015-08-18 09:27:20 +0200121/* Filesystem support (for USB key) */
122#define CONFIG_SUPPORT_VFAT
123#define CONFIG_DOS_PARTITION
124
Stefan Roese995b72d2012-05-30 22:59:08 +0000125
Stefan Roese995b72d2012-05-30 22:59:08 +0000126/*
127 * U-Boot Environment placing definitions.
128 */
129#define CONFIG_ENV_SECT_SIZE 0x00010000
130#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
131 CONFIG_SYS_MONITOR_LEN)
132#define CONFIG_ENV_SIZE 0x02000
133#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
134 CONFIG_ENV_SECT_SIZE)
135#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
136
137/* Miscellaneous configurable options */
138#define CONFIG_ARCH_CPU_INIT
Stefan Roese995b72d2012-05-30 22:59:08 +0000139#define CONFIG_BOOT_PARAMS_ADDR 0x00000100
140#define CONFIG_CMDLINE_TAG
Stefan Roese995b72d2012-05-30 22:59:08 +0000141#define CONFIG_SETUP_MEMORY_TAGS
142#define CONFIG_MISC_INIT_R
143#define CONFIG_BOARD_LATE_INIT
Stefan Roese995b72d2012-05-30 22:59:08 +0000144#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
Stefan Roese995b72d2012-05-30 22:59:08 +0000145
146#define CONFIG_SYS_MEMTEST_START 0x00800000
147#define CONFIG_SYS_MEMTEST_END 0x04000000
Stefan Roese285e2662015-08-18 09:27:20 +0200148#define CONFIG_SYS_MALLOC_LEN (8 << 20)
Stefan Roese995b72d2012-05-30 22:59:08 +0000149#define CONFIG_SYS_LONGHELP
Stefan Roese995b72d2012-05-30 22:59:08 +0000150#define CONFIG_CMDLINE_EDITING
Stefan Roese285e2662015-08-18 09:27:20 +0200151#define CONFIG_AUTO_COMPLETE
Stefan Roese995b72d2012-05-30 22:59:08 +0000152#define CONFIG_SYS_CBSIZE 256
153#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
154 sizeof(CONFIG_SYS_PROMPT) + 16)
155#define CONFIG_SYS_MAXARGS 16
156#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
157#define CONFIG_SYS_LOAD_ADDR 0x00800000
Stefan Roese995b72d2012-05-30 22:59:08 +0000158
159/* Use last 2 lwords in internal SRAM for bootcounter */
160#define CONFIG_BOOTCOUNT_LIMIT
Stefan Roese2fbdbda2015-08-18 09:27:17 +0200161#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SRAM_BASE + \
162 CONFIG_SRAM_SIZE)
Stefan Roese995b72d2012-05-30 22:59:08 +0000163
164#define CONFIG_HOSTNAME x600
165#define CONFIG_UBI_PART ubi0
166#define CONFIG_UBIFS_VOLUME rootfs
167
Stefan Roese995b72d2012-05-30 22:59:08 +0000168#define MTDIDS_DEFAULT "nand0=nand"
169#define MTDPARTS_DEFAULT "mtdparts=nand:64M(ubi0),64M(ubi1)"
170
171#define CONFIG_EXTRA_ENV_SETTINGS \
172 "u-boot_addr=1000000\0" \
Anatolij Gustschin4a8c3f62014-10-24 20:13:51 +0200173 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.spr\0" \
Stefan Roese995b72d2012-05-30 22:59:08 +0000174 "load=tftp ${u-boot_addr} ${u-boot}\0" \
Anatolij Gustschin4a8c3f62014-10-24 20:13:51 +0200175 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
176 " +${filesize};" \
177 "erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \
178 "cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \
Stefan Roese995b72d2012-05-30 22:59:08 +0000179 " ${filesize};" \
Anatolij Gustschin4a8c3f62014-10-24 20:13:51 +0200180 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
Stefan Roese995b72d2012-05-30 22:59:08 +0000181 " +${filesize}\0" \
182 "upd=run load update\0" \
Anatolij Gustschin4a8c3f62014-10-24 20:13:51 +0200183 "ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0" \
184 "part=" __stringify(CONFIG_UBI_PART) "\0" \
185 "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \
Stefan Roese995b72d2012-05-30 22:59:08 +0000186 "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \
187 "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \
188 " ${filesize}\0" \
189 "upd_ubifs=run load_ubifs update_ubifs\0" \
190 "init_ubifs=nand erase.part ubi0;ubi part ${part};" \
191 "ubi create ${vol} 4000000\0" \
192 "netdev=eth0\0" \
193 "rootpath=/opt/eldk-4.2/arm\0" \
194 "nfsargs=setenv bootargs root=/dev/nfs rw " \
195 "nfsroot=${serverip}:${rootpath}\0" \
196 "ramargs=setenv bootargs root=/dev/ram rw\0" \
197 "boot_part=0\0" \
198 "altbootcmd=if test $boot_part -eq 0;then " \
199 "echo Switching to partition 1!;" \
200 "setenv boot_part 1;" \
201 "else; " \
202 "echo Switching to partition 0!;" \
203 "setenv boot_part 0;" \
204 "fi;" \
205 "saveenv;boot\0" \
206 "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \
207 "root=ubi0:rootfs rootfstype=ubifs\0" \
Anatolij Gustschin4a8c3f62014-10-24 20:13:51 +0200208 "kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
Stefan Roese995b72d2012-05-30 22:59:08 +0000209 "kernel_fs=/boot/uImage \0" \
210 "kernel_addr=1000000\0" \
Anatolij Gustschin4a8c3f62014-10-24 20:13:51 +0200211 "dtb=" __stringify(CONFIG_HOSTNAME) "/" \
212 __stringify(CONFIG_HOSTNAME) ".dtb\0" \
213 "dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0" \
Stefan Roese995b72d2012-05-30 22:59:08 +0000214 "dtb_addr=1800000\0" \
215 "load_kernel=tftp ${kernel_addr} ${kernel}\0" \
216 "load_dtb=tftp ${dtb_addr} ${dtb}\0" \
217 "addip=setenv bootargs ${bootargs} " \
218 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
219 ":${hostname}:${netdev}:off panic=1\0" \
220 "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \
221 "${baudrate}\0" \
222 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
223 "net_nfs=run load_dtb load_kernel; " \
224 "run nfsargs addip addcon addmtd addmisc;" \
225 "bootm ${kernel_addr} - ${dtb_addr}\0" \
226 "mtdids=" MTDIDS_DEFAULT "\0" \
227 "mtdparts=" MTDPARTS_DEFAULT "\0" \
228 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \
229 " addcon addmisc addmtd;" \
230 "bootm ${kernel_addr} - ${dtb_addr}\0" \
Joe Hershberger949a7712012-11-01 16:54:18 +0000231 "ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \
Stefan Roese995b72d2012-05-30 22:59:08 +0000232 "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \
233 "ubifsload ${dtb_addr} ${dtb_fs};\0" \
234 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \
235 "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \
236 "bootcmd=run nand_ubifs\0" \
237 "\0"
238
Stefan Roese995b72d2012-05-30 22:59:08 +0000239/* Physical Memory Map */
240#define CONFIG_NR_DRAM_BANKS 1
241#define PHYS_SDRAM_1 0x00000000
242#define PHYS_SDRAM_1_MAXSIZE 0x40000000
243
244#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Stefan Roese2fbdbda2015-08-18 09:27:17 +0200245#define CONFIG_SRAM_BASE 0xd2800000
246/* Preserve the last 2 lwords for the boot-counter */
247#define CONFIG_SRAM_SIZE ((8 << 10) - 0x8)
248#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SRAM_BASE
249#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SRAM_SIZE
Stefan Roese995b72d2012-05-30 22:59:08 +0000250
251#define CONFIG_SYS_INIT_SP_OFFSET \
252 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
253
254#define CONFIG_SYS_INIT_SP_ADDR \
255 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
256
257/*
258 * SPL related defines
259 */
Stefan Roese2fbdbda2015-08-18 09:27:17 +0200260#define CONFIG_SPL_TEXT_BASE 0xd2800b00
261#define CONFIG_SPL_MAX_SIZE (CONFIG_SRAM_SIZE - 0xb00)
Stefan Roese995b72d2012-05-30 22:59:08 +0000262#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear"
263#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds"
264
Stefan Roese2fbdbda2015-08-18 09:27:17 +0200265#define CONFIG_SPL_FRAMEWORK
Stefan Roese995b72d2012-05-30 22:59:08 +0000266
267/*
268 * Please select/define only one of the following
269 * Each definition corresponds to a supported DDR chip.
270 * DDR configuration is based on the following selection
271 */
272#define CONFIG_DDR_MT47H64M16 1
273#define CONFIG_DDR_MT47H32M16 0
274#define CONFIG_DDR_MT47H128M8 0
275
276/*
277 * Synchronous/Asynchronous operation of DDR
278 *
279 * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation
280 * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation
281 * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation
282 */
283#define CONFIG_DDR_2HCLK 1
284#define CONFIG_DDR_HCLK 0
285#define CONFIG_DDR_PLL2 0
286
287/*
288 * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported
289 * or not. Modify/Add to only these macros to define new boot types
290 */
291#define USB_BOOT_SUPPORTED 0
292#define PCIE_BOOT_SUPPORTED 0
293#define SNOR_BOOT_SUPPORTED 1
294#define NAND_BOOT_SUPPORTED 1
295#define PNOR_BOOT_SUPPORTED 0
296#define TFTP_BOOT_SUPPORTED 0
297#define UART_BOOT_SUPPORTED 0
298#define SPI_BOOT_SUPPORTED 0
299#define I2C_BOOT_SUPPORTED 0
300#define MMC_BOOT_SUPPORTED 0
301
302#endif /* __CONFIG_H */