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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / c6435c317a7853fdde20a67af01e810a87e3d989 / . / drivers / pinctrl / renesas / pfc-r8a77965.c
blob: aeabda12ac934f208ef15f68eca29b75ce18e483 [file] [log] [blame]
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * R8A77965 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 * Copyright (C) 2016 Renesas Electronics Corp.
7 *
8 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
9 *
10 * R-Car Gen3 processor support - PFC hardware block.
11 *
12 * Copyright (C) 2015 Renesas Electronics Corporation
13 */
14
15#include <common.h>
16#include <dm.h>
17#include <errno.h>
18#include <dm/pinctrl.h>
19#include <linux/kernel.h>
20
21#include "sh_pfc.h"
22
23#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
24 SH_PFC_PIN_CFG_PULL_UP | \
25 SH_PFC_PIN_CFG_PULL_DOWN)
26
27#define CPU_ALL_PORT(fn, sfx) \
28 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
32 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
36 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
37 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
38 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
39 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
40/*
41 * F_() : just information
42 * FM() : macro for FN_xxx / xxx_MARK
43 */
44
45/* GPSR0 */
46#define GPSR0_15 F_(D15, IP7_11_8)
47#define GPSR0_14 F_(D14, IP7_7_4)
48#define GPSR0_13 F_(D13, IP7_3_0)
49#define GPSR0_12 F_(D12, IP6_31_28)
50#define GPSR0_11 F_(D11, IP6_27_24)
51#define GPSR0_10 F_(D10, IP6_23_20)
52#define GPSR0_9 F_(D9, IP6_19_16)
53#define GPSR0_8 F_(D8, IP6_15_12)
54#define GPSR0_7 F_(D7, IP6_11_8)
55#define GPSR0_6 F_(D6, IP6_7_4)
56#define GPSR0_5 F_(D5, IP6_3_0)
57#define GPSR0_4 F_(D4, IP5_31_28)
58#define GPSR0_3 F_(D3, IP5_27_24)
59#define GPSR0_2 F_(D2, IP5_23_20)
60#define GPSR0_1 F_(D1, IP5_19_16)
61#define GPSR0_0 F_(D0, IP5_15_12)
62
63/* GPSR1 */
64#define GPSR1_28 FM(CLKOUT)
65#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
66#define GPSR1_26 F_(WE1_N, IP5_7_4)
67#define GPSR1_25 F_(WE0_N, IP5_3_0)
68#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
69#define GPSR1_23 F_(RD_N, IP4_27_24)
70#define GPSR1_22 F_(BS_N, IP4_23_20)
71#define GPSR1_21 F_(CS1_N, IP4_19_16)
72#define GPSR1_20 F_(CS0_N, IP4_15_12)
73#define GPSR1_19 F_(A19, IP4_11_8)
74#define GPSR1_18 F_(A18, IP4_7_4)
75#define GPSR1_17 F_(A17, IP4_3_0)
76#define GPSR1_16 F_(A16, IP3_31_28)
77#define GPSR1_15 F_(A15, IP3_27_24)
78#define GPSR1_14 F_(A14, IP3_23_20)
79#define GPSR1_13 F_(A13, IP3_19_16)
80#define GPSR1_12 F_(A12, IP3_15_12)
81#define GPSR1_11 F_(A11, IP3_11_8)
82#define GPSR1_10 F_(A10, IP3_7_4)
83#define GPSR1_9 F_(A9, IP3_3_0)
84#define GPSR1_8 F_(A8, IP2_31_28)
85#define GPSR1_7 F_(A7, IP2_27_24)
86#define GPSR1_6 F_(A6, IP2_23_20)
87#define GPSR1_5 F_(A5, IP2_19_16)
88#define GPSR1_4 F_(A4, IP2_15_12)
89#define GPSR1_3 F_(A3, IP2_11_8)
90#define GPSR1_2 F_(A2, IP2_7_4)
91#define GPSR1_1 F_(A1, IP2_3_0)
92#define GPSR1_0 F_(A0, IP1_31_28)
93
94/* GPSR2 */
95#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
96#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
97#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
98#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
99#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
100#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
101#define GPSR2_8 F_(PWM2_A, IP1_27_24)
102#define GPSR2_7 F_(PWM1_A, IP1_23_20)
103#define GPSR2_6 F_(PWM0, IP1_19_16)
104#define GPSR2_5 F_(IRQ5, IP1_15_12)
105#define GPSR2_4 F_(IRQ4, IP1_11_8)
106#define GPSR2_3 F_(IRQ3, IP1_7_4)
107#define GPSR2_2 F_(IRQ2, IP1_3_0)
108#define GPSR2_1 F_(IRQ1, IP0_31_28)
109#define GPSR2_0 F_(IRQ0, IP0_27_24)
110
111/* GPSR3 */
112#define GPSR3_15 F_(SD1_WP, IP11_23_20)
113#define GPSR3_14 F_(SD1_CD, IP11_19_16)
114#define GPSR3_13 F_(SD0_WP, IP11_15_12)
115#define GPSR3_12 F_(SD0_CD, IP11_11_8)
116#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
117#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
118#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
119#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
120#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
121#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
122#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
123#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
124#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
125#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
126#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
127#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
128
129/* GPSR4 */
130#define GPSR4_17 F_(SD3_DS, IP11_7_4)
131#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
132#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
133#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
134#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
135#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
136#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
137#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
138#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
139#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
140#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
141#define GPSR4_6 F_(SD2_DS, IP9_27_24)
142#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
143#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
144#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
145#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
146#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
147#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
148
149/* GPSR5 */
150#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
151#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
152#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
153#define GPSR5_22 FM(MSIOF0_RXD)
154#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
155#define GPSR5_20 FM(MSIOF0_TXD)
156#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
157#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
158#define GPSR5_17 FM(MSIOF0_SCK)
159#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
160#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
161#define GPSR5_14 F_(HTX0, IP13_19_16)
162#define GPSR5_13 F_(HRX0, IP13_15_12)
163#define GPSR5_12 F_(HSCK0, IP13_11_8)
164#define GPSR5_11 F_(RX2_A, IP13_7_4)
165#define GPSR5_10 F_(TX2_A, IP13_3_0)
166#define GPSR5_9 F_(SCK2, IP12_31_28)
167#define GPSR5_8 F_(RTS1_N, IP12_27_24)
168#define GPSR5_7 F_(CTS1_N, IP12_23_20)
169#define GPSR5_6 F_(TX1_A, IP12_19_16)
170#define GPSR5_5 F_(RX1_A, IP12_15_12)
171#define GPSR5_4 F_(RTS0_N, IP12_11_8)
172#define GPSR5_3 F_(CTS0_N, IP12_7_4)
173#define GPSR5_2 F_(TX0, IP12_3_0)
174#define GPSR5_1 F_(RX0, IP11_31_28)
175#define GPSR5_0 F_(SCK0, IP11_27_24)
176
177/* GPSR6 */
178#define GPSR6_31 F_(GP6_31, IP18_7_4)
179#define GPSR6_30 F_(GP6_30, IP18_3_0)
180#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
181#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
182#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
183#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
184#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
185#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
186#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
187#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
188#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
189#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
190#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
191#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
192#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
193#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
194#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
195#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
196#define GPSR6_13 FM(SSI_SDATA5)
197#define GPSR6_12 FM(SSI_WS5)
198#define GPSR6_11 FM(SSI_SCK5)
199#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
200#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
201#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
202#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
203#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
204#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
205#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
206#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
207#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
208#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
209#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
210
211/* GPSR7 */
212#define GPSR7_3 FM(GP7_03)
213#define GPSR7_2 FM(HDMI0_CEC)
214#define GPSR7_1 FM(AVS2)
215#define GPSR7_0 FM(AVS1)
216
217
218/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
219#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246
247/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
248#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277
278/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
279#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313
314/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
315#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
336#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343
344/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
345#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
365#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
366#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
367#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
368#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
369#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
371#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
372
373#define PINMUX_GPSR \
374\
375 GPSR6_31 \
376 GPSR6_30 \
377 GPSR6_29 \
378 GPSR1_28 GPSR6_28 \
379 GPSR1_27 GPSR6_27 \
380 GPSR1_26 GPSR6_26 \
381 GPSR1_25 GPSR5_25 GPSR6_25 \
382 GPSR1_24 GPSR5_24 GPSR6_24 \
383 GPSR1_23 GPSR5_23 GPSR6_23 \
384 GPSR1_22 GPSR5_22 GPSR6_22 \
385 GPSR1_21 GPSR5_21 GPSR6_21 \
386 GPSR1_20 GPSR5_20 GPSR6_20 \
387 GPSR1_19 GPSR5_19 GPSR6_19 \
388 GPSR1_18 GPSR5_18 GPSR6_18 \
389 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
390 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
391GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
392GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
393GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
394GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
395GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
396GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
397GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
398GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
399GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
400GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
401GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
402GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
403GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
404GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
405GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
406GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
407
408#define PINMUX_IPSR \
409\
410FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
411FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
412FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
413FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
414FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
415FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
416FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
417FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
418\
419FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
420FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
421FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
422FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
423FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
424FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
425FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
426FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
427\
428FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
429FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
430FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
431FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
432FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
433FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
434FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
435FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
436\
437FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
438FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
439FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
440FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
441FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
442FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
443FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
444FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
445\
446FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
447FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
448FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
449FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
450FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
451FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
452FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
453FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
454
455/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
456#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
457#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
458#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
459#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
460#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
461#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
462#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
463#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
464#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
465#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
466#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
467#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
468#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
469#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
470#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
471#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
472#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
473#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
474
475/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
476#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
477#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
478#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
479#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
480#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
481#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
482#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
483#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
484#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
485#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
486#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
487#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
488#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
489#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
490#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
491#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
492#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
493#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
494#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
495#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
496#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
497#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
498
499/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
500#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
501#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
502#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
503#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
504#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
505#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
506#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
507#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
508#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
509#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
510#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
511#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
512#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
513
514#define PINMUX_MOD_SELS \
515\
516MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
517 MOD_SEL2_30 \
518 MOD_SEL1_29_28_27 MOD_SEL2_29 \
519MOD_SEL0_28_27 MOD_SEL2_28_27 \
520MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
521 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
522MOD_SEL0_23 MOD_SEL1_23_22_21 \
523MOD_SEL0_22 MOD_SEL2_22 \
524MOD_SEL0_21 MOD_SEL2_21 \
525MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
526MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
527MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
528 MOD_SEL2_17 \
529MOD_SEL0_16 MOD_SEL1_16 \
530 MOD_SEL1_15_14 \
531MOD_SEL0_14_13 \
532 MOD_SEL1_13 \
533MOD_SEL0_12 MOD_SEL1_12 \
534MOD_SEL0_11 MOD_SEL1_11 \
535MOD_SEL0_10 MOD_SEL1_10 \
536MOD_SEL0_9_8 MOD_SEL1_9 \
537MOD_SEL0_7_6 \
538 MOD_SEL1_6 \
539MOD_SEL0_5 MOD_SEL1_5 \
540MOD_SEL0_4_3 MOD_SEL1_4 \
541 MOD_SEL1_3 \
542 MOD_SEL1_2 \
543 MOD_SEL1_1 \
544 MOD_SEL1_0 MOD_SEL2_0
545
546/*
547 * These pins are not able to be muxed but have other properties
548 * that can be set, such as drive-strength or pull-up/pull-down enable.
549 */
550#define PINMUX_STATIC \
551 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
552 FM(QSPI0_IO2) FM(QSPI0_IO3) \
553 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
554 FM(QSPI1_IO2) FM(QSPI1_IO3) \
555 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
556 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
557 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
558 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
559 FM(PRESETOUT) \
560 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
561 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
562
563enum {
564 PINMUX_RESERVED = 0,
565
566 PINMUX_DATA_BEGIN,
567 GP_ALL(DATA),
568 PINMUX_DATA_END,
569
570#define F_(x, y)
571#define FM(x) FN_##x,
572 PINMUX_FUNCTION_BEGIN,
573 GP_ALL(FN),
574 PINMUX_GPSR
575 PINMUX_IPSR
576 PINMUX_MOD_SELS
577 PINMUX_FUNCTION_END,
578#undef F_
579#undef FM
580
581#define F_(x, y)
582#define FM(x) x##_MARK,
583 PINMUX_MARK_BEGIN,
584 PINMUX_GPSR
585 PINMUX_IPSR
586 PINMUX_MOD_SELS
587 PINMUX_STATIC
588 PINMUX_MARK_END,
589#undef F_
590#undef FM
591};
592
593static const u16 pinmux_data[] = {
594 PINMUX_DATA_GP_ALL(),
595
596 PINMUX_SINGLE(AVS1),
597 PINMUX_SINGLE(AVS2),
598 PINMUX_SINGLE(CLKOUT),
599 PINMUX_SINGLE(GP7_03),
600 PINMUX_SINGLE(HDMI0_CEC),
601 PINMUX_SINGLE(MSIOF0_RXD),
602 PINMUX_SINGLE(MSIOF0_SCK),
603 PINMUX_SINGLE(MSIOF0_TXD),
604 PINMUX_SINGLE(SSI_SCK5),
605 PINMUX_SINGLE(SSI_SDATA5),
606 PINMUX_SINGLE(SSI_WS5),
607
608 /* IPSR0 */
609 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
610 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
611
612 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
613 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
614 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
615
616 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
617 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
618 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
619
620 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
621 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
622 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
623 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
624
625 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
626 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
627 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
628
629 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
630 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
631 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
632
633 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
634 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
635 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
636 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
637 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
638 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
639 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
640
641 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
642 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
643 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
644 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
645 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
646 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
647 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
648
649 /* IPSR1 */
650 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
651 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
652 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
653 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
654 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
655 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
656
657 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
658 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
659 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
660 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
661 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
662 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
663
664 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
665 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
666 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
667 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
668 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
669 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
670
671 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
672 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
673 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
674 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
675 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
676 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
677 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
678
679 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
680 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
681 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
682 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
683
684 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
685 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
686 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
687 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
688
689 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
690 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
691 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
692
693 PINMUX_IPSR_GPSR(IP1_31_28, A0),
694 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
695 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
696 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
697 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
698 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
699
700 /* IPSR2 */
701 PINMUX_IPSR_GPSR(IP2_3_0, A1),
702 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
703 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
704 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
705 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
706 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
707
708 PINMUX_IPSR_GPSR(IP2_7_4, A2),
709 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
710 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
711 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
712 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
713 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
714
715 PINMUX_IPSR_GPSR(IP2_11_8, A3),
716 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
717 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
718 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
719 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
720 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
721
722 PINMUX_IPSR_GPSR(IP2_15_12, A4),
723 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
724 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
725 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
726 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
727 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
728
729 PINMUX_IPSR_GPSR(IP2_19_16, A5),
730 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
731 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
732 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
733 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
734 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
735 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
736
737 PINMUX_IPSR_GPSR(IP2_23_20, A6),
738 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
739 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
740 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
741 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
742 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
743 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
744
745 PINMUX_IPSR_GPSR(IP2_27_24, A7),
746 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
747 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
748 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
749 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
750 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
751 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
752
753 PINMUX_IPSR_GPSR(IP2_31_28, A8),
754 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
755 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
756 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
757 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
758 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
759 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
760
761 /* IPSR3 */
762 PINMUX_IPSR_GPSR(IP3_3_0, A9),
763 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
764 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
765 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
766
767 PINMUX_IPSR_GPSR(IP3_7_4, A10),
768 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
769 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
770 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
771
772 PINMUX_IPSR_GPSR(IP3_11_8, A11),
773 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
774 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
775 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
776 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
777 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
778 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
779 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
780 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
781
782 PINMUX_IPSR_GPSR(IP3_15_12, A12),
783 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
784 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
785 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
786 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
787 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
788
789 PINMUX_IPSR_GPSR(IP3_19_16, A13),
790 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
791 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
792 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
793 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
794 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
795
796 PINMUX_IPSR_GPSR(IP3_23_20, A14),
797 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
798 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
799 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
800 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
801 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
802
803 PINMUX_IPSR_GPSR(IP3_27_24, A15),
804 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
805 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
806 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
807 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
808 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
809
810 PINMUX_IPSR_GPSR(IP3_31_28, A16),
811 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
812 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
813 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
814
815 /* IPSR4 */
816 PINMUX_IPSR_GPSR(IP4_3_0, A17),
817 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
818 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
819 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
820
821 PINMUX_IPSR_GPSR(IP4_7_4, A18),
822 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
823 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
824 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
825
826 PINMUX_IPSR_GPSR(IP4_11_8, A19),
827 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
828 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
829 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
830
831 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
832 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
833
834 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
835 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
836 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
837
838 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
839 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
840 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
841 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
842 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
843 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
844 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
845 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
846
847 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
848 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
849 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
850 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
851 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
852 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
853
854 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
855 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
856 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
857 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
858 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
859 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
860
861 /* IPSR5 */
862 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
863 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
864 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
865 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
866 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
867 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
868 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
869
870 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
871 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
872 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
873 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
874 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
875 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
876 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
877 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
878
879 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
880 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
881 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
882 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
883
884 PINMUX_IPSR_GPSR(IP5_15_12, D0),
885 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
886 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
887 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
888 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
889
890 PINMUX_IPSR_GPSR(IP5_19_16, D1),
891 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
892 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
893 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
894 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
895
896 PINMUX_IPSR_GPSR(IP5_23_20, D2),
897 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
898 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
899 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
900
901 PINMUX_IPSR_GPSR(IP5_27_24, D3),
902 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
903 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
904 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
905
906 PINMUX_IPSR_GPSR(IP5_31_28, D4),
907 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
908 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
909 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
910
911 /* IPSR6 */
912 PINMUX_IPSR_GPSR(IP6_3_0, D5),
913 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
914 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
915 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
916
917 PINMUX_IPSR_GPSR(IP6_7_4, D6),
918 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
919 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
920 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
921
922 PINMUX_IPSR_GPSR(IP6_11_8, D7),
923 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
924 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
925 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
926
927 PINMUX_IPSR_GPSR(IP6_15_12, D8),
928 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
929 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
930 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
931 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
932 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
933
934 PINMUX_IPSR_GPSR(IP6_19_16, D9),
935 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
936 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
937 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
938 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
939
940 PINMUX_IPSR_GPSR(IP6_23_20, D10),
941 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
942 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
943 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
944 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
945 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
946 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
947
948 PINMUX_IPSR_GPSR(IP6_27_24, D11),
949 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
950 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
951 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
952 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
953 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
954 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
955
956 PINMUX_IPSR_GPSR(IP6_31_28, D12),
957 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
958 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
959 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
960 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
961 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
962
963 /* IPSR7 */
964 PINMUX_IPSR_GPSR(IP7_3_0, D13),
965 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
966 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
967 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
968 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
969 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
970
971 PINMUX_IPSR_GPSR(IP7_7_4, D14),
972 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
973 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
974 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
975 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
976 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
977 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
978
979 PINMUX_IPSR_GPSR(IP7_11_8, D15),
980 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
981 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
982 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
983 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
984 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
985 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
986
987 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
988 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
989 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
990
991 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
992 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
993 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
994
995 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
996 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
997 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
998 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
999
1000 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1001 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1002 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1003 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1004
1005 /* IPSR8 */
1006 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1007 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1008 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1009 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1010
1011 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1012 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1013 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1014 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1015
1016 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1017 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1018 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1019
1020 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1021 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1022 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1),
1023 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1024 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1025
1026 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1027 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1028 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1029 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1),
1030 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1031 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1032
1033 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1034 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1035 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1036 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
1037 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1038 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1039
1040 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1041 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1042 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1043 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
1044 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1045 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1046
1047 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1048 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1049 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1050 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1),
1051 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1052 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1053
1054 /* IPSR9 */
1055 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1056 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1057
1058 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1059 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1060
1061 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1062 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1063
1064 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1065 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1066
1067 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1068 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1069
1070 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1071 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1072
1073 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1074 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1075 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
1076
1077 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1078 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1079
1080 /* IPSR10 */
1081 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1082 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1083
1084 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1085 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1086
1087 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1088 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1089
1090 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1091 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1092
1093 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1094 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1095
1096 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1097 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1098 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1099
1100 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1101 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1102 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1103
1104 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1105 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1106 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1107
1108 /* IPSR11 */
1109 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1110 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1111 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1112
1113 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1114 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1115
1116 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1117 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0),
1118 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1119 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1120
1121 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1122 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0),
1123 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1124
1125 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
1126 PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDFC_0),
1127 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1128
1129 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
1130 PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDFC_0),
1131 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
1132
1133 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1134 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1135 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1136 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
1137 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1138 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1139 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1140 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1141 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1142 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1143
1144 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1145 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1146 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1147 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1148 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1149
1150 /* IPSR12 */
1151 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1152 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1153 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1154 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1155 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1156
1157 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1158 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1159 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1160 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1161 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1162 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1163 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1164 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1165
1166 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
1167 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1168 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1169 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
1170 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1171 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1172 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1173 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1174
1175 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1176 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1177 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1178 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1179 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1180
1181 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1182 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1183 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1184 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1185 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1186
1187 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1188 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1189 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1190 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1191 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1192 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1193 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1194
1195 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
1196 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1197 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1198 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1199 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1200 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1201 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1202
1203 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1204 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1205 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1206 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1207 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1208 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1209 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1210
1211 /* IPSR13 */
1212 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1213 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1214 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1215 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1216 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1217 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1218
1219 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1220 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1221 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1222 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1223 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1224 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1225
1226 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1227 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1228 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
1229 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
1230 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1231 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1232 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1233 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1234
1235 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1236 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1237 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
1238 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1239 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1240 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1241
1242 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1243 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1244 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
1245 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1246 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1247 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1248
1249 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1250 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1251 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1252 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
1253 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1254 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1255 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1256 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1257
1258 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1259 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1260 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1261 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
1262 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1263 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1264 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1265
1266 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1267 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1268 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1269 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1270
1271 /* IPSR14 */
1272 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1273 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1274 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0),
1275 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
1276 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
1277 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1278 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1279 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1280
1281 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1282 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1283 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1284 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
1285 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
1286 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1287 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1288 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1289
1290 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1291 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1292 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1293
1294 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1295 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1296 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1297 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1298
1299 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1300 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1301 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1302
1303 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1304 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1305
1306 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1307 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1308
1309 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1310 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1311
1312 /* IPSR15 */
1313 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
1314
1315 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1316 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
1317
1318 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1319 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1320 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1321
1322 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1323 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1324 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1325 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1326
1327 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1328 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1329 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1330 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1331 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1332 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1333 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1334
1335 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1336 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1337 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1338 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1339 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1340 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1341 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1342
1343 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1344 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1345 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1346 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1347 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1348 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1349 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1350
1351 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1352 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1353 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1354 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1355 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1356 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1357 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1358
1359 /* IPSR16 */
1360 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1361 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1362
1363 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1364 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1365
1366 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1367 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1368 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1369
1370 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1371 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1372 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1373 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1374 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1375 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1376 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1377
1378 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1379 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1380 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1381 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1382 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1383 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1384 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1385
1386 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1387 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1388 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1389 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1390 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1391 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1392 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1393 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1394
1395 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1396 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1397 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1398 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1399 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1400 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1401 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1402
1403 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
1404 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1405 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1406 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1407 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
1408 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1409 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1410 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1411
1412 /* IPSR17 */
1413 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1414 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1415
1416 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
1417 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1418 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1419 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1420 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1421
1422 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1423 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1424 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1425 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1426 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1427 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1428 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1429
1430 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1431 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1432 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1433 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1434 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1435 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1436
1437 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1438 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1439 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
1440 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1441 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1442 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1443 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1444 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1445 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1446
1447 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1448 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1449 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
1450 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1451 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1452 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1453 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1454 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1455 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1456
1457 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1458 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1459 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
1460 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1461 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1462 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1463 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1464 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1465 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1466 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1467 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1468
1469 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1470 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1471 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
1472 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1473 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1474 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1475 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1476 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1477 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1478
1479 /* IPSR18 */
1480 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
1481 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1482 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
1483 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1484 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1485 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1486 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1487 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1488 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1489
1490 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
1491 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1492 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
1493 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1494 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1495 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1496 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1497 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1498 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1499
1500 /* I2C */
1501 PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
1502 PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
1503 PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
1504
1505/*
1506 * Static pins can not be muxed between different functions but
1507 * still need mark entries in the pinmux list. Add each static
1508 * pin to the list without an associated function. The sh-pfc
1509 * core will do the right thing and skip trying to mux the pin
1510 * while still applying configuration to it.
1511 */
1512#define FM(x) PINMUX_DATA(x##_MARK, 0),
1513 PINMUX_STATIC
1514#undef FM
1515};
1516
1517/*
1518 * R8A77965 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1519 * Physical layout rows: A - AW, cols: 1 - 39.
1520 */
1521#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1522#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1523#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1524#define PIN_NONE U16_MAX
1525
1526static const struct sh_pfc_pin pinmux_pins[] = {
1527 PINMUX_GPIO_GP_ALL(),
1528
1529 /*
1530 * Pins not associated with a GPIO port.
1531 *
1532 * The pin positions are different between different r8a77965
1533 * packages, all that is needed for the pfc driver is a unique
1534 * number for each pin. To this end use the pin layout from
1535 * R-Car M3SiP to calculate a unique number for each pin.
1536 */
1537 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS),
1573 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1574 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1575 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1576 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1577 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1578 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1579};
1580
1581/* - AUDIO CLOCK ------------------------------------------------------------ */
1582static const unsigned int audio_clk_a_a_pins[] = {
1583 /* CLK A */
1584 RCAR_GP_PIN(6, 22),
1585};
1586static const unsigned int audio_clk_a_a_mux[] = {
1587 AUDIO_CLKA_A_MARK,
1588};
1589static const unsigned int audio_clk_a_b_pins[] = {
1590 /* CLK A */
1591 RCAR_GP_PIN(5, 4),
1592};
1593static const unsigned int audio_clk_a_b_mux[] = {
1594 AUDIO_CLKA_B_MARK,
1595};
1596static const unsigned int audio_clk_a_c_pins[] = {
1597 /* CLK A */
1598 RCAR_GP_PIN(5, 19),
1599};
1600static const unsigned int audio_clk_a_c_mux[] = {
1601 AUDIO_CLKA_C_MARK,
1602};
1603static const unsigned int audio_clk_b_a_pins[] = {
1604 /* CLK B */
1605 RCAR_GP_PIN(5, 12),
1606};
1607static const unsigned int audio_clk_b_a_mux[] = {
1608 AUDIO_CLKB_A_MARK,
1609};
1610static const unsigned int audio_clk_b_b_pins[] = {
1611 /* CLK B */
1612 RCAR_GP_PIN(6, 23),
1613};
1614static const unsigned int audio_clk_b_b_mux[] = {
1615 AUDIO_CLKB_B_MARK,
1616};
1617static const unsigned int audio_clk_c_a_pins[] = {
1618 /* CLK C */
1619 RCAR_GP_PIN(5, 21),
1620};
1621static const unsigned int audio_clk_c_a_mux[] = {
1622 AUDIO_CLKC_A_MARK,
1623};
1624static const unsigned int audio_clk_c_b_pins[] = {
1625 /* CLK C */
1626 RCAR_GP_PIN(5, 0),
1627};
1628static const unsigned int audio_clk_c_b_mux[] = {
1629 AUDIO_CLKC_B_MARK,
1630};
1631static const unsigned int audio_clkout_a_pins[] = {
1632 /* CLKOUT */
1633 RCAR_GP_PIN(5, 18),
1634};
1635static const unsigned int audio_clkout_a_mux[] = {
1636 AUDIO_CLKOUT_A_MARK,
1637};
1638static const unsigned int audio_clkout_b_pins[] = {
1639 /* CLKOUT */
1640 RCAR_GP_PIN(6, 28),
1641};
1642static const unsigned int audio_clkout_b_mux[] = {
1643 AUDIO_CLKOUT_B_MARK,
1644};
1645static const unsigned int audio_clkout_c_pins[] = {
1646 /* CLKOUT */
1647 RCAR_GP_PIN(5, 3),
1648};
1649static const unsigned int audio_clkout_c_mux[] = {
1650 AUDIO_CLKOUT_C_MARK,
1651};
1652static const unsigned int audio_clkout_d_pins[] = {
1653 /* CLKOUT */
1654 RCAR_GP_PIN(5, 21),
1655};
1656static const unsigned int audio_clkout_d_mux[] = {
1657 AUDIO_CLKOUT_D_MARK,
1658};
1659static const unsigned int audio_clkout1_a_pins[] = {
1660 /* CLKOUT1 */
1661 RCAR_GP_PIN(5, 15),
1662};
1663static const unsigned int audio_clkout1_a_mux[] = {
1664 AUDIO_CLKOUT1_A_MARK,
1665};
1666static const unsigned int audio_clkout1_b_pins[] = {
1667 /* CLKOUT1 */
1668 RCAR_GP_PIN(6, 29),
1669};
1670static const unsigned int audio_clkout1_b_mux[] = {
1671 AUDIO_CLKOUT1_B_MARK,
1672};
1673static const unsigned int audio_clkout2_a_pins[] = {
1674 /* CLKOUT2 */
1675 RCAR_GP_PIN(5, 16),
1676};
1677static const unsigned int audio_clkout2_a_mux[] = {
1678 AUDIO_CLKOUT2_A_MARK,
1679};
1680static const unsigned int audio_clkout2_b_pins[] = {
1681 /* CLKOUT2 */
1682 RCAR_GP_PIN(6, 30),
1683};
1684static const unsigned int audio_clkout2_b_mux[] = {
1685 AUDIO_CLKOUT2_B_MARK,
1686};
1687
1688static const unsigned int audio_clkout3_a_pins[] = {
1689 /* CLKOUT3 */
1690 RCAR_GP_PIN(5, 19),
1691};
1692static const unsigned int audio_clkout3_a_mux[] = {
1693 AUDIO_CLKOUT3_A_MARK,
1694};
1695static const unsigned int audio_clkout3_b_pins[] = {
1696 /* CLKOUT3 */
1697 RCAR_GP_PIN(6, 31),
1698};
1699static const unsigned int audio_clkout3_b_mux[] = {
1700 AUDIO_CLKOUT3_B_MARK,
1701};
1702
1703/* - EtherAVB --------------------------------------------------------------- */
1704static const unsigned int avb_link_pins[] = {
1705 /* AVB_LINK */
1706 RCAR_GP_PIN(2, 12),
1707};
1708static const unsigned int avb_link_mux[] = {
1709 AVB_LINK_MARK,
1710};
1711static const unsigned int avb_magic_pins[] = {
1712 /* AVB_MAGIC_ */
1713 RCAR_GP_PIN(2, 10),
1714};
1715static const unsigned int avb_magic_mux[] = {
1716 AVB_MAGIC_MARK,
1717};
1718static const unsigned int avb_phy_int_pins[] = {
1719 /* AVB_PHY_INT */
1720 RCAR_GP_PIN(2, 11),
1721};
1722static const unsigned int avb_phy_int_mux[] = {
1723 AVB_PHY_INT_MARK,
1724};
1725static const unsigned int avb_mdio_pins[] = {
1726 /* AVB_MDC, AVB_MDIO */
1727 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1728};
1729static const unsigned int avb_mdio_mux[] = {
1730 AVB_MDC_MARK, AVB_MDIO_MARK,
1731};
1732static const unsigned int avb_mii_pins[] = {
1733 /*
1734 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1735 * AVB_TD1, AVB_TD2, AVB_TD3,
1736 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1737 * AVB_RD1, AVB_RD2, AVB_RD3,
1738 * AVB_TXCREFCLK
1739 */
1740 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1741 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1742 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1743 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1744 PIN_NUMBER('A', 12),
1745
1746};
1747static const unsigned int avb_mii_mux[] = {
1748 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1749 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1750 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1751 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1752 AVB_TXCREFCLK_MARK,
1753};
1754static const unsigned int avb_avtp_pps_pins[] = {
1755 /* AVB_AVTP_PPS */
1756 RCAR_GP_PIN(2, 6),
1757};
1758static const unsigned int avb_avtp_pps_mux[] = {
1759 AVB_AVTP_PPS_MARK,
1760};
1761static const unsigned int avb_avtp_match_a_pins[] = {
1762 /* AVB_AVTP_MATCH_A */
1763 RCAR_GP_PIN(2, 13),
1764};
1765static const unsigned int avb_avtp_match_a_mux[] = {
1766 AVB_AVTP_MATCH_A_MARK,
1767};
1768static const unsigned int avb_avtp_capture_a_pins[] = {
1769 /* AVB_AVTP_CAPTURE_A */
1770 RCAR_GP_PIN(2, 14),
1771};
1772static const unsigned int avb_avtp_capture_a_mux[] = {
1773 AVB_AVTP_CAPTURE_A_MARK,
1774};
1775static const unsigned int avb_avtp_match_b_pins[] = {
1776 /* AVB_AVTP_MATCH_B */
1777 RCAR_GP_PIN(1, 8),
1778};
1779static const unsigned int avb_avtp_match_b_mux[] = {
1780 AVB_AVTP_MATCH_B_MARK,
1781};
1782static const unsigned int avb_avtp_capture_b_pins[] = {
1783 /* AVB_AVTP_CAPTURE_B */
1784 RCAR_GP_PIN(1, 11),
1785};
1786static const unsigned int avb_avtp_capture_b_mux[] = {
1787 AVB_AVTP_CAPTURE_B_MARK,
1788};
1789
1790/* - CAN ------------------------------------------------------------------ */
1791static const unsigned int can0_data_a_pins[] = {
1792 /* TX, RX */
1793 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1794};
1795
1796static const unsigned int can0_data_a_mux[] = {
1797 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1798};
1799
1800static const unsigned int can0_data_b_pins[] = {
1801 /* TX, RX */
1802 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1803};
1804
1805static const unsigned int can0_data_b_mux[] = {
1806 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1807};
1808
1809static const unsigned int can1_data_pins[] = {
1810 /* TX, RX */
1811 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1812};
1813
1814static const unsigned int can1_data_mux[] = {
1815 CAN1_TX_MARK, CAN1_RX_MARK,
1816};
1817
1818/* - CAN Clock -------------------------------------------------------------- */
1819static const unsigned int can_clk_pins[] = {
1820 /* CLK */
1821 RCAR_GP_PIN(1, 25),
1822};
1823
1824static const unsigned int can_clk_mux[] = {
1825 CAN_CLK_MARK,
1826};
1827
1828/* - CAN FD --------------------------------------------------------------- */
1829static const unsigned int canfd0_data_a_pins[] = {
1830 /* TX, RX */
1831 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1832};
1833
1834static const unsigned int canfd0_data_a_mux[] = {
1835 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1836};
1837
1838static const unsigned int canfd0_data_b_pins[] = {
1839 /* TX, RX */
1840 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1841};
1842
1843static const unsigned int canfd0_data_b_mux[] = {
1844 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1845};
1846
1847static const unsigned int canfd1_data_pins[] = {
1848 /* TX, RX */
1849 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1850};
1851
1852static const unsigned int canfd1_data_mux[] = {
1853 CANFD1_TX_MARK, CANFD1_RX_MARK,
1854};
1855
1856/* - DU --------------------------------------------------------------------- */
1857static const unsigned int du_rgb666_pins[] = {
1858 /* R[7:2], G[7:2], B[7:2] */
1859 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1860 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1861 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1862 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1863 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1864 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1865};
1866
1867static const unsigned int du_rgb666_mux[] = {
1868 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1869 DU_DR3_MARK, DU_DR2_MARK,
1870 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1871 DU_DG3_MARK, DU_DG2_MARK,
1872 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1873 DU_DB3_MARK, DU_DB2_MARK,
1874};
1875
1876static const unsigned int du_rgb888_pins[] = {
1877 /* R[7:0], G[7:0], B[7:0] */
1878 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1879 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1880 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
1881 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1882 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1883 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1884 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1885 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1886 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
1887};
1888
1889static const unsigned int du_rgb888_mux[] = {
1890 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1891 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
1892 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1893 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
1894 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1895 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
1896};
1897
1898static const unsigned int du_clk_out_0_pins[] = {
1899 /* CLKOUT */
1900 RCAR_GP_PIN(1, 27),
1901};
1902
1903static const unsigned int du_clk_out_0_mux[] = {
1904 DU_DOTCLKOUT0_MARK
1905};
1906
1907static const unsigned int du_clk_out_1_pins[] = {
1908 /* CLKOUT */
1909 RCAR_GP_PIN(2, 3),
1910};
1911
1912static const unsigned int du_clk_out_1_mux[] = {
1913 DU_DOTCLKOUT1_MARK
1914};
1915
1916static const unsigned int du_sync_pins[] = {
1917 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1918 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
1919};
1920
1921static const unsigned int du_sync_mux[] = {
1922 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
1923};
1924
1925static const unsigned int du_oddf_pins[] = {
1926 /* EXDISP/EXODDF/EXCDE */
1927 RCAR_GP_PIN(2, 2),
1928};
1929
1930static const unsigned int du_oddf_mux[] = {
1931 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
1932};
1933
1934static const unsigned int du_cde_pins[] = {
1935 /* CDE */
1936 RCAR_GP_PIN(2, 0),
1937};
1938
1939static const unsigned int du_cde_mux[] = {
1940 DU_CDE_MARK,
1941};
1942
1943static const unsigned int du_disp_pins[] = {
1944 /* DISP */
1945 RCAR_GP_PIN(2, 1),
1946};
1947
1948static const unsigned int du_disp_mux[] = {
1949 DU_DISP_MARK,
1950};
1951
1952/* - HSCIF0 ----------------------------------------------------------------- */
1953static const unsigned int hscif0_data_pins[] = {
1954 /* RX, TX */
1955 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1956};
1957
1958static const unsigned int hscif0_data_mux[] = {
1959 HRX0_MARK, HTX0_MARK,
1960};
1961
1962static const unsigned int hscif0_clk_pins[] = {
1963 /* SCK */
1964 RCAR_GP_PIN(5, 12),
1965};
1966
1967static const unsigned int hscif0_clk_mux[] = {
1968 HSCK0_MARK,
1969};
1970
1971static const unsigned int hscif0_ctrl_pins[] = {
1972 /* RTS, CTS */
1973 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
1974};
1975
1976static const unsigned int hscif0_ctrl_mux[] = {
1977 HRTS0_N_MARK, HCTS0_N_MARK,
1978};
1979
1980/* - HSCIF1 ----------------------------------------------------------------- */
1981static const unsigned int hscif1_data_a_pins[] = {
1982 /* RX, TX */
1983 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
1984};
1985
1986static const unsigned int hscif1_data_a_mux[] = {
1987 HRX1_A_MARK, HTX1_A_MARK,
1988};
1989
1990static const unsigned int hscif1_clk_a_pins[] = {
1991 /* SCK */
1992 RCAR_GP_PIN(6, 21),
1993};
1994
1995static const unsigned int hscif1_clk_a_mux[] = {
1996 HSCK1_A_MARK,
1997};
1998
1999static const unsigned int hscif1_ctrl_a_pins[] = {
2000 /* RTS, CTS */
2001 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2002};
2003
2004static const unsigned int hscif1_ctrl_a_mux[] = {
2005 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2006};
2007
2008static const unsigned int hscif1_data_b_pins[] = {
2009 /* RX, TX */
2010 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2011};
2012
2013static const unsigned int hscif1_data_b_mux[] = {
2014 HRX1_B_MARK, HTX1_B_MARK,
2015};
2016
2017static const unsigned int hscif1_clk_b_pins[] = {
2018 /* SCK */
2019 RCAR_GP_PIN(5, 0),
2020};
2021
2022static const unsigned int hscif1_clk_b_mux[] = {
2023 HSCK1_B_MARK,
2024};
2025
2026static const unsigned int hscif1_ctrl_b_pins[] = {
2027 /* RTS, CTS */
2028 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2029};
2030
2031static const unsigned int hscif1_ctrl_b_mux[] = {
2032 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2033};
2034
2035/* - HSCIF2 ----------------------------------------------------------------- */
2036static const unsigned int hscif2_data_a_pins[] = {
2037 /* RX, TX */
2038 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2039};
2040
2041static const unsigned int hscif2_data_a_mux[] = {
2042 HRX2_A_MARK, HTX2_A_MARK,
2043};
2044
2045static const unsigned int hscif2_clk_a_pins[] = {
2046 /* SCK */
2047 RCAR_GP_PIN(6, 10),
2048};
2049
2050static const unsigned int hscif2_clk_a_mux[] = {
2051 HSCK2_A_MARK,
2052};
2053
2054static const unsigned int hscif2_ctrl_a_pins[] = {
2055 /* RTS, CTS */
2056 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2057};
2058
2059static const unsigned int hscif2_ctrl_a_mux[] = {
2060 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2061};
2062
2063static const unsigned int hscif2_data_b_pins[] = {
2064 /* RX, TX */
2065 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2066};
2067
2068static const unsigned int hscif2_data_b_mux[] = {
2069 HRX2_B_MARK, HTX2_B_MARK,
2070};
2071
2072static const unsigned int hscif2_clk_b_pins[] = {
2073 /* SCK */
2074 RCAR_GP_PIN(6, 21),
2075};
2076
2077static const unsigned int hscif2_clk_b_mux[] = {
2078 HSCK2_B_MARK,
2079};
2080
2081static const unsigned int hscif2_ctrl_b_pins[] = {
2082 /* RTS, CTS */
2083 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2084};
2085
2086static const unsigned int hscif2_ctrl_b_mux[] = {
2087 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2088};
2089
2090static const unsigned int hscif2_data_c_pins[] = {
2091 /* RX, TX */
2092 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2093};
2094
2095static const unsigned int hscif2_data_c_mux[] = {
2096 HRX2_C_MARK, HTX2_C_MARK,
2097};
2098
2099static const unsigned int hscif2_clk_c_pins[] = {
2100 /* SCK */
2101 RCAR_GP_PIN(6, 24),
2102};
2103
2104static const unsigned int hscif2_clk_c_mux[] = {
2105 HSCK2_C_MARK,
2106};
2107
2108static const unsigned int hscif2_ctrl_c_pins[] = {
2109 /* RTS, CTS */
2110 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2111};
2112
2113static const unsigned int hscif2_ctrl_c_mux[] = {
2114 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2115};
2116
2117/* - HSCIF3 ----------------------------------------------------------------- */
2118static const unsigned int hscif3_data_a_pins[] = {
2119 /* RX, TX */
2120 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2121};
2122
2123static const unsigned int hscif3_data_a_mux[] = {
2124 HRX3_A_MARK, HTX3_A_MARK,
2125};
2126
2127static const unsigned int hscif3_clk_pins[] = {
2128 /* SCK */
2129 RCAR_GP_PIN(1, 22),
2130};
2131
2132static const unsigned int hscif3_clk_mux[] = {
2133 HSCK3_MARK,
2134};
2135
2136static const unsigned int hscif3_ctrl_pins[] = {
2137 /* RTS, CTS */
2138 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2139};
2140
2141static const unsigned int hscif3_ctrl_mux[] = {
2142 HRTS3_N_MARK, HCTS3_N_MARK,
2143};
2144
2145static const unsigned int hscif3_data_b_pins[] = {
2146 /* RX, TX */
2147 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2148};
2149
2150static const unsigned int hscif3_data_b_mux[] = {
2151 HRX3_B_MARK, HTX3_B_MARK,
2152};
2153
2154static const unsigned int hscif3_data_c_pins[] = {
2155 /* RX, TX */
2156 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2157};
2158
2159static const unsigned int hscif3_data_c_mux[] = {
2160 HRX3_C_MARK, HTX3_C_MARK,
2161};
2162
2163static const unsigned int hscif3_data_d_pins[] = {
2164 /* RX, TX */
2165 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2166};
2167
2168static const unsigned int hscif3_data_d_mux[] = {
2169 HRX3_D_MARK, HTX3_D_MARK,
2170};
2171
2172/* - HSCIF4 ----------------------------------------------------------------- */
2173static const unsigned int hscif4_data_a_pins[] = {
2174 /* RX, TX */
2175 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2176};
2177
2178static const unsigned int hscif4_data_a_mux[] = {
2179 HRX4_A_MARK, HTX4_A_MARK,
2180};
2181
2182static const unsigned int hscif4_clk_pins[] = {
2183 /* SCK */
2184 RCAR_GP_PIN(1, 11),
2185};
2186
2187static const unsigned int hscif4_clk_mux[] = {
2188 HSCK4_MARK,
2189};
2190
2191static const unsigned int hscif4_ctrl_pins[] = {
2192 /* RTS, CTS */
2193 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2194};
2195
2196static const unsigned int hscif4_ctrl_mux[] = {
2197 HRTS4_N_MARK, HCTS4_N_MARK,
2198};
2199
2200static const unsigned int hscif4_data_b_pins[] = {
2201 /* RX, TX */
2202 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2203};
2204
2205static const unsigned int hscif4_data_b_mux[] = {
2206 HRX4_B_MARK, HTX4_B_MARK,
2207};
2208
2209/* - I2C -------------------------------------------------------------------- */
2210static const unsigned int i2c1_a_pins[] = {
2211 /* SDA, SCL */
2212 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2213};
2214static const unsigned int i2c1_a_mux[] = {
2215 SDA1_A_MARK, SCL1_A_MARK,
2216};
2217static const unsigned int i2c1_b_pins[] = {
2218 /* SDA, SCL */
2219 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2220};
2221static const unsigned int i2c1_b_mux[] = {
2222 SDA1_B_MARK, SCL1_B_MARK,
2223};
2224static const unsigned int i2c2_a_pins[] = {
2225 /* SDA, SCL */
2226 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2227};
2228static const unsigned int i2c2_a_mux[] = {
2229 SDA2_A_MARK, SCL2_A_MARK,
2230};
2231static const unsigned int i2c2_b_pins[] = {
2232 /* SDA, SCL */
2233 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2234};
2235static const unsigned int i2c2_b_mux[] = {
2236 SDA2_B_MARK, SCL2_B_MARK,
2237};
2238static const unsigned int i2c6_a_pins[] = {
2239 /* SDA, SCL */
2240 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2241};
2242static const unsigned int i2c6_a_mux[] = {
2243 SDA6_A_MARK, SCL6_A_MARK,
2244};
2245static const unsigned int i2c6_b_pins[] = {
2246 /* SDA, SCL */
2247 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2248};
2249static const unsigned int i2c6_b_mux[] = {
2250 SDA6_B_MARK, SCL6_B_MARK,
2251};
2252static const unsigned int i2c6_c_pins[] = {
2253 /* SDA, SCL */
2254 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2255};
2256static const unsigned int i2c6_c_mux[] = {
2257 SDA6_C_MARK, SCL6_C_MARK,
2258};
2259
2260/* - INTC-EX ---------------------------------------------------------------- */
2261static const unsigned int intc_ex_irq0_pins[] = {
2262 /* IRQ0 */
2263 RCAR_GP_PIN(2, 0),
2264};
2265static const unsigned int intc_ex_irq0_mux[] = {
2266 IRQ0_MARK,
2267};
2268static const unsigned int intc_ex_irq1_pins[] = {
2269 /* IRQ1 */
2270 RCAR_GP_PIN(2, 1),
2271};
2272static const unsigned int intc_ex_irq1_mux[] = {
2273 IRQ1_MARK,
2274};
2275static const unsigned int intc_ex_irq2_pins[] = {
2276 /* IRQ2 */
2277 RCAR_GP_PIN(2, 2),
2278};
2279static const unsigned int intc_ex_irq2_mux[] = {
2280 IRQ2_MARK,
2281};
2282static const unsigned int intc_ex_irq3_pins[] = {
2283 /* IRQ3 */
2284 RCAR_GP_PIN(2, 3),
2285};
2286static const unsigned int intc_ex_irq3_mux[] = {
2287 IRQ3_MARK,
2288};
2289static const unsigned int intc_ex_irq4_pins[] = {
2290 /* IRQ4 */
2291 RCAR_GP_PIN(2, 4),
2292};
2293static const unsigned int intc_ex_irq4_mux[] = {
2294 IRQ4_MARK,
2295};
2296static const unsigned int intc_ex_irq5_pins[] = {
2297 /* IRQ5 */
2298 RCAR_GP_PIN(2, 5),
2299};
2300static const unsigned int intc_ex_irq5_mux[] = {
2301 IRQ5_MARK,
2302};
2303
2304/* - MSIOF0 ----------------------------------------------------------------- */
2305static const unsigned int msiof0_clk_pins[] = {
2306 /* SCK */
2307 RCAR_GP_PIN(5, 17),
2308};
2309static const unsigned int msiof0_clk_mux[] = {
2310 MSIOF0_SCK_MARK,
2311};
2312static const unsigned int msiof0_sync_pins[] = {
2313 /* SYNC */
2314 RCAR_GP_PIN(5, 18),
2315};
2316static const unsigned int msiof0_sync_mux[] = {
2317 MSIOF0_SYNC_MARK,
2318};
2319static const unsigned int msiof0_ss1_pins[] = {
2320 /* SS1 */
2321 RCAR_GP_PIN(5, 19),
2322};
2323static const unsigned int msiof0_ss1_mux[] = {
2324 MSIOF0_SS1_MARK,
2325};
2326static const unsigned int msiof0_ss2_pins[] = {
2327 /* SS2 */
2328 RCAR_GP_PIN(5, 21),
2329};
2330static const unsigned int msiof0_ss2_mux[] = {
2331 MSIOF0_SS2_MARK,
2332};
2333static const unsigned int msiof0_txd_pins[] = {
2334 /* TXD */
2335 RCAR_GP_PIN(5, 20),
2336};
2337static const unsigned int msiof0_txd_mux[] = {
2338 MSIOF0_TXD_MARK,
2339};
2340static const unsigned int msiof0_rxd_pins[] = {
2341 /* RXD */
2342 RCAR_GP_PIN(5, 22),
2343};
2344static const unsigned int msiof0_rxd_mux[] = {
2345 MSIOF0_RXD_MARK,
2346};
2347/* - MSIOF1 ----------------------------------------------------------------- */
2348static const unsigned int msiof1_clk_a_pins[] = {
2349 /* SCK */
2350 RCAR_GP_PIN(6, 8),
2351};
2352static const unsigned int msiof1_clk_a_mux[] = {
2353 MSIOF1_SCK_A_MARK,
2354};
2355static const unsigned int msiof1_sync_a_pins[] = {
2356 /* SYNC */
2357 RCAR_GP_PIN(6, 9),
2358};
2359static const unsigned int msiof1_sync_a_mux[] = {
2360 MSIOF1_SYNC_A_MARK,
2361};
2362static const unsigned int msiof1_ss1_a_pins[] = {
2363 /* SS1 */
2364 RCAR_GP_PIN(6, 5),
2365};
2366static const unsigned int msiof1_ss1_a_mux[] = {
2367 MSIOF1_SS1_A_MARK,
2368};
2369static const unsigned int msiof1_ss2_a_pins[] = {
2370 /* SS2 */
2371 RCAR_GP_PIN(6, 6),
2372};
2373static const unsigned int msiof1_ss2_a_mux[] = {
2374 MSIOF1_SS2_A_MARK,
2375};
2376static const unsigned int msiof1_txd_a_pins[] = {
2377 /* TXD */
2378 RCAR_GP_PIN(6, 7),
2379};
2380static const unsigned int msiof1_txd_a_mux[] = {
2381 MSIOF1_TXD_A_MARK,
2382};
2383static const unsigned int msiof1_rxd_a_pins[] = {
2384 /* RXD */
2385 RCAR_GP_PIN(6, 10),
2386};
2387static const unsigned int msiof1_rxd_a_mux[] = {
2388 MSIOF1_RXD_A_MARK,
2389};
2390static const unsigned int msiof1_clk_b_pins[] = {
2391 /* SCK */
2392 RCAR_GP_PIN(5, 9),
2393};
2394static const unsigned int msiof1_clk_b_mux[] = {
2395 MSIOF1_SCK_B_MARK,
2396};
2397static const unsigned int msiof1_sync_b_pins[] = {
2398 /* SYNC */
2399 RCAR_GP_PIN(5, 3),
2400};
2401static const unsigned int msiof1_sync_b_mux[] = {
2402 MSIOF1_SYNC_B_MARK,
2403};
2404static const unsigned int msiof1_ss1_b_pins[] = {
2405 /* SS1 */
2406 RCAR_GP_PIN(5, 4),
2407};
2408static const unsigned int msiof1_ss1_b_mux[] = {
2409 MSIOF1_SS1_B_MARK,
2410};
2411static const unsigned int msiof1_ss2_b_pins[] = {
2412 /* SS2 */
2413 RCAR_GP_PIN(5, 0),
2414};
2415static const unsigned int msiof1_ss2_b_mux[] = {
2416 MSIOF1_SS2_B_MARK,
2417};
2418static const unsigned int msiof1_txd_b_pins[] = {
2419 /* TXD */
2420 RCAR_GP_PIN(5, 8),
2421};
2422static const unsigned int msiof1_txd_b_mux[] = {
2423 MSIOF1_TXD_B_MARK,
2424};
2425static const unsigned int msiof1_rxd_b_pins[] = {
2426 /* RXD */
2427 RCAR_GP_PIN(5, 7),
2428};
2429static const unsigned int msiof1_rxd_b_mux[] = {
2430 MSIOF1_RXD_B_MARK,
2431};
2432static const unsigned int msiof1_clk_c_pins[] = {
2433 /* SCK */
2434 RCAR_GP_PIN(6, 17),
2435};
2436static const unsigned int msiof1_clk_c_mux[] = {
2437 MSIOF1_SCK_C_MARK,
2438};
2439static const unsigned int msiof1_sync_c_pins[] = {
2440 /* SYNC */
2441 RCAR_GP_PIN(6, 18),
2442};
2443static const unsigned int msiof1_sync_c_mux[] = {
2444 MSIOF1_SYNC_C_MARK,
2445};
2446static const unsigned int msiof1_ss1_c_pins[] = {
2447 /* SS1 */
2448 RCAR_GP_PIN(6, 21),
2449};
2450static const unsigned int msiof1_ss1_c_mux[] = {
2451 MSIOF1_SS1_C_MARK,
2452};
2453static const unsigned int msiof1_ss2_c_pins[] = {
2454 /* SS2 */
2455 RCAR_GP_PIN(6, 27),
2456};
2457static const unsigned int msiof1_ss2_c_mux[] = {
2458 MSIOF1_SS2_C_MARK,
2459};
2460static const unsigned int msiof1_txd_c_pins[] = {
2461 /* TXD */
2462 RCAR_GP_PIN(6, 20),
2463};
2464static const unsigned int msiof1_txd_c_mux[] = {
2465 MSIOF1_TXD_C_MARK,
2466};
2467static const unsigned int msiof1_rxd_c_pins[] = {
2468 /* RXD */
2469 RCAR_GP_PIN(6, 19),
2470};
2471static const unsigned int msiof1_rxd_c_mux[] = {
2472 MSIOF1_RXD_C_MARK,
2473};
2474static const unsigned int msiof1_clk_d_pins[] = {
2475 /* SCK */
2476 RCAR_GP_PIN(5, 12),
2477};
2478static const unsigned int msiof1_clk_d_mux[] = {
2479 MSIOF1_SCK_D_MARK,
2480};
2481static const unsigned int msiof1_sync_d_pins[] = {
2482 /* SYNC */
2483 RCAR_GP_PIN(5, 15),
2484};
2485static const unsigned int msiof1_sync_d_mux[] = {
2486 MSIOF1_SYNC_D_MARK,
2487};
2488static const unsigned int msiof1_ss1_d_pins[] = {
2489 /* SS1 */
2490 RCAR_GP_PIN(5, 16),
2491};
2492static const unsigned int msiof1_ss1_d_mux[] = {
2493 MSIOF1_SS1_D_MARK,
2494};
2495static const unsigned int msiof1_ss2_d_pins[] = {
2496 /* SS2 */
2497 RCAR_GP_PIN(5, 21),
2498};
2499static const unsigned int msiof1_ss2_d_mux[] = {
2500 MSIOF1_SS2_D_MARK,
2501};
2502static const unsigned int msiof1_txd_d_pins[] = {
2503 /* TXD */
2504 RCAR_GP_PIN(5, 14),
2505};
2506static const unsigned int msiof1_txd_d_mux[] = {
2507 MSIOF1_TXD_D_MARK,
2508};
2509static const unsigned int msiof1_rxd_d_pins[] = {
2510 /* RXD */
2511 RCAR_GP_PIN(5, 13),
2512};
2513static const unsigned int msiof1_rxd_d_mux[] = {
2514 MSIOF1_RXD_D_MARK,
2515};
2516static const unsigned int msiof1_clk_e_pins[] = {
2517 /* SCK */
2518 RCAR_GP_PIN(3, 0),
2519};
2520static const unsigned int msiof1_clk_e_mux[] = {
2521 MSIOF1_SCK_E_MARK,
2522};
2523static const unsigned int msiof1_sync_e_pins[] = {
2524 /* SYNC */
2525 RCAR_GP_PIN(3, 1),
2526};
2527static const unsigned int msiof1_sync_e_mux[] = {
2528 MSIOF1_SYNC_E_MARK,
2529};
2530static const unsigned int msiof1_ss1_e_pins[] = {
2531 /* SS1 */
2532 RCAR_GP_PIN(3, 4),
2533};
2534static const unsigned int msiof1_ss1_e_mux[] = {
2535 MSIOF1_SS1_E_MARK,
2536};
2537static const unsigned int msiof1_ss2_e_pins[] = {
2538 /* SS2 */
2539 RCAR_GP_PIN(3, 5),
2540};
2541static const unsigned int msiof1_ss2_e_mux[] = {
2542 MSIOF1_SS2_E_MARK,
2543};
2544static const unsigned int msiof1_txd_e_pins[] = {
2545 /* TXD */
2546 RCAR_GP_PIN(3, 3),
2547};
2548static const unsigned int msiof1_txd_e_mux[] = {
2549 MSIOF1_TXD_E_MARK,
2550};
2551static const unsigned int msiof1_rxd_e_pins[] = {
2552 /* RXD */
2553 RCAR_GP_PIN(3, 2),
2554};
2555static const unsigned int msiof1_rxd_e_mux[] = {
2556 MSIOF1_RXD_E_MARK,
2557};
2558static const unsigned int msiof1_clk_f_pins[] = {
2559 /* SCK */
2560 RCAR_GP_PIN(5, 23),
2561};
2562static const unsigned int msiof1_clk_f_mux[] = {
2563 MSIOF1_SCK_F_MARK,
2564};
2565static const unsigned int msiof1_sync_f_pins[] = {
2566 /* SYNC */
2567 RCAR_GP_PIN(5, 24),
2568};
2569static const unsigned int msiof1_sync_f_mux[] = {
2570 MSIOF1_SYNC_F_MARK,
2571};
2572static const unsigned int msiof1_ss1_f_pins[] = {
2573 /* SS1 */
2574 RCAR_GP_PIN(6, 1),
2575};
2576static const unsigned int msiof1_ss1_f_mux[] = {
2577 MSIOF1_SS1_F_MARK,
2578};
2579static const unsigned int msiof1_ss2_f_pins[] = {
2580 /* SS2 */
2581 RCAR_GP_PIN(6, 2),
2582};
2583static const unsigned int msiof1_ss2_f_mux[] = {
2584 MSIOF1_SS2_F_MARK,
2585};
2586static const unsigned int msiof1_txd_f_pins[] = {
2587 /* TXD */
2588 RCAR_GP_PIN(6, 0),
2589};
2590static const unsigned int msiof1_txd_f_mux[] = {
2591 MSIOF1_TXD_F_MARK,
2592};
2593static const unsigned int msiof1_rxd_f_pins[] = {
2594 /* RXD */
2595 RCAR_GP_PIN(5, 25),
2596};
2597static const unsigned int msiof1_rxd_f_mux[] = {
2598 MSIOF1_RXD_F_MARK,
2599};
2600static const unsigned int msiof1_clk_g_pins[] = {
2601 /* SCK */
2602 RCAR_GP_PIN(3, 6),
2603};
2604static const unsigned int msiof1_clk_g_mux[] = {
2605 MSIOF1_SCK_G_MARK,
2606};
2607static const unsigned int msiof1_sync_g_pins[] = {
2608 /* SYNC */
2609 RCAR_GP_PIN(3, 7),
2610};
2611static const unsigned int msiof1_sync_g_mux[] = {
2612 MSIOF1_SYNC_G_MARK,
2613};
2614static const unsigned int msiof1_ss1_g_pins[] = {
2615 /* SS1 */
2616 RCAR_GP_PIN(3, 10),
2617};
2618static const unsigned int msiof1_ss1_g_mux[] = {
2619 MSIOF1_SS1_G_MARK,
2620};
2621static const unsigned int msiof1_ss2_g_pins[] = {
2622 /* SS2 */
2623 RCAR_GP_PIN(3, 11),
2624};
2625static const unsigned int msiof1_ss2_g_mux[] = {
2626 MSIOF1_SS2_G_MARK,
2627};
2628static const unsigned int msiof1_txd_g_pins[] = {
2629 /* TXD */
2630 RCAR_GP_PIN(3, 9),
2631};
2632static const unsigned int msiof1_txd_g_mux[] = {
2633 MSIOF1_TXD_G_MARK,
2634};
2635static const unsigned int msiof1_rxd_g_pins[] = {
2636 /* RXD */
2637 RCAR_GP_PIN(3, 8),
2638};
2639static const unsigned int msiof1_rxd_g_mux[] = {
2640 MSIOF1_RXD_G_MARK,
2641};
2642/* - MSIOF2 ----------------------------------------------------------------- */
2643static const unsigned int msiof2_clk_a_pins[] = {
2644 /* SCK */
2645 RCAR_GP_PIN(1, 9),
2646};
2647static const unsigned int msiof2_clk_a_mux[] = {
2648 MSIOF2_SCK_A_MARK,
2649};
2650static const unsigned int msiof2_sync_a_pins[] = {
2651 /* SYNC */
2652 RCAR_GP_PIN(1, 8),
2653};
2654static const unsigned int msiof2_sync_a_mux[] = {
2655 MSIOF2_SYNC_A_MARK,
2656};
2657static const unsigned int msiof2_ss1_a_pins[] = {
2658 /* SS1 */
2659 RCAR_GP_PIN(1, 6),
2660};
2661static const unsigned int msiof2_ss1_a_mux[] = {
2662 MSIOF2_SS1_A_MARK,
2663};
2664static const unsigned int msiof2_ss2_a_pins[] = {
2665 /* SS2 */
2666 RCAR_GP_PIN(1, 7),
2667};
2668static const unsigned int msiof2_ss2_a_mux[] = {
2669 MSIOF2_SS2_A_MARK,
2670};
2671static const unsigned int msiof2_txd_a_pins[] = {
2672 /* TXD */
2673 RCAR_GP_PIN(1, 11),
2674};
2675static const unsigned int msiof2_txd_a_mux[] = {
2676 MSIOF2_TXD_A_MARK,
2677};
2678static const unsigned int msiof2_rxd_a_pins[] = {
2679 /* RXD */
2680 RCAR_GP_PIN(1, 10),
2681};
2682static const unsigned int msiof2_rxd_a_mux[] = {
2683 MSIOF2_RXD_A_MARK,
2684};
2685static const unsigned int msiof2_clk_b_pins[] = {
2686 /* SCK */
2687 RCAR_GP_PIN(0, 4),
2688};
2689static const unsigned int msiof2_clk_b_mux[] = {
2690 MSIOF2_SCK_B_MARK,
2691};
2692static const unsigned int msiof2_sync_b_pins[] = {
2693 /* SYNC */
2694 RCAR_GP_PIN(0, 5),
2695};
2696static const unsigned int msiof2_sync_b_mux[] = {
2697 MSIOF2_SYNC_B_MARK,
2698};
2699static const unsigned int msiof2_ss1_b_pins[] = {
2700 /* SS1 */
2701 RCAR_GP_PIN(0, 0),
2702};
2703static const unsigned int msiof2_ss1_b_mux[] = {
2704 MSIOF2_SS1_B_MARK,
2705};
2706static const unsigned int msiof2_ss2_b_pins[] = {
2707 /* SS2 */
2708 RCAR_GP_PIN(0, 1),
2709};
2710static const unsigned int msiof2_ss2_b_mux[] = {
2711 MSIOF2_SS2_B_MARK,
2712};
2713static const unsigned int msiof2_txd_b_pins[] = {
2714 /* TXD */
2715 RCAR_GP_PIN(0, 7),
2716};
2717static const unsigned int msiof2_txd_b_mux[] = {
2718 MSIOF2_TXD_B_MARK,
2719};
2720static const unsigned int msiof2_rxd_b_pins[] = {
2721 /* RXD */
2722 RCAR_GP_PIN(0, 6),
2723};
2724static const unsigned int msiof2_rxd_b_mux[] = {
2725 MSIOF2_RXD_B_MARK,
2726};
2727static const unsigned int msiof2_clk_c_pins[] = {
2728 /* SCK */
2729 RCAR_GP_PIN(2, 12),
2730};
2731static const unsigned int msiof2_clk_c_mux[] = {
2732 MSIOF2_SCK_C_MARK,
2733};
2734static const unsigned int msiof2_sync_c_pins[] = {
2735 /* SYNC */
2736 RCAR_GP_PIN(2, 11),
2737};
2738static const unsigned int msiof2_sync_c_mux[] = {
2739 MSIOF2_SYNC_C_MARK,
2740};
2741static const unsigned int msiof2_ss1_c_pins[] = {
2742 /* SS1 */
2743 RCAR_GP_PIN(2, 10),
2744};
2745static const unsigned int msiof2_ss1_c_mux[] = {
2746 MSIOF2_SS1_C_MARK,
2747};
2748static const unsigned int msiof2_ss2_c_pins[] = {
2749 /* SS2 */
2750 RCAR_GP_PIN(2, 9),
2751};
2752static const unsigned int msiof2_ss2_c_mux[] = {
2753 MSIOF2_SS2_C_MARK,
2754};
2755static const unsigned int msiof2_txd_c_pins[] = {
2756 /* TXD */
2757 RCAR_GP_PIN(2, 14),
2758};
2759static const unsigned int msiof2_txd_c_mux[] = {
2760 MSIOF2_TXD_C_MARK,
2761};
2762static const unsigned int msiof2_rxd_c_pins[] = {
2763 /* RXD */
2764 RCAR_GP_PIN(2, 13),
2765};
2766static const unsigned int msiof2_rxd_c_mux[] = {
2767 MSIOF2_RXD_C_MARK,
2768};
2769static const unsigned int msiof2_clk_d_pins[] = {
2770 /* SCK */
2771 RCAR_GP_PIN(0, 8),
2772};
2773static const unsigned int msiof2_clk_d_mux[] = {
2774 MSIOF2_SCK_D_MARK,
2775};
2776static const unsigned int msiof2_sync_d_pins[] = {
2777 /* SYNC */
2778 RCAR_GP_PIN(0, 9),
2779};
2780static const unsigned int msiof2_sync_d_mux[] = {
2781 MSIOF2_SYNC_D_MARK,
2782};
2783static const unsigned int msiof2_ss1_d_pins[] = {
2784 /* SS1 */
2785 RCAR_GP_PIN(0, 12),
2786};
2787static const unsigned int msiof2_ss1_d_mux[] = {
2788 MSIOF2_SS1_D_MARK,
2789};
2790static const unsigned int msiof2_ss2_d_pins[] = {
2791 /* SS2 */
2792 RCAR_GP_PIN(0, 13),
2793};
2794static const unsigned int msiof2_ss2_d_mux[] = {
2795 MSIOF2_SS2_D_MARK,
2796};
2797static const unsigned int msiof2_txd_d_pins[] = {
2798 /* TXD */
2799 RCAR_GP_PIN(0, 11),
2800};
2801static const unsigned int msiof2_txd_d_mux[] = {
2802 MSIOF2_TXD_D_MARK,
2803};
2804static const unsigned int msiof2_rxd_d_pins[] = {
2805 /* RXD */
2806 RCAR_GP_PIN(0, 10),
2807};
2808static const unsigned int msiof2_rxd_d_mux[] = {
2809 MSIOF2_RXD_D_MARK,
2810};
2811/* - MSIOF3 ----------------------------------------------------------------- */
2812static const unsigned int msiof3_clk_a_pins[] = {
2813 /* SCK */
2814 RCAR_GP_PIN(0, 0),
2815};
2816static const unsigned int msiof3_clk_a_mux[] = {
2817 MSIOF3_SCK_A_MARK,
2818};
2819static const unsigned int msiof3_sync_a_pins[] = {
2820 /* SYNC */
2821 RCAR_GP_PIN(0, 1),
2822};
2823static const unsigned int msiof3_sync_a_mux[] = {
2824 MSIOF3_SYNC_A_MARK,
2825};
2826static const unsigned int msiof3_ss1_a_pins[] = {
2827 /* SS1 */
2828 RCAR_GP_PIN(0, 14),
2829};
2830static const unsigned int msiof3_ss1_a_mux[] = {
2831 MSIOF3_SS1_A_MARK,
2832};
2833static const unsigned int msiof3_ss2_a_pins[] = {
2834 /* SS2 */
2835 RCAR_GP_PIN(0, 15),
2836};
2837static const unsigned int msiof3_ss2_a_mux[] = {
2838 MSIOF3_SS2_A_MARK,
2839};
2840static const unsigned int msiof3_txd_a_pins[] = {
2841 /* TXD */
2842 RCAR_GP_PIN(0, 3),
2843};
2844static const unsigned int msiof3_txd_a_mux[] = {
2845 MSIOF3_TXD_A_MARK,
2846};
2847static const unsigned int msiof3_rxd_a_pins[] = {
2848 /* RXD */
2849 RCAR_GP_PIN(0, 2),
2850};
2851static const unsigned int msiof3_rxd_a_mux[] = {
2852 MSIOF3_RXD_A_MARK,
2853};
2854static const unsigned int msiof3_clk_b_pins[] = {
2855 /* SCK */
2856 RCAR_GP_PIN(1, 2),
2857};
2858static const unsigned int msiof3_clk_b_mux[] = {
2859 MSIOF3_SCK_B_MARK,
2860};
2861static const unsigned int msiof3_sync_b_pins[] = {
2862 /* SYNC */
2863 RCAR_GP_PIN(1, 0),
2864};
2865static const unsigned int msiof3_sync_b_mux[] = {
2866 MSIOF3_SYNC_B_MARK,
2867};
2868static const unsigned int msiof3_ss1_b_pins[] = {
2869 /* SS1 */
2870 RCAR_GP_PIN(1, 4),
2871};
2872static const unsigned int msiof3_ss1_b_mux[] = {
2873 MSIOF3_SS1_B_MARK,
2874};
2875static const unsigned int msiof3_ss2_b_pins[] = {
2876 /* SS2 */
2877 RCAR_GP_PIN(1, 5),
2878};
2879static const unsigned int msiof3_ss2_b_mux[] = {
2880 MSIOF3_SS2_B_MARK,
2881};
2882static const unsigned int msiof3_txd_b_pins[] = {
2883 /* TXD */
2884 RCAR_GP_PIN(1, 1),
2885};
2886static const unsigned int msiof3_txd_b_mux[] = {
2887 MSIOF3_TXD_B_MARK,
2888};
2889static const unsigned int msiof3_rxd_b_pins[] = {
2890 /* RXD */
2891 RCAR_GP_PIN(1, 3),
2892};
2893static const unsigned int msiof3_rxd_b_mux[] = {
2894 MSIOF3_RXD_B_MARK,
2895};
2896static const unsigned int msiof3_clk_c_pins[] = {
2897 /* SCK */
2898 RCAR_GP_PIN(1, 12),
2899};
2900static const unsigned int msiof3_clk_c_mux[] = {
2901 MSIOF3_SCK_C_MARK,
2902};
2903static const unsigned int msiof3_sync_c_pins[] = {
2904 /* SYNC */
2905 RCAR_GP_PIN(1, 13),
2906};
2907static const unsigned int msiof3_sync_c_mux[] = {
2908 MSIOF3_SYNC_C_MARK,
2909};
2910static const unsigned int msiof3_txd_c_pins[] = {
2911 /* TXD */
2912 RCAR_GP_PIN(1, 15),
2913};
2914static const unsigned int msiof3_txd_c_mux[] = {
2915 MSIOF3_TXD_C_MARK,
2916};
2917static const unsigned int msiof3_rxd_c_pins[] = {
2918 /* RXD */
2919 RCAR_GP_PIN(1, 14),
2920};
2921static const unsigned int msiof3_rxd_c_mux[] = {
2922 MSIOF3_RXD_C_MARK,
2923};
2924static const unsigned int msiof3_clk_d_pins[] = {
2925 /* SCK */
2926 RCAR_GP_PIN(1, 22),
2927};
2928static const unsigned int msiof3_clk_d_mux[] = {
2929 MSIOF3_SCK_D_MARK,
2930};
2931static const unsigned int msiof3_sync_d_pins[] = {
2932 /* SYNC */
2933 RCAR_GP_PIN(1, 23),
2934};
2935static const unsigned int msiof3_sync_d_mux[] = {
2936 MSIOF3_SYNC_D_MARK,
2937};
2938static const unsigned int msiof3_ss1_d_pins[] = {
2939 /* SS1 */
2940 RCAR_GP_PIN(1, 26),
2941};
2942static const unsigned int msiof3_ss1_d_mux[] = {
2943 MSIOF3_SS1_D_MARK,
2944};
2945static const unsigned int msiof3_txd_d_pins[] = {
2946 /* TXD */
2947 RCAR_GP_PIN(1, 25),
2948};
2949static const unsigned int msiof3_txd_d_mux[] = {
2950 MSIOF3_TXD_D_MARK,
2951};
2952static const unsigned int msiof3_rxd_d_pins[] = {
2953 /* RXD */
2954 RCAR_GP_PIN(1, 24),
2955};
2956static const unsigned int msiof3_rxd_d_mux[] = {
2957 MSIOF3_RXD_D_MARK,
2958};
2959static const unsigned int msiof3_clk_e_pins[] = {
2960 /* SCK */
2961 RCAR_GP_PIN(2, 3),
2962};
2963static const unsigned int msiof3_clk_e_mux[] = {
2964 MSIOF3_SCK_E_MARK,
2965};
2966static const unsigned int msiof3_sync_e_pins[] = {
2967 /* SYNC */
2968 RCAR_GP_PIN(2, 2),
2969};
2970static const unsigned int msiof3_sync_e_mux[] = {
2971 MSIOF3_SYNC_E_MARK,
2972};
2973static const unsigned int msiof3_ss1_e_pins[] = {
2974 /* SS1 */
2975 RCAR_GP_PIN(2, 1),
2976};
2977static const unsigned int msiof3_ss1_e_mux[] = {
2978 MSIOF3_SS1_E_MARK,
2979};
2980static const unsigned int msiof3_ss2_e_pins[] = {
2981 /* SS2 */
2982 RCAR_GP_PIN(2, 0),
2983};
2984static const unsigned int msiof3_ss2_e_mux[] = {
2985 MSIOF3_SS2_E_MARK,
2986};
2987static const unsigned int msiof3_txd_e_pins[] = {
2988 /* TXD */
2989 RCAR_GP_PIN(2, 5),
2990};
2991static const unsigned int msiof3_txd_e_mux[] = {
2992 MSIOF3_TXD_E_MARK,
2993};
2994static const unsigned int msiof3_rxd_e_pins[] = {
2995 /* RXD */
2996 RCAR_GP_PIN(2, 4),
2997};
2998static const unsigned int msiof3_rxd_e_mux[] = {
2999 MSIOF3_RXD_E_MARK,
3000};
3001
3002/* - PWM0 --------------------------------------------------------------------*/
3003static const unsigned int pwm0_pins[] = {
3004 /* PWM */
3005 RCAR_GP_PIN(2, 6),
3006};
3007static const unsigned int pwm0_mux[] = {
3008 PWM0_MARK,
3009};
3010/* - PWM1 --------------------------------------------------------------------*/
3011static const unsigned int pwm1_a_pins[] = {
3012 /* PWM */
3013 RCAR_GP_PIN(2, 7),
3014};
3015static const unsigned int pwm1_a_mux[] = {
3016 PWM1_A_MARK,
3017};
3018static const unsigned int pwm1_b_pins[] = {
3019 /* PWM */
3020 RCAR_GP_PIN(1, 8),
3021};
3022static const unsigned int pwm1_b_mux[] = {
3023 PWM1_B_MARK,
3024};
3025/* - PWM2 --------------------------------------------------------------------*/
3026static const unsigned int pwm2_a_pins[] = {
3027 /* PWM */
3028 RCAR_GP_PIN(2, 8),
3029};
3030static const unsigned int pwm2_a_mux[] = {
3031 PWM2_A_MARK,
3032};
3033static const unsigned int pwm2_b_pins[] = {
3034 /* PWM */
3035 RCAR_GP_PIN(1, 11),
3036};
3037static const unsigned int pwm2_b_mux[] = {
3038 PWM2_B_MARK,
3039};
3040/* - PWM3 --------------------------------------------------------------------*/
3041static const unsigned int pwm3_a_pins[] = {
3042 /* PWM */
3043 RCAR_GP_PIN(1, 0),
3044};
3045static const unsigned int pwm3_a_mux[] = {
3046 PWM3_A_MARK,
3047};
3048static const unsigned int pwm3_b_pins[] = {
3049 /* PWM */
3050 RCAR_GP_PIN(2, 2),
3051};
3052static const unsigned int pwm3_b_mux[] = {
3053 PWM3_B_MARK,
3054};
3055/* - PWM4 --------------------------------------------------------------------*/
3056static const unsigned int pwm4_a_pins[] = {
3057 /* PWM */
3058 RCAR_GP_PIN(1, 1),
3059};
3060static const unsigned int pwm4_a_mux[] = {
3061 PWM4_A_MARK,
3062};
3063static const unsigned int pwm4_b_pins[] = {
3064 /* PWM */
3065 RCAR_GP_PIN(2, 3),
3066};
3067static const unsigned int pwm4_b_mux[] = {
3068 PWM4_B_MARK,
3069};
3070/* - PWM5 --------------------------------------------------------------------*/
3071static const unsigned int pwm5_a_pins[] = {
3072 /* PWM */
3073 RCAR_GP_PIN(1, 2),
3074};
3075static const unsigned int pwm5_a_mux[] = {
3076 PWM5_A_MARK,
3077};
3078static const unsigned int pwm5_b_pins[] = {
3079 /* PWM */
3080 RCAR_GP_PIN(2, 4),
3081};
3082static const unsigned int pwm5_b_mux[] = {
3083 PWM5_B_MARK,
3084};
3085/* - PWM6 --------------------------------------------------------------------*/
3086static const unsigned int pwm6_a_pins[] = {
3087 /* PWM */
3088 RCAR_GP_PIN(1, 3),
3089};
3090static const unsigned int pwm6_a_mux[] = {
3091 PWM6_A_MARK,
3092};
3093static const unsigned int pwm6_b_pins[] = {
3094 /* PWM */
3095 RCAR_GP_PIN(2, 5),
3096};
3097static const unsigned int pwm6_b_mux[] = {
3098 PWM6_B_MARK,
3099};
3100
3101/* - SATA --------------------------------------------------------------------*/
3102static const unsigned int sata0_devslp_a_pins[] = {
3103 /* DEVSLP */
3104 RCAR_GP_PIN(6, 16),
3105};
3106
3107static const unsigned int sata0_devslp_a_mux[] = {
3108 SATA_DEVSLP_A_MARK,
3109};
3110
3111static const unsigned int sata0_devslp_b_pins[] = {
3112 /* DEVSLP */
3113 RCAR_GP_PIN(4, 6),
3114};
3115
3116static const unsigned int sata0_devslp_b_mux[] = {
3117 SATA_DEVSLP_B_MARK,
3118};
3119
3120/* - SCIF0 ------------------------------------------------------------------ */
3121static const unsigned int scif0_data_pins[] = {
3122 /* RX, TX */
3123 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3124};
3125static const unsigned int scif0_data_mux[] = {
3126 RX0_MARK, TX0_MARK,
3127};
3128static const unsigned int scif0_clk_pins[] = {
3129 /* SCK */
3130 RCAR_GP_PIN(5, 0),
3131};
3132static const unsigned int scif0_clk_mux[] = {
3133 SCK0_MARK,
3134};
3135static const unsigned int scif0_ctrl_pins[] = {
3136 /* RTS, CTS */
3137 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3138};
3139static const unsigned int scif0_ctrl_mux[] = {
3140 RTS0_N_MARK, CTS0_N_MARK,
3141};
3142/* - SCIF1 ------------------------------------------------------------------ */
3143static const unsigned int scif1_data_a_pins[] = {
3144 /* RX, TX */
3145 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3146};
3147static const unsigned int scif1_data_a_mux[] = {
3148 RX1_A_MARK, TX1_A_MARK,
3149};
3150static const unsigned int scif1_clk_pins[] = {
3151 /* SCK */
3152 RCAR_GP_PIN(6, 21),
3153};
3154static const unsigned int scif1_clk_mux[] = {
3155 SCK1_MARK,
3156};
3157static const unsigned int scif1_ctrl_pins[] = {
3158 /* RTS, CTS */
3159 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3160};
3161static const unsigned int scif1_ctrl_mux[] = {
3162 RTS1_N_MARK, CTS1_N_MARK,
3163};
3164static const unsigned int scif1_data_b_pins[] = {
3165 /* RX, TX */
3166 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3167};
3168static const unsigned int scif1_data_b_mux[] = {
3169 RX1_B_MARK, TX1_B_MARK,
3170};
3171/* - SCIF2 ------------------------------------------------------------------ */
3172static const unsigned int scif2_data_a_pins[] = {
3173 /* RX, TX */
3174 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3175};
3176static const unsigned int scif2_data_a_mux[] = {
3177 RX2_A_MARK, TX2_A_MARK,
3178};
3179static const unsigned int scif2_clk_pins[] = {
3180 /* SCK */
3181 RCAR_GP_PIN(5, 9),
3182};
3183static const unsigned int scif2_clk_mux[] = {
3184 SCK2_MARK,
3185};
3186static const unsigned int scif2_data_b_pins[] = {
3187 /* RX, TX */
3188 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3189};
3190static const unsigned int scif2_data_b_mux[] = {
3191 RX2_B_MARK, TX2_B_MARK,
3192};
3193/* - SCIF3 ------------------------------------------------------------------ */
3194static const unsigned int scif3_data_a_pins[] = {
3195 /* RX, TX */
3196 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3197};
3198static const unsigned int scif3_data_a_mux[] = {
3199 RX3_A_MARK, TX3_A_MARK,
3200};
3201static const unsigned int scif3_clk_pins[] = {
3202 /* SCK */
3203 RCAR_GP_PIN(1, 22),
3204};
3205static const unsigned int scif3_clk_mux[] = {
3206 SCK3_MARK,
3207};
3208static const unsigned int scif3_ctrl_pins[] = {
3209 /* RTS, CTS */
3210 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3211};
3212static const unsigned int scif3_ctrl_mux[] = {
3213 RTS3_N_MARK, CTS3_N_MARK,
3214};
3215static const unsigned int scif3_data_b_pins[] = {
3216 /* RX, TX */
3217 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3218};
3219static const unsigned int scif3_data_b_mux[] = {
3220 RX3_B_MARK, TX3_B_MARK,
3221};
3222/* - SCIF4 ------------------------------------------------------------------ */
3223static const unsigned int scif4_data_a_pins[] = {
3224 /* RX, TX */
3225 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3226};
3227static const unsigned int scif4_data_a_mux[] = {
3228 RX4_A_MARK, TX4_A_MARK,
3229};
3230static const unsigned int scif4_clk_a_pins[] = {
3231 /* SCK */
3232 RCAR_GP_PIN(2, 10),
3233};
3234static const unsigned int scif4_clk_a_mux[] = {
3235 SCK4_A_MARK,
3236};
3237static const unsigned int scif4_ctrl_a_pins[] = {
3238 /* RTS, CTS */
3239 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3240};
3241static const unsigned int scif4_ctrl_a_mux[] = {
3242 RTS4_N_A_MARK, CTS4_N_A_MARK,
3243};
3244static const unsigned int scif4_data_b_pins[] = {
3245 /* RX, TX */
3246 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3247};
3248static const unsigned int scif4_data_b_mux[] = {
3249 RX4_B_MARK, TX4_B_MARK,
3250};
3251static const unsigned int scif4_clk_b_pins[] = {
3252 /* SCK */
3253 RCAR_GP_PIN(1, 5),
3254};
3255static const unsigned int scif4_clk_b_mux[] = {
3256 SCK4_B_MARK,
3257};
3258static const unsigned int scif4_ctrl_b_pins[] = {
3259 /* RTS, CTS */
3260 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3261};
3262static const unsigned int scif4_ctrl_b_mux[] = {
3263 RTS4_N_B_MARK, CTS4_N_B_MARK,
3264};
3265static const unsigned int scif4_data_c_pins[] = {
3266 /* RX, TX */
3267 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3268};
3269static const unsigned int scif4_data_c_mux[] = {
3270 RX4_C_MARK, TX4_C_MARK,
3271};
3272static const unsigned int scif4_clk_c_pins[] = {
3273 /* SCK */
3274 RCAR_GP_PIN(0, 8),
3275};
3276static const unsigned int scif4_clk_c_mux[] = {
3277 SCK4_C_MARK,
3278};
3279static const unsigned int scif4_ctrl_c_pins[] = {
3280 /* RTS, CTS */
3281 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3282};
3283static const unsigned int scif4_ctrl_c_mux[] = {
3284 RTS4_N_C_MARK, CTS4_N_C_MARK,
3285};
3286/* - SCIF5 ------------------------------------------------------------------ */
3287static const unsigned int scif5_data_a_pins[] = {
3288 /* RX, TX */
3289 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3290};
3291static const unsigned int scif5_data_a_mux[] = {
3292 RX5_A_MARK, TX5_A_MARK,
3293};
3294static const unsigned int scif5_clk_a_pins[] = {
3295 /* SCK */
3296 RCAR_GP_PIN(6, 21),
3297};
3298static const unsigned int scif5_clk_a_mux[] = {
3299 SCK5_A_MARK,
3300};
3301static const unsigned int scif5_data_b_pins[] = {
3302 /* RX, TX */
3303 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3304};
3305static const unsigned int scif5_data_b_mux[] = {
3306 RX5_B_MARK, TX5_B_MARK,
3307};
3308static const unsigned int scif5_clk_b_pins[] = {
3309 /* SCK */
3310 RCAR_GP_PIN(5, 0),
3311};
3312static const unsigned int scif5_clk_b_mux[] = {
3313 SCK5_B_MARK,
3314};
3315/* - SCIF Clock ------------------------------------------------------------- */
3316static const unsigned int scif_clk_a_pins[] = {
3317 /* SCIF_CLK */
3318 RCAR_GP_PIN(6, 23),
3319};
3320static const unsigned int scif_clk_a_mux[] = {
3321 SCIF_CLK_A_MARK,
3322};
3323static const unsigned int scif_clk_b_pins[] = {
3324 /* SCIF_CLK */
3325 RCAR_GP_PIN(5, 9),
3326};
3327static const unsigned int scif_clk_b_mux[] = {
3328 SCIF_CLK_B_MARK,
3329};
3330
3331/* - SDHI0 ------------------------------------------------------------------ */
3332static const unsigned int sdhi0_data1_pins[] = {
3333 /* D0 */
3334 RCAR_GP_PIN(3, 2),
3335};
3336
3337static const unsigned int sdhi0_data1_mux[] = {
3338 SD0_DAT0_MARK,
3339};
3340
3341static const unsigned int sdhi0_data4_pins[] = {
3342 /* D[0:3] */
3343 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3344 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3345};
3346
3347static const unsigned int sdhi0_data4_mux[] = {
3348 SD0_DAT0_MARK, SD0_DAT1_MARK,
3349 SD0_DAT2_MARK, SD0_DAT3_MARK,
3350};
3351
3352static const unsigned int sdhi0_ctrl_pins[] = {
3353 /* CLK, CMD */
3354 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3355};
3356
3357static const unsigned int sdhi0_ctrl_mux[] = {
3358 SD0_CLK_MARK, SD0_CMD_MARK,
3359};
3360
3361static const unsigned int sdhi0_cd_pins[] = {
3362 /* CD */
3363 RCAR_GP_PIN(3, 12),
3364};
3365
3366static const unsigned int sdhi0_cd_mux[] = {
3367 SD0_CD_MARK,
3368};
3369
3370static const unsigned int sdhi0_wp_pins[] = {
3371 /* WP */
3372 RCAR_GP_PIN(3, 13),
3373};
3374
3375static const unsigned int sdhi0_wp_mux[] = {
3376 SD0_WP_MARK,
3377};
3378
3379/* - SDHI1 ------------------------------------------------------------------ */
3380static const unsigned int sdhi1_data1_pins[] = {
3381 /* D0 */
3382 RCAR_GP_PIN(3, 8),
3383};
3384
3385static const unsigned int sdhi1_data1_mux[] = {
3386 SD1_DAT0_MARK,
3387};
3388
3389static const unsigned int sdhi1_data4_pins[] = {
3390 /* D[0:3] */
3391 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3392 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3393};
3394
3395static const unsigned int sdhi1_data4_mux[] = {
3396 SD1_DAT0_MARK, SD1_DAT1_MARK,
3397 SD1_DAT2_MARK, SD1_DAT3_MARK,
3398};
3399
3400static const unsigned int sdhi1_ctrl_pins[] = {
3401 /* CLK, CMD */
3402 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3403};
3404
3405static const unsigned int sdhi1_ctrl_mux[] = {
3406 SD1_CLK_MARK, SD1_CMD_MARK,
3407};
3408
3409static const unsigned int sdhi1_cd_pins[] = {
3410 /* CD */
3411 RCAR_GP_PIN(3, 14),
3412};
3413
3414static const unsigned int sdhi1_cd_mux[] = {
3415 SD1_CD_MARK,
3416};
3417
3418static const unsigned int sdhi1_wp_pins[] = {
3419 /* WP */
3420 RCAR_GP_PIN(3, 15),
3421};
3422
3423static const unsigned int sdhi1_wp_mux[] = {
3424 SD1_WP_MARK,
3425};
3426
3427/* - SDHI2 ------------------------------------------------------------------ */
3428static const unsigned int sdhi2_data1_pins[] = {
3429 /* D0 */
3430 RCAR_GP_PIN(4, 2),
3431};
3432
3433static const unsigned int sdhi2_data1_mux[] = {
3434 SD2_DAT0_MARK,
3435};
3436
3437static const unsigned int sdhi2_data4_pins[] = {
3438 /* D[0:3] */
3439 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3440 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3441};
3442
3443static const unsigned int sdhi2_data4_mux[] = {
3444 SD2_DAT0_MARK, SD2_DAT1_MARK,
3445 SD2_DAT2_MARK, SD2_DAT3_MARK,
3446};
3447
3448static const unsigned int sdhi2_data8_pins[] = {
3449 /* D[0:7] */
3450 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3451 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3452 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3453 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3454};
3455
3456static const unsigned int sdhi2_data8_mux[] = {
3457 SD2_DAT0_MARK, SD2_DAT1_MARK,
3458 SD2_DAT2_MARK, SD2_DAT3_MARK,
3459 SD2_DAT4_MARK, SD2_DAT5_MARK,
3460 SD2_DAT6_MARK, SD2_DAT7_MARK,
3461};
3462
3463static const unsigned int sdhi2_ctrl_pins[] = {
3464 /* CLK, CMD */
3465 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3466};
3467
3468static const unsigned int sdhi2_ctrl_mux[] = {
3469 SD2_CLK_MARK, SD2_CMD_MARK,
3470};
3471
3472static const unsigned int sdhi2_cd_a_pins[] = {
3473 /* CD */
3474 RCAR_GP_PIN(4, 13),
3475};
3476
3477static const unsigned int sdhi2_cd_a_mux[] = {
3478 SD2_CD_A_MARK,
3479};
3480
3481static const unsigned int sdhi2_cd_b_pins[] = {
3482 /* CD */
3483 RCAR_GP_PIN(5, 10),
3484};
3485
3486static const unsigned int sdhi2_cd_b_mux[] = {
3487 SD2_CD_B_MARK,
3488};
3489
3490static const unsigned int sdhi2_wp_a_pins[] = {
3491 /* WP */
3492 RCAR_GP_PIN(4, 14),
3493};
3494
3495static const unsigned int sdhi2_wp_a_mux[] = {
3496 SD2_WP_A_MARK,
3497};
3498
3499static const unsigned int sdhi2_wp_b_pins[] = {
3500 /* WP */
3501 RCAR_GP_PIN(5, 11),
3502};
3503
3504static const unsigned int sdhi2_wp_b_mux[] = {
3505 SD2_WP_B_MARK,
3506};
3507
3508static const unsigned int sdhi2_ds_pins[] = {
3509 /* DS */
3510 RCAR_GP_PIN(4, 6),
3511};
3512
3513static const unsigned int sdhi2_ds_mux[] = {
3514 SD2_DS_MARK,
3515};
3516
3517/* - SDHI3 ------------------------------------------------------------------ */
3518static const unsigned int sdhi3_data1_pins[] = {
3519 /* D0 */
3520 RCAR_GP_PIN(4, 9),
3521};
3522
3523static const unsigned int sdhi3_data1_mux[] = {
3524 SD3_DAT0_MARK,
3525};
3526
3527static const unsigned int sdhi3_data4_pins[] = {
3528 /* D[0:3] */
3529 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3530 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3531};
3532
3533static const unsigned int sdhi3_data4_mux[] = {
3534 SD3_DAT0_MARK, SD3_DAT1_MARK,
3535 SD3_DAT2_MARK, SD3_DAT3_MARK,
3536};
3537
3538static const unsigned int sdhi3_data8_pins[] = {
3539 /* D[0:7] */
3540 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3541 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3542 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3543 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3544};
3545
3546static const unsigned int sdhi3_data8_mux[] = {
3547 SD3_DAT0_MARK, SD3_DAT1_MARK,
3548 SD3_DAT2_MARK, SD3_DAT3_MARK,
3549 SD3_DAT4_MARK, SD3_DAT5_MARK,
3550 SD3_DAT6_MARK, SD3_DAT7_MARK,
3551};
3552
3553static const unsigned int sdhi3_ctrl_pins[] = {
3554 /* CLK, CMD */
3555 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3556};
3557
3558static const unsigned int sdhi3_ctrl_mux[] = {
3559 SD3_CLK_MARK, SD3_CMD_MARK,
3560};
3561
3562static const unsigned int sdhi3_cd_pins[] = {
3563 /* CD */
3564 RCAR_GP_PIN(4, 15),
3565};
3566
3567static const unsigned int sdhi3_cd_mux[] = {
3568 SD3_CD_MARK,
3569};
3570
3571static const unsigned int sdhi3_wp_pins[] = {
3572 /* WP */
3573 RCAR_GP_PIN(4, 16),
3574};
3575
3576static const unsigned int sdhi3_wp_mux[] = {
3577 SD3_WP_MARK,
3578};
3579
3580static const unsigned int sdhi3_ds_pins[] = {
3581 /* DS */
3582 RCAR_GP_PIN(4, 17),
3583};
3584
3585static const unsigned int sdhi3_ds_mux[] = {
3586 SD3_DS_MARK,
3587};
3588
3589/* - SSI -------------------------------------------------------------------- */
3590static const unsigned int ssi0_data_pins[] = {
3591 /* SDATA */
3592 RCAR_GP_PIN(6, 2),
3593};
3594static const unsigned int ssi0_data_mux[] = {
3595 SSI_SDATA0_MARK,
3596};
3597static const unsigned int ssi01239_ctrl_pins[] = {
3598 /* SCK, WS */
3599 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3600};
3601static const unsigned int ssi01239_ctrl_mux[] = {
3602 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3603};
3604static const unsigned int ssi1_data_a_pins[] = {
3605 /* SDATA */
3606 RCAR_GP_PIN(6, 3),
3607};
3608static const unsigned int ssi1_data_a_mux[] = {
3609 SSI_SDATA1_A_MARK,
3610};
3611static const unsigned int ssi1_data_b_pins[] = {
3612 /* SDATA */
3613 RCAR_GP_PIN(5, 12),
3614};
3615static const unsigned int ssi1_data_b_mux[] = {
3616 SSI_SDATA1_B_MARK,
3617};
3618static const unsigned int ssi1_ctrl_a_pins[] = {
3619 /* SCK, WS */
3620 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3621};
3622static const unsigned int ssi1_ctrl_a_mux[] = {
3623 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3624};
3625static const unsigned int ssi1_ctrl_b_pins[] = {
3626 /* SCK, WS */
3627 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3628};
3629static const unsigned int ssi1_ctrl_b_mux[] = {
3630 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3631};
3632static const unsigned int ssi2_data_a_pins[] = {
3633 /* SDATA */
3634 RCAR_GP_PIN(6, 4),
3635};
3636static const unsigned int ssi2_data_a_mux[] = {
3637 SSI_SDATA2_A_MARK,
3638};
3639static const unsigned int ssi2_data_b_pins[] = {
3640 /* SDATA */
3641 RCAR_GP_PIN(5, 13),
3642};
3643static const unsigned int ssi2_data_b_mux[] = {
3644 SSI_SDATA2_B_MARK,
3645};
3646static const unsigned int ssi2_ctrl_a_pins[] = {
3647 /* SCK, WS */
3648 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3649};
3650static const unsigned int ssi2_ctrl_a_mux[] = {
3651 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3652};
3653static const unsigned int ssi2_ctrl_b_pins[] = {
3654 /* SCK, WS */
3655 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3656};
3657static const unsigned int ssi2_ctrl_b_mux[] = {
3658 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3659};
3660static const unsigned int ssi3_data_pins[] = {
3661 /* SDATA */
3662 RCAR_GP_PIN(6, 7),
3663};
3664static const unsigned int ssi3_data_mux[] = {
3665 SSI_SDATA3_MARK,
3666};
3667static const unsigned int ssi349_ctrl_pins[] = {
3668 /* SCK, WS */
3669 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3670};
3671static const unsigned int ssi349_ctrl_mux[] = {
3672 SSI_SCK349_MARK, SSI_WS349_MARK,
3673};
3674static const unsigned int ssi4_data_pins[] = {
3675 /* SDATA */
3676 RCAR_GP_PIN(6, 10),
3677};
3678static const unsigned int ssi4_data_mux[] = {
3679 SSI_SDATA4_MARK,
3680};
3681static const unsigned int ssi4_ctrl_pins[] = {
3682 /* SCK, WS */
3683 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3684};
3685static const unsigned int ssi4_ctrl_mux[] = {
3686 SSI_SCK4_MARK, SSI_WS4_MARK,
3687};
3688static const unsigned int ssi5_data_pins[] = {
3689 /* SDATA */
3690 RCAR_GP_PIN(6, 13),
3691};
3692static const unsigned int ssi5_data_mux[] = {
3693 SSI_SDATA5_MARK,
3694};
3695static const unsigned int ssi5_ctrl_pins[] = {
3696 /* SCK, WS */
3697 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3698};
3699static const unsigned int ssi5_ctrl_mux[] = {
3700 SSI_SCK5_MARK, SSI_WS5_MARK,
3701};
3702static const unsigned int ssi6_data_pins[] = {
3703 /* SDATA */
3704 RCAR_GP_PIN(6, 16),
3705};
3706static const unsigned int ssi6_data_mux[] = {
3707 SSI_SDATA6_MARK,
3708};
3709static const unsigned int ssi6_ctrl_pins[] = {
3710 /* SCK, WS */
3711 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3712};
3713static const unsigned int ssi6_ctrl_mux[] = {
3714 SSI_SCK6_MARK, SSI_WS6_MARK,
3715};
3716static const unsigned int ssi7_data_pins[] = {
3717 /* SDATA */
3718 RCAR_GP_PIN(6, 19),
3719};
3720static const unsigned int ssi7_data_mux[] = {
3721 SSI_SDATA7_MARK,
3722};
3723static const unsigned int ssi78_ctrl_pins[] = {
3724 /* SCK, WS */
3725 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3726};
3727static const unsigned int ssi78_ctrl_mux[] = {
3728 SSI_SCK78_MARK, SSI_WS78_MARK,
3729};
3730static const unsigned int ssi8_data_pins[] = {
3731 /* SDATA */
3732 RCAR_GP_PIN(6, 20),
3733};
3734static const unsigned int ssi8_data_mux[] = {
3735 SSI_SDATA8_MARK,
3736};
3737static const unsigned int ssi9_data_a_pins[] = {
3738 /* SDATA */
3739 RCAR_GP_PIN(6, 21),
3740};
3741static const unsigned int ssi9_data_a_mux[] = {
3742 SSI_SDATA9_A_MARK,
3743};
3744static const unsigned int ssi9_data_b_pins[] = {
3745 /* SDATA */
3746 RCAR_GP_PIN(5, 14),
3747};
3748static const unsigned int ssi9_data_b_mux[] = {
3749 SSI_SDATA9_B_MARK,
3750};
3751static const unsigned int ssi9_ctrl_a_pins[] = {
3752 /* SCK, WS */
3753 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3754};
3755static const unsigned int ssi9_ctrl_a_mux[] = {
3756 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3757};
3758static const unsigned int ssi9_ctrl_b_pins[] = {
3759 /* SCK, WS */
3760 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3761};
3762static const unsigned int ssi9_ctrl_b_mux[] = {
3763 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3764};
3765
3766
3767/* - USB0 ------------------------------------------------------------------- */
3768static const unsigned int usb0_pins[] = {
3769 /* PWEN, OVC */
3770 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3771};
3772
3773static const unsigned int usb0_mux[] = {
3774 USB0_PWEN_MARK, USB0_OVC_MARK,
3775};
3776
3777/* - USB1 ------------------------------------------------------------------- */
3778static const unsigned int usb1_pins[] = {
3779 /* PWEN, OVC */
3780 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3781};
3782
3783static const unsigned int usb1_mux[] = {
3784 USB1_PWEN_MARK, USB1_OVC_MARK,
3785};
3786
3787/* - USB30 ------------------------------------------------------------------ */
3788static const unsigned int usb30_pins[] = {
3789 /* PWEN, OVC */
3790 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3791};
3792
3793static const unsigned int usb30_mux[] = {
3794 USB30_PWEN_MARK, USB30_OVC_MARK,
3795};
3796
3797/* - VIN4 ------------------------------------------------------------------- */
3798static const unsigned int vin4_data18_a_pins[] = {
3799 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3800 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3801 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3802 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3803 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3804 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3805 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3806 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3807 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3808};
3809
3810static const unsigned int vin4_data18_a_mux[] = {
3811 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3812 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3813 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3814 VI4_DATA10_MARK, VI4_DATA11_MARK,
3815 VI4_DATA12_MARK, VI4_DATA13_MARK,
3816 VI4_DATA14_MARK, VI4_DATA15_MARK,
3817 VI4_DATA18_MARK, VI4_DATA19_MARK,
3818 VI4_DATA20_MARK, VI4_DATA21_MARK,
3819 VI4_DATA22_MARK, VI4_DATA23_MARK,
3820};
3821
3822static const union vin_data vin4_data_a_pins = {
3823 .data24 = {
3824 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3825 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3826 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3827 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3828 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3829 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3830 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3831 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3832 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3833 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3834 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3835 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3836 },
3837};
3838
3839static const union vin_data vin4_data_a_mux = {
3840 .data24 = {
3841 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
3842 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3843 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3844 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3845 VI4_DATA8_MARK, VI4_DATA9_MARK,
3846 VI4_DATA10_MARK, VI4_DATA11_MARK,
3847 VI4_DATA12_MARK, VI4_DATA13_MARK,
3848 VI4_DATA14_MARK, VI4_DATA15_MARK,
3849 VI4_DATA16_MARK, VI4_DATA17_MARK,
3850 VI4_DATA18_MARK, VI4_DATA19_MARK,
3851 VI4_DATA20_MARK, VI4_DATA21_MARK,
3852 VI4_DATA22_MARK, VI4_DATA23_MARK,
3853 },
3854};
3855
3856static const unsigned int vin4_data18_b_pins[] = {
3857 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3858 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3859 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3860 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3861 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3862 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3863 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3864 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3865 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3866};
3867
3868static const unsigned int vin4_data18_b_mux[] = {
3869 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3870 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3871 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3872 VI4_DATA10_MARK, VI4_DATA11_MARK,
3873 VI4_DATA12_MARK, VI4_DATA13_MARK,
3874 VI4_DATA14_MARK, VI4_DATA15_MARK,
3875 VI4_DATA18_MARK, VI4_DATA19_MARK,
3876 VI4_DATA20_MARK, VI4_DATA21_MARK,
3877 VI4_DATA22_MARK, VI4_DATA23_MARK,
3878};
3879
3880static const union vin_data vin4_data_b_pins = {
3881 .data24 = {
3882 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3883 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3884 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3885 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3886 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3887 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3888 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3889 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3890 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3891 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3892 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3893 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3894 },
3895};
3896
3897static const union vin_data vin4_data_b_mux = {
3898 .data24 = {
3899 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
3900 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3901 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3902 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3903 VI4_DATA8_MARK, VI4_DATA9_MARK,
3904 VI4_DATA10_MARK, VI4_DATA11_MARK,
3905 VI4_DATA12_MARK, VI4_DATA13_MARK,
3906 VI4_DATA14_MARK, VI4_DATA15_MARK,
3907 VI4_DATA16_MARK, VI4_DATA17_MARK,
3908 VI4_DATA18_MARK, VI4_DATA19_MARK,
3909 VI4_DATA20_MARK, VI4_DATA21_MARK,
3910 VI4_DATA22_MARK, VI4_DATA23_MARK,
3911 },
3912};
3913
3914static const unsigned int vin4_sync_pins[] = {
3915 /* VSYNC_N, HSYNC_N */
3916 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3917};
3918
3919static const unsigned int vin4_sync_mux[] = {
3920 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
3921};
3922
3923static const unsigned int vin4_field_pins[] = {
3924 RCAR_GP_PIN(1, 16),
3925};
3926
3927static const unsigned int vin4_field_mux[] = {
3928 VI4_FIELD_MARK,
3929};
3930
3931static const unsigned int vin4_clkenb_pins[] = {
3932 RCAR_GP_PIN(1, 19),
3933};
3934
3935static const unsigned int vin4_clkenb_mux[] = {
3936 VI4_CLKENB_MARK,
3937};
3938
3939static const unsigned int vin4_clk_pins[] = {
3940 RCAR_GP_PIN(1, 27),
3941};
3942
3943static const unsigned int vin4_clk_mux[] = {
3944 VI4_CLK_MARK,
3945};
3946
3947/* - VIN5 ------------------------------------------------------------------- */
3948static const union vin_data16 vin5_data_pins = {
3949 .data16 = {
3950 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3951 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3952 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3953 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3954 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3955 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3956 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3957 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3958 },
3959};
3960
3961static const union vin_data16 vin5_data_mux = {
3962 .data16 = {
3963 VI5_DATA0_MARK, VI5_DATA1_MARK,
3964 VI5_DATA2_MARK, VI5_DATA3_MARK,
3965 VI5_DATA4_MARK, VI5_DATA5_MARK,
3966 VI5_DATA6_MARK, VI5_DATA7_MARK,
3967 VI5_DATA8_MARK, VI5_DATA9_MARK,
3968 VI5_DATA10_MARK, VI5_DATA11_MARK,
3969 VI5_DATA12_MARK, VI5_DATA13_MARK,
3970 VI5_DATA14_MARK, VI5_DATA15_MARK,
3971 },
3972};
3973
3974static const unsigned int vin5_sync_pins[] = {
3975 /* VSYNC_N, HSYNC_N */
3976 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
3977};
3978
3979static const unsigned int vin5_sync_mux[] = {
3980 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
3981};
3982
3983static const unsigned int vin5_field_pins[] = {
3984 RCAR_GP_PIN(1, 11),
3985};
3986
3987static const unsigned int vin5_field_mux[] = {
3988 VI5_FIELD_MARK,
3989};
3990
3991static const unsigned int vin5_clkenb_pins[] = {
3992 RCAR_GP_PIN(1, 20),
3993};
3994
3995static const unsigned int vin5_clkenb_mux[] = {
3996 VI5_CLKENB_MARK,
3997};
3998
3999static const unsigned int vin5_clk_pins[] = {
4000 RCAR_GP_PIN(1, 21),
4001};
4002
4003static const unsigned int vin5_clk_mux[] = {
4004 VI5_CLK_MARK,
4005};
4006
4007static const struct sh_pfc_pin_group pinmux_groups[] = {
4008 SH_PFC_PIN_GROUP(audio_clk_a_a),
4009 SH_PFC_PIN_GROUP(audio_clk_a_b),
4010 SH_PFC_PIN_GROUP(audio_clk_a_c),
4011 SH_PFC_PIN_GROUP(audio_clk_b_a),
4012 SH_PFC_PIN_GROUP(audio_clk_b_b),
4013 SH_PFC_PIN_GROUP(audio_clk_c_a),
4014 SH_PFC_PIN_GROUP(audio_clk_c_b),
4015 SH_PFC_PIN_GROUP(audio_clkout_a),
4016 SH_PFC_PIN_GROUP(audio_clkout_b),
4017 SH_PFC_PIN_GROUP(audio_clkout_c),
4018 SH_PFC_PIN_GROUP(audio_clkout_d),
4019 SH_PFC_PIN_GROUP(audio_clkout1_a),
4020 SH_PFC_PIN_GROUP(audio_clkout1_b),
4021 SH_PFC_PIN_GROUP(audio_clkout2_a),
4022 SH_PFC_PIN_GROUP(audio_clkout2_b),
4023 SH_PFC_PIN_GROUP(audio_clkout3_a),
4024 SH_PFC_PIN_GROUP(audio_clkout3_b),
4025 SH_PFC_PIN_GROUP(avb_link),
4026 SH_PFC_PIN_GROUP(avb_magic),
4027 SH_PFC_PIN_GROUP(avb_phy_int),
4028 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4029 SH_PFC_PIN_GROUP(avb_mdio),
4030 SH_PFC_PIN_GROUP(avb_mii),
4031 SH_PFC_PIN_GROUP(avb_avtp_pps),
4032 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4033 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4034 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4035 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4036 SH_PFC_PIN_GROUP(can0_data_a),
4037 SH_PFC_PIN_GROUP(can0_data_b),
4038 SH_PFC_PIN_GROUP(can1_data),
4039 SH_PFC_PIN_GROUP(can_clk),
4040 SH_PFC_PIN_GROUP(canfd0_data_a),
4041 SH_PFC_PIN_GROUP(canfd0_data_b),
4042 SH_PFC_PIN_GROUP(canfd1_data),
4043 SH_PFC_PIN_GROUP(du_rgb666),
4044 SH_PFC_PIN_GROUP(du_rgb888),
4045 SH_PFC_PIN_GROUP(du_clk_out_0),
4046 SH_PFC_PIN_GROUP(du_clk_out_1),
4047 SH_PFC_PIN_GROUP(du_sync),
4048 SH_PFC_PIN_GROUP(du_oddf),
4049 SH_PFC_PIN_GROUP(du_cde),
4050 SH_PFC_PIN_GROUP(du_disp),
4051 SH_PFC_PIN_GROUP(hscif0_data),
4052 SH_PFC_PIN_GROUP(hscif0_clk),
4053 SH_PFC_PIN_GROUP(hscif0_ctrl),
4054 SH_PFC_PIN_GROUP(hscif1_data_a),
4055 SH_PFC_PIN_GROUP(hscif1_clk_a),
4056 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4057 SH_PFC_PIN_GROUP(hscif1_data_b),
4058 SH_PFC_PIN_GROUP(hscif1_clk_b),
4059 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4060 SH_PFC_PIN_GROUP(hscif2_data_a),
4061 SH_PFC_PIN_GROUP(hscif2_clk_a),
4062 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4063 SH_PFC_PIN_GROUP(hscif2_data_b),
4064 SH_PFC_PIN_GROUP(hscif2_clk_b),
4065 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4066 SH_PFC_PIN_GROUP(hscif2_data_c),
4067 SH_PFC_PIN_GROUP(hscif2_clk_c),
4068 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4069 SH_PFC_PIN_GROUP(hscif3_data_a),
4070 SH_PFC_PIN_GROUP(hscif3_clk),
4071 SH_PFC_PIN_GROUP(hscif3_ctrl),
4072 SH_PFC_PIN_GROUP(hscif3_data_b),
4073 SH_PFC_PIN_GROUP(hscif3_data_c),
4074 SH_PFC_PIN_GROUP(hscif3_data_d),
4075 SH_PFC_PIN_GROUP(hscif4_data_a),
4076 SH_PFC_PIN_GROUP(hscif4_clk),
4077 SH_PFC_PIN_GROUP(hscif4_ctrl),
4078 SH_PFC_PIN_GROUP(hscif4_data_b),
4079 SH_PFC_PIN_GROUP(i2c1_a),
4080 SH_PFC_PIN_GROUP(i2c1_b),
4081 SH_PFC_PIN_GROUP(i2c2_a),
4082 SH_PFC_PIN_GROUP(i2c2_b),
4083 SH_PFC_PIN_GROUP(i2c6_a),
4084 SH_PFC_PIN_GROUP(i2c6_b),
4085 SH_PFC_PIN_GROUP(i2c6_c),
4086 SH_PFC_PIN_GROUP(intc_ex_irq0),
4087 SH_PFC_PIN_GROUP(intc_ex_irq1),
4088 SH_PFC_PIN_GROUP(intc_ex_irq2),
4089 SH_PFC_PIN_GROUP(intc_ex_irq3),
4090 SH_PFC_PIN_GROUP(intc_ex_irq4),
4091 SH_PFC_PIN_GROUP(intc_ex_irq5),
4092 SH_PFC_PIN_GROUP(msiof0_clk),
4093 SH_PFC_PIN_GROUP(msiof0_sync),
4094 SH_PFC_PIN_GROUP(msiof0_ss1),
4095 SH_PFC_PIN_GROUP(msiof0_ss2),
4096 SH_PFC_PIN_GROUP(msiof0_txd),
4097 SH_PFC_PIN_GROUP(msiof0_rxd),
4098 SH_PFC_PIN_GROUP(msiof1_clk_a),
4099 SH_PFC_PIN_GROUP(msiof1_sync_a),
4100 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4101 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4102 SH_PFC_PIN_GROUP(msiof1_txd_a),
4103 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4104 SH_PFC_PIN_GROUP(msiof1_clk_b),
4105 SH_PFC_PIN_GROUP(msiof1_sync_b),
4106 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4107 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4108 SH_PFC_PIN_GROUP(msiof1_txd_b),
4109 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4110 SH_PFC_PIN_GROUP(msiof1_clk_c),
4111 SH_PFC_PIN_GROUP(msiof1_sync_c),
4112 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4113 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4114 SH_PFC_PIN_GROUP(msiof1_txd_c),
4115 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4116 SH_PFC_PIN_GROUP(msiof1_clk_d),
4117 SH_PFC_PIN_GROUP(msiof1_sync_d),
4118 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4119 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4120 SH_PFC_PIN_GROUP(msiof1_txd_d),
4121 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4122 SH_PFC_PIN_GROUP(msiof1_clk_e),
4123 SH_PFC_PIN_GROUP(msiof1_sync_e),
4124 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4125 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4126 SH_PFC_PIN_GROUP(msiof1_txd_e),
4127 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4128 SH_PFC_PIN_GROUP(msiof1_clk_f),
4129 SH_PFC_PIN_GROUP(msiof1_sync_f),
4130 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4131 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4132 SH_PFC_PIN_GROUP(msiof1_txd_f),
4133 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4134 SH_PFC_PIN_GROUP(msiof1_clk_g),
4135 SH_PFC_PIN_GROUP(msiof1_sync_g),
4136 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4137 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4138 SH_PFC_PIN_GROUP(msiof1_txd_g),
4139 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4140 SH_PFC_PIN_GROUP(msiof2_clk_a),
4141 SH_PFC_PIN_GROUP(msiof2_sync_a),
4142 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4143 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4144 SH_PFC_PIN_GROUP(msiof2_txd_a),
4145 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4146 SH_PFC_PIN_GROUP(msiof2_clk_b),
4147 SH_PFC_PIN_GROUP(msiof2_sync_b),
4148 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4149 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4150 SH_PFC_PIN_GROUP(msiof2_txd_b),
4151 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4152 SH_PFC_PIN_GROUP(msiof2_clk_c),
4153 SH_PFC_PIN_GROUP(msiof2_sync_c),
4154 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4155 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4156 SH_PFC_PIN_GROUP(msiof2_txd_c),
4157 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4158 SH_PFC_PIN_GROUP(msiof2_clk_d),
4159 SH_PFC_PIN_GROUP(msiof2_sync_d),
4160 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4161 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4162 SH_PFC_PIN_GROUP(msiof2_txd_d),
4163 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4164 SH_PFC_PIN_GROUP(msiof3_clk_a),
4165 SH_PFC_PIN_GROUP(msiof3_sync_a),
4166 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4167 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4168 SH_PFC_PIN_GROUP(msiof3_txd_a),
4169 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4170 SH_PFC_PIN_GROUP(msiof3_clk_b),
4171 SH_PFC_PIN_GROUP(msiof3_sync_b),
4172 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4173 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4174 SH_PFC_PIN_GROUP(msiof3_txd_b),
4175 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4176 SH_PFC_PIN_GROUP(msiof3_clk_c),
4177 SH_PFC_PIN_GROUP(msiof3_sync_c),
4178 SH_PFC_PIN_GROUP(msiof3_txd_c),
4179 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4180 SH_PFC_PIN_GROUP(msiof3_clk_d),
4181 SH_PFC_PIN_GROUP(msiof3_sync_d),
4182 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4183 SH_PFC_PIN_GROUP(msiof3_txd_d),
4184 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4185 SH_PFC_PIN_GROUP(msiof3_clk_e),
4186 SH_PFC_PIN_GROUP(msiof3_sync_e),
4187 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4188 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4189 SH_PFC_PIN_GROUP(msiof3_txd_e),
4190 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4191 SH_PFC_PIN_GROUP(pwm0),
4192 SH_PFC_PIN_GROUP(pwm1_a),
4193 SH_PFC_PIN_GROUP(pwm1_b),
4194 SH_PFC_PIN_GROUP(pwm2_a),
4195 SH_PFC_PIN_GROUP(pwm2_b),
4196 SH_PFC_PIN_GROUP(pwm3_a),
4197 SH_PFC_PIN_GROUP(pwm3_b),
4198 SH_PFC_PIN_GROUP(pwm4_a),
4199 SH_PFC_PIN_GROUP(pwm4_b),
4200 SH_PFC_PIN_GROUP(pwm5_a),
4201 SH_PFC_PIN_GROUP(pwm5_b),
4202 SH_PFC_PIN_GROUP(pwm6_a),
4203 SH_PFC_PIN_GROUP(pwm6_b),
4204 SH_PFC_PIN_GROUP(sata0_devslp_a),
4205 SH_PFC_PIN_GROUP(sata0_devslp_b),
4206 SH_PFC_PIN_GROUP(scif0_data),
4207 SH_PFC_PIN_GROUP(scif0_clk),
4208 SH_PFC_PIN_GROUP(scif0_ctrl),
4209 SH_PFC_PIN_GROUP(scif1_data_a),
4210 SH_PFC_PIN_GROUP(scif1_clk),
4211 SH_PFC_PIN_GROUP(scif1_ctrl),
4212 SH_PFC_PIN_GROUP(scif1_data_b),
4213 SH_PFC_PIN_GROUP(scif2_data_a),
4214 SH_PFC_PIN_GROUP(scif2_clk),
4215 SH_PFC_PIN_GROUP(scif2_data_b),
4216 SH_PFC_PIN_GROUP(scif3_data_a),
4217 SH_PFC_PIN_GROUP(scif3_clk),
4218 SH_PFC_PIN_GROUP(scif3_ctrl),
4219 SH_PFC_PIN_GROUP(scif3_data_b),
4220 SH_PFC_PIN_GROUP(scif4_data_a),
4221 SH_PFC_PIN_GROUP(scif4_clk_a),
4222 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4223 SH_PFC_PIN_GROUP(scif4_data_b),
4224 SH_PFC_PIN_GROUP(scif4_clk_b),
4225 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4226 SH_PFC_PIN_GROUP(scif4_data_c),
4227 SH_PFC_PIN_GROUP(scif4_clk_c),
4228 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4229 SH_PFC_PIN_GROUP(scif5_data_a),
4230 SH_PFC_PIN_GROUP(scif5_clk_a),
4231 SH_PFC_PIN_GROUP(scif5_data_b),
4232 SH_PFC_PIN_GROUP(scif5_clk_b),
4233 SH_PFC_PIN_GROUP(scif_clk_a),
4234 SH_PFC_PIN_GROUP(scif_clk_b),
4235 SH_PFC_PIN_GROUP(sdhi0_data1),
4236 SH_PFC_PIN_GROUP(sdhi0_data4),
4237 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4238 SH_PFC_PIN_GROUP(sdhi0_cd),
4239 SH_PFC_PIN_GROUP(sdhi0_wp),
4240 SH_PFC_PIN_GROUP(sdhi1_data1),
4241 SH_PFC_PIN_GROUP(sdhi1_data4),
4242 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4243 SH_PFC_PIN_GROUP(sdhi1_cd),
4244 SH_PFC_PIN_GROUP(sdhi1_wp),
4245 SH_PFC_PIN_GROUP(sdhi2_data1),
4246 SH_PFC_PIN_GROUP(sdhi2_data4),
4247 SH_PFC_PIN_GROUP(sdhi2_data8),
4248 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4249 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4250 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4251 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4252 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4253 SH_PFC_PIN_GROUP(sdhi2_ds),
4254 SH_PFC_PIN_GROUP(sdhi3_data1),
4255 SH_PFC_PIN_GROUP(sdhi3_data4),
4256 SH_PFC_PIN_GROUP(sdhi3_data8),
4257 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4258 SH_PFC_PIN_GROUP(sdhi3_cd),
4259 SH_PFC_PIN_GROUP(sdhi3_wp),
4260 SH_PFC_PIN_GROUP(sdhi3_ds),
4261 SH_PFC_PIN_GROUP(ssi0_data),
4262 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4263 SH_PFC_PIN_GROUP(ssi1_data_a),
4264 SH_PFC_PIN_GROUP(ssi1_data_b),
4265 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4266 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4267 SH_PFC_PIN_GROUP(ssi2_data_a),
4268 SH_PFC_PIN_GROUP(ssi2_data_b),
4269 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4270 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4271 SH_PFC_PIN_GROUP(ssi3_data),
4272 SH_PFC_PIN_GROUP(ssi349_ctrl),
4273 SH_PFC_PIN_GROUP(ssi4_data),
4274 SH_PFC_PIN_GROUP(ssi4_ctrl),
4275 SH_PFC_PIN_GROUP(ssi5_data),
4276 SH_PFC_PIN_GROUP(ssi5_ctrl),
4277 SH_PFC_PIN_GROUP(ssi6_data),
4278 SH_PFC_PIN_GROUP(ssi6_ctrl),
4279 SH_PFC_PIN_GROUP(ssi7_data),
4280 SH_PFC_PIN_GROUP(ssi78_ctrl),
4281 SH_PFC_PIN_GROUP(ssi8_data),
4282 SH_PFC_PIN_GROUP(ssi9_data_a),
4283 SH_PFC_PIN_GROUP(ssi9_data_b),
4284 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4285 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4286 SH_PFC_PIN_GROUP(usb0),
4287 SH_PFC_PIN_GROUP(usb1),
4288 SH_PFC_PIN_GROUP(usb30),
4289 VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4290 VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4291 VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4292 VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4293 SH_PFC_PIN_GROUP(vin4_data18_a),
4294 VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4295 VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4296 VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4297 VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4298 VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4299 VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4300 SH_PFC_PIN_GROUP(vin4_data18_b),
4301 VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4302 VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4303 SH_PFC_PIN_GROUP(vin4_sync),
4304 SH_PFC_PIN_GROUP(vin4_field),
4305 SH_PFC_PIN_GROUP(vin4_clkenb),
4306 SH_PFC_PIN_GROUP(vin4_clk),
4307 VIN_DATA_PIN_GROUP(vin5_data, 8),
4308 VIN_DATA_PIN_GROUP(vin5_data, 10),
4309 VIN_DATA_PIN_GROUP(vin5_data, 12),
4310 VIN_DATA_PIN_GROUP(vin5_data, 16),
4311 SH_PFC_PIN_GROUP(vin5_sync),
4312 SH_PFC_PIN_GROUP(vin5_field),
4313 SH_PFC_PIN_GROUP(vin5_clkenb),
4314 SH_PFC_PIN_GROUP(vin5_clk),
4315};
4316
4317static const char * const audio_clk_groups[] = {
4318 "audio_clk_a_a",
4319 "audio_clk_a_b",
4320 "audio_clk_a_c",
4321 "audio_clk_b_a",
4322 "audio_clk_b_b",
4323 "audio_clk_c_a",
4324 "audio_clk_c_b",
4325 "audio_clkout_a",
4326 "audio_clkout_b",
4327 "audio_clkout_c",
4328 "audio_clkout_d",
4329 "audio_clkout1_a",
4330 "audio_clkout1_b",
4331 "audio_clkout2_a",
4332 "audio_clkout2_b",
4333 "audio_clkout3_a",
4334 "audio_clkout3_b",
4335};
4336
4337static const char * const avb_groups[] = {
4338 "avb_link",
4339 "avb_magic",
4340 "avb_phy_int",
4341 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4342 "avb_mdio",
4343 "avb_mii",
4344 "avb_avtp_pps",
4345 "avb_avtp_match_a",
4346 "avb_avtp_capture_a",
4347 "avb_avtp_match_b",
4348 "avb_avtp_capture_b",
4349};
4350
4351static const char * const can0_groups[] = {
4352 "can0_data_a",
4353 "can0_data_b",
4354};
4355
4356static const char * const can1_groups[] = {
4357 "can1_data",
4358};
4359
4360static const char * const can_clk_groups[] = {
4361 "can_clk",
4362};
4363
4364static const char * const canfd0_groups[] = {
4365 "canfd0_data_a",
4366 "canfd0_data_b",
4367};
4368
4369static const char * const canfd1_groups[] = {
4370 "canfd1_data",
4371};
4372
4373static const char * const du_groups[] = {
4374 "du_rgb666",
4375 "du_rgb888",
4376 "du_clk_out_0",
4377 "du_clk_out_1",
4378 "du_sync",
4379 "du_oddf",
4380 "du_cde",
4381 "du_disp",
4382};
4383
4384static const char * const hscif0_groups[] = {
4385 "hscif0_data",
4386 "hscif0_clk",
4387 "hscif0_ctrl",
4388};
4389
4390static const char * const hscif1_groups[] = {
4391 "hscif1_data_a",
4392 "hscif1_clk_a",
4393 "hscif1_ctrl_a",
4394 "hscif1_data_b",
4395 "hscif1_clk_b",
4396 "hscif1_ctrl_b",
4397};
4398
4399static const char * const hscif2_groups[] = {
4400 "hscif2_data_a",
4401 "hscif2_clk_a",
4402 "hscif2_ctrl_a",
4403 "hscif2_data_b",
4404 "hscif2_clk_b",
4405 "hscif2_ctrl_b",
4406 "hscif2_data_c",
4407 "hscif2_clk_c",
4408 "hscif2_ctrl_c",
4409};
4410
4411static const char * const hscif3_groups[] = {
4412 "hscif3_data_a",
4413 "hscif3_clk",
4414 "hscif3_ctrl",
4415 "hscif3_data_b",
4416 "hscif3_data_c",
4417 "hscif3_data_d",
4418};
4419
4420static const char * const hscif4_groups[] = {
4421 "hscif4_data_a",
4422 "hscif4_clk",
4423 "hscif4_ctrl",
4424 "hscif4_data_b",
4425};
4426
4427static const char * const i2c1_groups[] = {
4428 "i2c1_a",
4429 "i2c1_b",
4430};
4431
4432static const char * const i2c2_groups[] = {
4433 "i2c2_a",
4434 "i2c2_b",
4435};
4436
4437static const char * const i2c6_groups[] = {
4438 "i2c6_a",
4439 "i2c6_b",
4440 "i2c6_c",
4441};
4442
4443static const char * const intc_ex_groups[] = {
4444 "intc_ex_irq0",
4445 "intc_ex_irq1",
4446 "intc_ex_irq2",
4447 "intc_ex_irq3",
4448 "intc_ex_irq4",
4449 "intc_ex_irq5",
4450};
4451
4452static const char * const msiof0_groups[] = {
4453 "msiof0_clk",
4454 "msiof0_sync",
4455 "msiof0_ss1",
4456 "msiof0_ss2",
4457 "msiof0_txd",
4458 "msiof0_rxd",
4459};
4460
4461static const char * const msiof1_groups[] = {
4462 "msiof1_clk_a",
4463 "msiof1_sync_a",
4464 "msiof1_ss1_a",
4465 "msiof1_ss2_a",
4466 "msiof1_txd_a",
4467 "msiof1_rxd_a",
4468 "msiof1_clk_b",
4469 "msiof1_sync_b",
4470 "msiof1_ss1_b",
4471 "msiof1_ss2_b",
4472 "msiof1_txd_b",
4473 "msiof1_rxd_b",
4474 "msiof1_clk_c",
4475 "msiof1_sync_c",
4476 "msiof1_ss1_c",
4477 "msiof1_ss2_c",
4478 "msiof1_txd_c",
4479 "msiof1_rxd_c",
4480 "msiof1_clk_d",
4481 "msiof1_sync_d",
4482 "msiof1_ss1_d",
4483 "msiof1_ss2_d",
4484 "msiof1_txd_d",
4485 "msiof1_rxd_d",
4486 "msiof1_clk_e",
4487 "msiof1_sync_e",
4488 "msiof1_ss1_e",
4489 "msiof1_ss2_e",
4490 "msiof1_txd_e",
4491 "msiof1_rxd_e",
4492 "msiof1_clk_f",
4493 "msiof1_sync_f",
4494 "msiof1_ss1_f",
4495 "msiof1_ss2_f",
4496 "msiof1_txd_f",
4497 "msiof1_rxd_f",
4498 "msiof1_clk_g",
4499 "msiof1_sync_g",
4500 "msiof1_ss1_g",
4501 "msiof1_ss2_g",
4502 "msiof1_txd_g",
4503 "msiof1_rxd_g",
4504};
4505
4506static const char * const msiof2_groups[] = {
4507 "msiof2_clk_a",
4508 "msiof2_sync_a",
4509 "msiof2_ss1_a",
4510 "msiof2_ss2_a",
4511 "msiof2_txd_a",
4512 "msiof2_rxd_a",
4513 "msiof2_clk_b",
4514 "msiof2_sync_b",
4515 "msiof2_ss1_b",
4516 "msiof2_ss2_b",
4517 "msiof2_txd_b",
4518 "msiof2_rxd_b",
4519 "msiof2_clk_c",
4520 "msiof2_sync_c",
4521 "msiof2_ss1_c",
4522 "msiof2_ss2_c",
4523 "msiof2_txd_c",
4524 "msiof2_rxd_c",
4525 "msiof2_clk_d",
4526 "msiof2_sync_d",
4527 "msiof2_ss1_d",
4528 "msiof2_ss2_d",
4529 "msiof2_txd_d",
4530 "msiof2_rxd_d",
4531};
4532
4533static const char * const msiof3_groups[] = {
4534 "msiof3_clk_a",
4535 "msiof3_sync_a",
4536 "msiof3_ss1_a",
4537 "msiof3_ss2_a",
4538 "msiof3_txd_a",
4539 "msiof3_rxd_a",
4540 "msiof3_clk_b",
4541 "msiof3_sync_b",
4542 "msiof3_ss1_b",
4543 "msiof3_ss2_b",
4544 "msiof3_txd_b",
4545 "msiof3_rxd_b",
4546 "msiof3_clk_c",
4547 "msiof3_sync_c",
4548 "msiof3_txd_c",
4549 "msiof3_rxd_c",
4550 "msiof3_clk_d",
4551 "msiof3_sync_d",
4552 "msiof3_ss1_d",
4553 "msiof3_txd_d",
4554 "msiof3_rxd_d",
4555 "msiof3_clk_e",
4556 "msiof3_sync_e",
4557 "msiof3_ss1_e",
4558 "msiof3_ss2_e",
4559 "msiof3_txd_e",
4560 "msiof3_rxd_e",
4561};
4562
4563static const char * const pwm0_groups[] = {
4564 "pwm0",
4565};
4566
4567static const char * const pwm1_groups[] = {
4568 "pwm1_a",
4569 "pwm1_b",
4570};
4571
4572static const char * const pwm2_groups[] = {
4573 "pwm2_a",
4574 "pwm2_b",
4575};
4576
4577static const char * const pwm3_groups[] = {
4578 "pwm3_a",
4579 "pwm3_b",
4580};
4581
4582static const char * const pwm4_groups[] = {
4583 "pwm4_a",
4584 "pwm4_b",
4585};
4586
4587static const char * const pwm5_groups[] = {
4588 "pwm5_a",
4589 "pwm5_b",
4590};
4591
4592static const char * const pwm6_groups[] = {
4593 "pwm6_a",
4594 "pwm6_b",
4595};
4596
4597static const char * const sata0_groups[] = {
4598 "sata0_devslp_a",
4599 "sata0_devslp_b",
4600};
4601
4602static const char * const scif0_groups[] = {
4603 "scif0_data",
4604 "scif0_clk",
4605 "scif0_ctrl",
4606};
4607
4608static const char * const scif1_groups[] = {
4609 "scif1_data_a",
4610 "scif1_clk",
4611 "scif1_ctrl",
4612 "scif1_data_b",
4613};
4614static const char * const scif2_groups[] = {
4615 "scif2_data_a",
4616 "scif2_clk",
4617 "scif2_data_b",
4618};
4619
4620static const char * const scif3_groups[] = {
4621 "scif3_data_a",
4622 "scif3_clk",
4623 "scif3_ctrl",
4624 "scif3_data_b",
4625};
4626
4627static const char * const scif4_groups[] = {
4628 "scif4_data_a",
4629 "scif4_clk_a",
4630 "scif4_ctrl_a",
4631 "scif4_data_b",
4632 "scif4_clk_b",
4633 "scif4_ctrl_b",
4634 "scif4_data_c",
4635 "scif4_clk_c",
4636 "scif4_ctrl_c",
4637};
4638
4639static const char * const scif5_groups[] = {
4640 "scif5_data_a",
4641 "scif5_clk_a",
4642 "scif5_data_b",
4643 "scif5_clk_b",
4644};
4645
4646static const char * const scif_clk_groups[] = {
4647 "scif_clk_a",
4648 "scif_clk_b",
4649};
4650
4651static const char * const sdhi0_groups[] = {
4652 "sdhi0_data1",
4653 "sdhi0_data4",
4654 "sdhi0_ctrl",
4655 "sdhi0_cd",
4656 "sdhi0_wp",
4657};
4658
4659static const char * const sdhi1_groups[] = {
4660 "sdhi1_data1",
4661 "sdhi1_data4",
4662 "sdhi1_ctrl",
4663 "sdhi1_cd",
4664 "sdhi1_wp",
4665};
4666
4667static const char * const sdhi2_groups[] = {
4668 "sdhi2_data1",
4669 "sdhi2_data4",
4670 "sdhi2_data8",
4671 "sdhi2_ctrl",
4672 "sdhi2_cd_a",
4673 "sdhi2_wp_a",
4674 "sdhi2_cd_b",
4675 "sdhi2_wp_b",
4676 "sdhi2_ds",
4677};
4678
4679static const char * const sdhi3_groups[] = {
4680 "sdhi3_data1",
4681 "sdhi3_data4",
4682 "sdhi3_data8",
4683 "sdhi3_ctrl",
4684 "sdhi3_cd",
4685 "sdhi3_wp",
4686 "sdhi3_ds",
4687};
4688
4689static const char * const ssi_groups[] = {
4690 "ssi0_data",
4691 "ssi01239_ctrl",
4692 "ssi1_data_a",
4693 "ssi1_data_b",
4694 "ssi1_ctrl_a",
4695 "ssi1_ctrl_b",
4696 "ssi2_data_a",
4697 "ssi2_data_b",
4698 "ssi2_ctrl_a",
4699 "ssi2_ctrl_b",
4700 "ssi3_data",
4701 "ssi349_ctrl",
4702 "ssi4_data",
4703 "ssi4_ctrl",
4704 "ssi5_data",
4705 "ssi5_ctrl",
4706 "ssi6_data",
4707 "ssi6_ctrl",
4708 "ssi7_data",
4709 "ssi78_ctrl",
4710 "ssi8_data",
4711 "ssi9_data_a",
4712 "ssi9_data_b",
4713 "ssi9_ctrl_a",
4714 "ssi9_ctrl_b",
4715};
4716
4717static const char * const usb0_groups[] = {
4718 "usb0",
4719};
4720
4721static const char * const usb1_groups[] = {
4722 "usb1",
4723};
4724
4725static const char * const usb30_groups[] = {
4726 "usb30",
4727};
4728
4729static const char * const vin4_groups[] = {
4730 "vin4_data8_a",
4731 "vin4_data10_a",
4732 "vin4_data12_a",
4733 "vin4_data16_a",
4734 "vin4_data18_a",
4735 "vin4_data20_a",
4736 "vin4_data24_a",
4737 "vin4_data8_b",
4738 "vin4_data10_b",
4739 "vin4_data12_b",
4740 "vin4_data16_b",
4741 "vin4_data18_b",
4742 "vin4_data20_b",
4743 "vin4_data24_b",
4744 "vin4_sync",
4745 "vin4_field",
4746 "vin4_clkenb",
4747 "vin4_clk",
4748};
4749
4750static const char * const vin5_groups[] = {
4751 "vin5_data8",
4752 "vin5_data10",
4753 "vin5_data12",
4754 "vin5_data16",
4755 "vin5_sync",
4756 "vin5_field",
4757 "vin5_clkenb",
4758 "vin5_clk",
4759};
4760
4761static const struct sh_pfc_function pinmux_functions[] = {
4762 SH_PFC_FUNCTION(audio_clk),
4763 SH_PFC_FUNCTION(avb),
4764 SH_PFC_FUNCTION(can0),
4765 SH_PFC_FUNCTION(can1),
4766 SH_PFC_FUNCTION(can_clk),
4767 SH_PFC_FUNCTION(canfd0),
4768 SH_PFC_FUNCTION(canfd1),
4769 SH_PFC_FUNCTION(du),
4770 SH_PFC_FUNCTION(hscif0),
4771 SH_PFC_FUNCTION(hscif1),
4772 SH_PFC_FUNCTION(hscif2),
4773 SH_PFC_FUNCTION(hscif3),
4774 SH_PFC_FUNCTION(hscif4),
4775 SH_PFC_FUNCTION(i2c1),
4776 SH_PFC_FUNCTION(i2c2),
4777 SH_PFC_FUNCTION(i2c6),
4778 SH_PFC_FUNCTION(intc_ex),
4779 SH_PFC_FUNCTION(msiof0),
4780 SH_PFC_FUNCTION(msiof1),
4781 SH_PFC_FUNCTION(msiof2),
4782 SH_PFC_FUNCTION(msiof3),
4783 SH_PFC_FUNCTION(pwm0),
4784 SH_PFC_FUNCTION(pwm1),
4785 SH_PFC_FUNCTION(pwm2),
4786 SH_PFC_FUNCTION(pwm3),
4787 SH_PFC_FUNCTION(pwm4),
4788 SH_PFC_FUNCTION(pwm5),
4789 SH_PFC_FUNCTION(pwm6),
4790 SH_PFC_FUNCTION(sata0),
4791 SH_PFC_FUNCTION(scif0),
4792 SH_PFC_FUNCTION(scif1),
4793 SH_PFC_FUNCTION(scif2),
4794 SH_PFC_FUNCTION(scif3),
4795 SH_PFC_FUNCTION(scif4),
4796 SH_PFC_FUNCTION(scif5),
4797 SH_PFC_FUNCTION(scif_clk),
4798 SH_PFC_FUNCTION(sdhi0),
4799 SH_PFC_FUNCTION(sdhi1),
4800 SH_PFC_FUNCTION(sdhi2),
4801 SH_PFC_FUNCTION(sdhi3),
4802 SH_PFC_FUNCTION(ssi),
4803 SH_PFC_FUNCTION(usb0),
4804 SH_PFC_FUNCTION(usb1),
4805 SH_PFC_FUNCTION(usb30),
4806 SH_PFC_FUNCTION(vin4),
4807 SH_PFC_FUNCTION(vin5),
4808};
4809
4810static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4811#define F_(x, y) FN_##y
4812#define FM(x) FN_##x
4813 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
4814 0, 0,
4815 0, 0,
4816 0, 0,
4817 0, 0,
4818 0, 0,
4819 0, 0,
4820 0, 0,
4821 0, 0,
4822 0, 0,
4823 0, 0,
4824 0, 0,
4825 0, 0,
4826 0, 0,
4827 0, 0,
4828 0, 0,
4829 0, 0,
4830 GP_0_15_FN, GPSR0_15,
4831 GP_0_14_FN, GPSR0_14,
4832 GP_0_13_FN, GPSR0_13,
4833 GP_0_12_FN, GPSR0_12,
4834 GP_0_11_FN, GPSR0_11,
4835 GP_0_10_FN, GPSR0_10,
4836 GP_0_9_FN, GPSR0_9,
4837 GP_0_8_FN, GPSR0_8,
4838 GP_0_7_FN, GPSR0_7,
4839 GP_0_6_FN, GPSR0_6,
4840 GP_0_5_FN, GPSR0_5,
4841 GP_0_4_FN, GPSR0_4,
4842 GP_0_3_FN, GPSR0_3,
4843 GP_0_2_FN, GPSR0_2,
4844 GP_0_1_FN, GPSR0_1,
4845 GP_0_0_FN, GPSR0_0, }
4846 },
4847 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
4848 0, 0,
4849 0, 0,
4850 0, 0,
4851 GP_1_28_FN, GPSR1_28,
4852 GP_1_27_FN, GPSR1_27,
4853 GP_1_26_FN, GPSR1_26,
4854 GP_1_25_FN, GPSR1_25,
4855 GP_1_24_FN, GPSR1_24,
4856 GP_1_23_FN, GPSR1_23,
4857 GP_1_22_FN, GPSR1_22,
4858 GP_1_21_FN, GPSR1_21,
4859 GP_1_20_FN, GPSR1_20,
4860 GP_1_19_FN, GPSR1_19,
4861 GP_1_18_FN, GPSR1_18,
4862 GP_1_17_FN, GPSR1_17,
4863 GP_1_16_FN, GPSR1_16,
4864 GP_1_15_FN, GPSR1_15,
4865 GP_1_14_FN, GPSR1_14,
4866 GP_1_13_FN, GPSR1_13,
4867 GP_1_12_FN, GPSR1_12,
4868 GP_1_11_FN, GPSR1_11,
4869 GP_1_10_FN, GPSR1_10,
4870 GP_1_9_FN, GPSR1_9,
4871 GP_1_8_FN, GPSR1_8,
4872 GP_1_7_FN, GPSR1_7,
4873 GP_1_6_FN, GPSR1_6,
4874 GP_1_5_FN, GPSR1_5,
4875 GP_1_4_FN, GPSR1_4,
4876 GP_1_3_FN, GPSR1_3,
4877 GP_1_2_FN, GPSR1_2,
4878 GP_1_1_FN, GPSR1_1,
4879 GP_1_0_FN, GPSR1_0, }
4880 },
4881 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
4882 0, 0,
4883 0, 0,
4884 0, 0,
4885 0, 0,
4886 0, 0,
4887 0, 0,
4888 0, 0,
4889 0, 0,
4890 0, 0,
4891 0, 0,
4892 0, 0,
4893 0, 0,
4894 0, 0,
4895 0, 0,
4896 0, 0,
4897 0, 0,
4898 0, 0,
4899 GP_2_14_FN, GPSR2_14,
4900 GP_2_13_FN, GPSR2_13,
4901 GP_2_12_FN, GPSR2_12,
4902 GP_2_11_FN, GPSR2_11,
4903 GP_2_10_FN, GPSR2_10,
4904 GP_2_9_FN, GPSR2_9,
4905 GP_2_8_FN, GPSR2_8,
4906 GP_2_7_FN, GPSR2_7,
4907 GP_2_6_FN, GPSR2_6,
4908 GP_2_5_FN, GPSR2_5,
4909 GP_2_4_FN, GPSR2_4,
4910 GP_2_3_FN, GPSR2_3,
4911 GP_2_2_FN, GPSR2_2,
4912 GP_2_1_FN, GPSR2_1,
4913 GP_2_0_FN, GPSR2_0, }
4914 },
4915 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
4916 0, 0,
4917 0, 0,
4918 0, 0,
4919 0, 0,
4920 0, 0,
4921 0, 0,
4922 0, 0,
4923 0, 0,
4924 0, 0,
4925 0, 0,
4926 0, 0,
4927 0, 0,
4928 0, 0,
4929 0, 0,
4930 0, 0,
4931 0, 0,
4932 GP_3_15_FN, GPSR3_15,
4933 GP_3_14_FN, GPSR3_14,
4934 GP_3_13_FN, GPSR3_13,
4935 GP_3_12_FN, GPSR3_12,
4936 GP_3_11_FN, GPSR3_11,
4937 GP_3_10_FN, GPSR3_10,
4938 GP_3_9_FN, GPSR3_9,
4939 GP_3_8_FN, GPSR3_8,
4940 GP_3_7_FN, GPSR3_7,
4941 GP_3_6_FN, GPSR3_6,
4942 GP_3_5_FN, GPSR3_5,
4943 GP_3_4_FN, GPSR3_4,
4944 GP_3_3_FN, GPSR3_3,
4945 GP_3_2_FN, GPSR3_2,
4946 GP_3_1_FN, GPSR3_1,
4947 GP_3_0_FN, GPSR3_0, }
4948 },
4949 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
4950 0, 0,
4951 0, 0,
4952 0, 0,
4953 0, 0,
4954 0, 0,
4955 0, 0,
4956 0, 0,
4957 0, 0,
4958 0, 0,
4959 0, 0,
4960 0, 0,
4961 0, 0,
4962 0, 0,
4963 0, 0,
4964 GP_4_17_FN, GPSR4_17,
4965 GP_4_16_FN, GPSR4_16,
4966 GP_4_15_FN, GPSR4_15,
4967 GP_4_14_FN, GPSR4_14,
4968 GP_4_13_FN, GPSR4_13,
4969 GP_4_12_FN, GPSR4_12,
4970 GP_4_11_FN, GPSR4_11,
4971 GP_4_10_FN, GPSR4_10,
4972 GP_4_9_FN, GPSR4_9,
4973 GP_4_8_FN, GPSR4_8,
4974 GP_4_7_FN, GPSR4_7,
4975 GP_4_6_FN, GPSR4_6,
4976 GP_4_5_FN, GPSR4_5,
4977 GP_4_4_FN, GPSR4_4,
4978 GP_4_3_FN, GPSR4_3,
4979 GP_4_2_FN, GPSR4_2,
4980 GP_4_1_FN, GPSR4_1,
4981 GP_4_0_FN, GPSR4_0, }
4982 },
4983 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
4984 0, 0,
4985 0, 0,
4986 0, 0,
4987 0, 0,
4988 0, 0,
4989 0, 0,
4990 GP_5_25_FN, GPSR5_25,
4991 GP_5_24_FN, GPSR5_24,
4992 GP_5_23_FN, GPSR5_23,
4993 GP_5_22_FN, GPSR5_22,
4994 GP_5_21_FN, GPSR5_21,
4995 GP_5_20_FN, GPSR5_20,
4996 GP_5_19_FN, GPSR5_19,
4997 GP_5_18_FN, GPSR5_18,
4998 GP_5_17_FN, GPSR5_17,
4999 GP_5_16_FN, GPSR5_16,
5000 GP_5_15_FN, GPSR5_15,
5001 GP_5_14_FN, GPSR5_14,
5002 GP_5_13_FN, GPSR5_13,
5003 GP_5_12_FN, GPSR5_12,
5004 GP_5_11_FN, GPSR5_11,
5005 GP_5_10_FN, GPSR5_10,
5006 GP_5_9_FN, GPSR5_9,
5007 GP_5_8_FN, GPSR5_8,
5008 GP_5_7_FN, GPSR5_7,
5009 GP_5_6_FN, GPSR5_6,
5010 GP_5_5_FN, GPSR5_5,
5011 GP_5_4_FN, GPSR5_4,
5012 GP_5_3_FN, GPSR5_3,
5013 GP_5_2_FN, GPSR5_2,
5014 GP_5_1_FN, GPSR5_1,
5015 GP_5_0_FN, GPSR5_0, }
5016 },
5017 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
5018 GP_6_31_FN, GPSR6_31,
5019 GP_6_30_FN, GPSR6_30,
5020 GP_6_29_FN, GPSR6_29,
5021 GP_6_28_FN, GPSR6_28,
5022 GP_6_27_FN, GPSR6_27,
5023 GP_6_26_FN, GPSR6_26,
5024 GP_6_25_FN, GPSR6_25,
5025 GP_6_24_FN, GPSR6_24,
5026 GP_6_23_FN, GPSR6_23,
5027 GP_6_22_FN, GPSR6_22,
5028 GP_6_21_FN, GPSR6_21,
5029 GP_6_20_FN, GPSR6_20,
5030 GP_6_19_FN, GPSR6_19,
5031 GP_6_18_FN, GPSR6_18,
5032 GP_6_17_FN, GPSR6_17,
5033 GP_6_16_FN, GPSR6_16,
5034 GP_6_15_FN, GPSR6_15,
5035 GP_6_14_FN, GPSR6_14,
5036 GP_6_13_FN, GPSR6_13,
5037 GP_6_12_FN, GPSR6_12,
5038 GP_6_11_FN, GPSR6_11,
5039 GP_6_10_FN, GPSR6_10,
5040 GP_6_9_FN, GPSR6_9,
5041 GP_6_8_FN, GPSR6_8,
5042 GP_6_7_FN, GPSR6_7,
5043 GP_6_6_FN, GPSR6_6,
5044 GP_6_5_FN, GPSR6_5,
5045 GP_6_4_FN, GPSR6_4,
5046 GP_6_3_FN, GPSR6_3,
5047 GP_6_2_FN, GPSR6_2,
5048 GP_6_1_FN, GPSR6_1,
5049 GP_6_0_FN, GPSR6_0, }
5050 },
5051 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
5052 0, 0,
5053 0, 0,
5054 0, 0,
5055 0, 0,
5056 0, 0,
5057 0, 0,
5058 0, 0,
5059 0, 0,
5060 0, 0,
5061 0, 0,
5062 0, 0,
5063 0, 0,
5064 0, 0,
5065 0, 0,
5066 0, 0,
5067 0, 0,
5068 0, 0,
5069 0, 0,
5070 0, 0,
5071 0, 0,
5072 0, 0,
5073 0, 0,
5074 0, 0,
5075 0, 0,
5076 0, 0,
5077 0, 0,
5078 0, 0,
5079 0, 0,
5080 GP_7_3_FN, GPSR7_3,
5081 GP_7_2_FN, GPSR7_2,
5082 GP_7_1_FN, GPSR7_1,
5083 GP_7_0_FN, GPSR7_0, }
5084 },
5085#undef F_
5086#undef FM
5087
5088#define F_(x, y) x,
5089#define FM(x) FN_##x,
5090 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
5091 IP0_31_28
5092 IP0_27_24
5093 IP0_23_20
5094 IP0_19_16
5095 IP0_15_12
5096 IP0_11_8
5097 IP0_7_4
5098 IP0_3_0 }
5099 },
5100 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
5101 IP1_31_28
5102 IP1_27_24
5103 IP1_23_20
5104 IP1_19_16
5105 IP1_15_12
5106 IP1_11_8
5107 IP1_7_4
5108 IP1_3_0 }
5109 },
5110 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
5111 IP2_31_28
5112 IP2_27_24
5113 IP2_23_20
5114 IP2_19_16
5115 IP2_15_12
5116 IP2_11_8
5117 IP2_7_4
5118 IP2_3_0 }
5119 },
5120 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
5121 IP3_31_28
5122 IP3_27_24
5123 IP3_23_20
5124 IP3_19_16
5125 IP3_15_12
5126 IP3_11_8
5127 IP3_7_4
5128 IP3_3_0 }
5129 },
5130 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
5131 IP4_31_28
5132 IP4_27_24
5133 IP4_23_20
5134 IP4_19_16
5135 IP4_15_12
5136 IP4_11_8
5137 IP4_7_4
5138 IP4_3_0 }
5139 },
5140 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
5141 IP5_31_28
5142 IP5_27_24
5143 IP5_23_20
5144 IP5_19_16
5145 IP5_15_12
5146 IP5_11_8
5147 IP5_7_4
5148 IP5_3_0 }
5149 },
5150 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
5151 IP6_31_28
5152 IP6_27_24
5153 IP6_23_20
5154 IP6_19_16
5155 IP6_15_12
5156 IP6_11_8
5157 IP6_7_4
5158 IP6_3_0 }
5159 },
5160 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
5161 IP7_31_28
5162 IP7_27_24
5163 IP7_23_20
5164 IP7_19_16
5165 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5166 IP7_11_8
5167 IP7_7_4
5168 IP7_3_0 }
5169 },
5170 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
5171 IP8_31_28
5172 IP8_27_24
5173 IP8_23_20
5174 IP8_19_16
5175 IP8_15_12
5176 IP8_11_8
5177 IP8_7_4
5178 IP8_3_0 }
5179 },
5180 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
5181 IP9_31_28
5182 IP9_27_24
5183 IP9_23_20
5184 IP9_19_16
5185 IP9_15_12
5186 IP9_11_8
5187 IP9_7_4
5188 IP9_3_0 }
5189 },
5190 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
5191 IP10_31_28
5192 IP10_27_24
5193 IP10_23_20
5194 IP10_19_16
5195 IP10_15_12
5196 IP10_11_8
5197 IP10_7_4
5198 IP10_3_0 }
5199 },
5200 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
5201 IP11_31_28
5202 IP11_27_24
5203 IP11_23_20
5204 IP11_19_16
5205 IP11_15_12
5206 IP11_11_8
5207 IP11_7_4
5208 IP11_3_0 }
5209 },
5210 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
5211 IP12_31_28
5212 IP12_27_24
5213 IP12_23_20
5214 IP12_19_16
5215 IP12_15_12
5216 IP12_11_8
5217 IP12_7_4
5218 IP12_3_0 }
5219 },
5220 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5221 IP13_31_28
5222 IP13_27_24
5223 IP13_23_20
5224 IP13_19_16
5225 IP13_15_12
5226 IP13_11_8
5227 IP13_7_4
5228 IP13_3_0 }
5229 },
5230 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5231 IP14_31_28
5232 IP14_27_24
5233 IP14_23_20
5234 IP14_19_16
5235 IP14_15_12
5236 IP14_11_8
5237 IP14_7_4
5238 IP14_3_0 }
5239 },
5240 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5241 IP15_31_28
5242 IP15_27_24
5243 IP15_23_20
5244 IP15_19_16
5245 IP15_15_12
5246 IP15_11_8
5247 IP15_7_4
5248 IP15_3_0 }
5249 },
5250 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5251 IP16_31_28
5252 IP16_27_24
5253 IP16_23_20
5254 IP16_19_16
5255 IP16_15_12
5256 IP16_11_8
5257 IP16_7_4
5258 IP16_3_0 }
5259 },
5260 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
5261 IP17_31_28
5262 IP17_27_24
5263 IP17_23_20
5264 IP17_19_16
5265 IP17_15_12
5266 IP17_11_8
5267 IP17_7_4
5268 IP17_3_0 }
5269 },
5270 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
5271 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5272 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5273 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5274 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5275 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5276 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5277 IP18_7_4
5278 IP18_3_0 }
5279 },
5280#undef F_
5281#undef FM
5282
5283#define F_(x, y) x,
5284#define FM(x) FN_##x,
5285 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5286 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
5287 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
5288 MOD_SEL0_31_30_29
5289 MOD_SEL0_28_27
5290 MOD_SEL0_26_25_24
5291 MOD_SEL0_23
5292 MOD_SEL0_22
5293 MOD_SEL0_21
5294 MOD_SEL0_20
5295 MOD_SEL0_19
5296 MOD_SEL0_18_17
5297 MOD_SEL0_16
5298 0, 0, /* RESERVED 15 */
5299 MOD_SEL0_14_13
5300 MOD_SEL0_12
5301 MOD_SEL0_11
5302 MOD_SEL0_10
5303 MOD_SEL0_9_8
5304 MOD_SEL0_7_6
5305 MOD_SEL0_5
5306 MOD_SEL0_4_3
5307 /* RESERVED 2, 1, 0 */
5308 0, 0, 0, 0, 0, 0, 0, 0 }
5309 },
5310 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5311 2, 3, 1, 2, 3, 1, 1, 2, 1,
5312 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5313 MOD_SEL1_31_30
5314 MOD_SEL1_29_28_27
5315 MOD_SEL1_26
5316 MOD_SEL1_25_24
5317 MOD_SEL1_23_22_21
5318 MOD_SEL1_20
5319 MOD_SEL1_19
5320 MOD_SEL1_18_17
5321 MOD_SEL1_16
5322 MOD_SEL1_15_14
5323 MOD_SEL1_13
5324 MOD_SEL1_12
5325 MOD_SEL1_11
5326 MOD_SEL1_10
5327 MOD_SEL1_9
5328 0, 0, 0, 0, /* RESERVED 8, 7 */
5329 MOD_SEL1_6
5330 MOD_SEL1_5
5331 MOD_SEL1_4
5332 MOD_SEL1_3
5333 MOD_SEL1_2
5334 MOD_SEL1_1
5335 MOD_SEL1_0 }
5336 },
5337 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5338 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
5339 4, 4, 4, 3, 1) {
5340 MOD_SEL2_31
5341 MOD_SEL2_30
5342 MOD_SEL2_29
5343 MOD_SEL2_28_27
5344 MOD_SEL2_26
5345 MOD_SEL2_25_24_23
5346 MOD_SEL2_22
5347 MOD_SEL2_21
5348 MOD_SEL2_20
5349 MOD_SEL2_19
5350 MOD_SEL2_18
5351 MOD_SEL2_17
5352 /* RESERVED 16 */
5353 0, 0,
5354 /* RESERVED 15, 14, 13, 12 */
5355 0, 0, 0, 0, 0, 0, 0, 0,
5356 0, 0, 0, 0, 0, 0, 0, 0,
5357 /* RESERVED 11, 10, 9, 8 */
5358 0, 0, 0, 0, 0, 0, 0, 0,
5359 0, 0, 0, 0, 0, 0, 0, 0,
5360 /* RESERVED 7, 6, 5, 4 */
5361 0, 0, 0, 0, 0, 0, 0, 0,
5362 0, 0, 0, 0, 0, 0, 0, 0,
5363 /* RESERVED 3, 2, 1 */
5364 0, 0, 0, 0, 0, 0, 0, 0,
5365 MOD_SEL2_0 }
5366 },
5367 { },
5368};
5369
5370static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5371 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5372 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
5373 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
5374 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
5375 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
5376 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
5377 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
5378 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
5379 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
5380 } },
5381 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5382 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
5383 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
5384 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
5385 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
5386 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
5387 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
5388 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
5389 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
5390 } },
5391 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5392 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
5393 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
5394 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
5395 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
5396 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
5397 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
5398 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
5399 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
5400 } },
5401 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5402 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
5403 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
5404 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
5405 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
5406 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
5407 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5408 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5409 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5410 } },
5411 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5412 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5413 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5414 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5415 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5416 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5417 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5418 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5419 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5420 } },
5421 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5422 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5423 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5424 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5425 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5426 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5427 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5428 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5429 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5430 } },
5431 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5432 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5433 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5434 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5435 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5436 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5437 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5438 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5439 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5440 } },
5441 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5442 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5443 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5444 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5445 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5446 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5447 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5448 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5449 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5450 } },
5451 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5452 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
5453 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5454 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5455 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5456 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5457 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5458 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5459 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5460 } },
5461 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5462 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5463 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
5464 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5465 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5466 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5467 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5468 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5469 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5470 } },
5471 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5472 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5473 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5474 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5475 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5476 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5477 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5478 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5479 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5480 } },
5481 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5482 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5483 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5484 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5485 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5486 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
5487 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5488 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5489 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
5490 } },
5491 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5492 { PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN3 */
5493 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */
5494 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
5495 } },
5496 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5497 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
5498 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
5499 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5500 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5501 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5502 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5503 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5504 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
5505 } },
5506 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5507 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5508 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5509 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5510 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5511 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5512 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5513 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5514 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5515 } },
5516 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5517 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5518 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5519 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5520 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5521 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5522 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5523 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5524 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5525 } },
5526 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5527 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5528 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5529 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5530 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5531 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5532 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5533 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5534 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5535 } },
5536 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5537 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5538 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5539 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5540 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5541 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5542 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5543 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5544 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5545 } },
5546 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5547 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
5548 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5549 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5550 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
5551 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
5552 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5553 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5554 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5555 } },
5556 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5557 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5558 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5559 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5560 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5561 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5562 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5563 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5564 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5565 } },
5566 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5567 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5568 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5569 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5570 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5571 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5572 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
5573 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
5574 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5575 } },
5576 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5577 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5578 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5579 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5580 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
5581 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5582 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
5583 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5584 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5585 } },
5586 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5587 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5588 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5589 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5590 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5591 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5592 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5593 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5594 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5595 } },
5596 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5597 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5598 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5599 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5600 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5601 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5602 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5603 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5604 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5605 } },
5606 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5607 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5608 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5609 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5610 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5611 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
5612 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
5613 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
5614 } },
5615 { },
5616};
5617
5618enum ioctrl_regs {
5619 POCCTRL,
5620};
5621
5622static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5623 [POCCTRL] = { 0xe6060380, },
5624 { /* sentinel */ },
5625};
5626
5627static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5628{
5629 int bit = -EINVAL;
5630
5631 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5632
5633 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5634 bit = pin & 0x1f;
5635
5636 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5637 bit = (pin & 0x1f) + 12;
5638
5639 return bit;
5640}
5641
5642static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5643 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5644 [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
5645 [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
5646 [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
5647 [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
5648 [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
5649 [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
5650 [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
5651 [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
5652 [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
5653 [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
5654 [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
5655 [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
5656 [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
5657 [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
5658 [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
5659 [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
5660 [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
5661 [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
5662 [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
5663 [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
5664 [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
5665 [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
5666 [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
5667 [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
5668 [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
5669 [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
5670 [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
5671 [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
5672 [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
5673 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
5674 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
5675 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
5676 } },
5677 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5678 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
5679 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
5680 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
5681 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
5682 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
5683 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
5684 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
5685 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
5686 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
5687 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
5688 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
5689 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
5690 [12] = RCAR_GP_PIN(1, 0), /* A0 */
5691 [13] = RCAR_GP_PIN(1, 1), /* A1 */
5692 [14] = RCAR_GP_PIN(1, 2), /* A2 */
5693 [15] = RCAR_GP_PIN(1, 3), /* A3 */
5694 [16] = RCAR_GP_PIN(1, 4), /* A4 */
5695 [17] = RCAR_GP_PIN(1, 5), /* A5 */
5696 [18] = RCAR_GP_PIN(1, 6), /* A6 */
5697 [19] = RCAR_GP_PIN(1, 7), /* A7 */
5698 [20] = RCAR_GP_PIN(1, 8), /* A8 */
5699 [21] = RCAR_GP_PIN(1, 9), /* A9 */
5700 [22] = RCAR_GP_PIN(1, 10), /* A10 */
5701 [23] = RCAR_GP_PIN(1, 11), /* A11 */
5702 [24] = RCAR_GP_PIN(1, 12), /* A12 */
5703 [25] = RCAR_GP_PIN(1, 13), /* A13 */
5704 [26] = RCAR_GP_PIN(1, 14), /* A14 */
5705 [27] = RCAR_GP_PIN(1, 15), /* A15 */
5706 [28] = RCAR_GP_PIN(1, 16), /* A16 */
5707 [29] = RCAR_GP_PIN(1, 17), /* A17 */
5708 [30] = RCAR_GP_PIN(1, 18), /* A18 */
5709 [31] = RCAR_GP_PIN(1, 19), /* A19 */
5710 } },
5711 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5712 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
5713 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
5714 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
5715 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
5716 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
5717 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
5718 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
5719 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
5720 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
5721 [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
5722 [10] = RCAR_GP_PIN(0, 0), /* D0 */
5723 [11] = RCAR_GP_PIN(0, 1), /* D1 */
5724 [12] = RCAR_GP_PIN(0, 2), /* D2 */
5725 [13] = RCAR_GP_PIN(0, 3), /* D3 */
5726 [14] = RCAR_GP_PIN(0, 4), /* D4 */
5727 [15] = RCAR_GP_PIN(0, 5), /* D5 */
5728 [16] = RCAR_GP_PIN(0, 6), /* D6 */
5729 [17] = RCAR_GP_PIN(0, 7), /* D7 */
5730 [18] = RCAR_GP_PIN(0, 8), /* D8 */
5731 [19] = RCAR_GP_PIN(0, 9), /* D9 */
5732 [20] = RCAR_GP_PIN(0, 10), /* D10 */
5733 [21] = RCAR_GP_PIN(0, 11), /* D11 */
5734 [22] = RCAR_GP_PIN(0, 12), /* D12 */
5735 [23] = RCAR_GP_PIN(0, 13), /* D13 */
5736 [24] = RCAR_GP_PIN(0, 14), /* D14 */
5737 [25] = RCAR_GP_PIN(0, 15), /* D15 */
5738 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
5739 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
5740 [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
5741 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
5742 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
5743 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
5744 } },
5745 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5746 [ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN2 */
5747 [ 1] = PIN_NONE,
5748 [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */
5749 [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
5750 [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
5751 [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
5752 [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
5753 [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
5754 [ 8] = PIN_NONE,
5755 [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
5756 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
5757 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
5758 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
5759 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
5760 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
5761 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
5762 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
5763 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
5764 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
5765 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
5766 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
5767 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
5768 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
5769 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
5770 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
5771 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
5772 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
5773 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
5774 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
5775 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
5776 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
5777 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
5778 } },
5779 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5780 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
5781 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
5782 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
5783 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
5784 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
5785 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
5786 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
5787 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
5788 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
5789 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
5790 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
5791 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
5792 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
5793 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
5794 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
5795 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
5796 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
5797 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
5798 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
5799 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
5800 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
5801 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
5802 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
5803 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
5804 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
5805 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
5806 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
5807 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
5808 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
5809 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
5810 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
5811 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
5812 } },
5813 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
5814 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
5815 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
5816 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
5817 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
5818 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
5819 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
5820 [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
5821 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
5822 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
5823 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
5824 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
5825 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
5826 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
5827 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
5828 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
5829 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
5830 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
5831 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
5832 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
5833 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
5834 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
5835 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
5836 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
5837 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
5838 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
5839 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
5840 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
5841 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
5842 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
5843 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
5844 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
5845 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
5846 } },
5847 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
5848 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
5849 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
5850 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
5851 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
5852 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
5853 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
5854 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
5855 [ 7] = PIN_NONE,
5856 [ 8] = PIN_NONE,
5857 [ 9] = PIN_NONE,
5858 [10] = PIN_NONE,
5859 [11] = PIN_NONE,
5860 [12] = PIN_NONE,
5861 [13] = PIN_NONE,
5862 [14] = PIN_NONE,
5863 [15] = PIN_NONE,
5864 [16] = PIN_NONE,
5865 [17] = PIN_NONE,
5866 [18] = PIN_NONE,
5867 [19] = PIN_NONE,
5868 [20] = PIN_NONE,
5869 [21] = PIN_NONE,
5870 [22] = PIN_NONE,
5871 [23] = PIN_NONE,
5872 [24] = PIN_NONE,
5873 [25] = PIN_NONE,
5874 [26] = PIN_NONE,
5875 [27] = PIN_NONE,
5876 [28] = PIN_NONE,
5877 [29] = PIN_NONE,
5878 [30] = PIN_NONE,
5879 [31] = PIN_NONE,
5880 } },
5881 { /* sentinel */ },
5882};
5883
5884static unsigned int r8a77965_pinmux_get_bias(struct sh_pfc *pfc,
5885 unsigned int pin)
5886{
5887 const struct pinmux_bias_reg *reg;
5888 unsigned int bit;
5889
5890 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5891 if (!reg)
5892 return PIN_CONFIG_BIAS_DISABLE;
5893
5894 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
5895 return PIN_CONFIG_BIAS_DISABLE;
5896 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
5897 return PIN_CONFIG_BIAS_PULL_UP;
5898 else
5899 return PIN_CONFIG_BIAS_PULL_DOWN;
5900}
5901
5902static void r8a77965_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5903 unsigned int bias)
5904{
5905 const struct pinmux_bias_reg *reg;
5906 u32 enable, updown;
5907 unsigned int bit;
5908
5909 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5910 if (!reg)
5911 return;
5912
5913 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
5914 if (bias != PIN_CONFIG_BIAS_DISABLE)
5915 enable |= BIT(bit);
5916
5917 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
5918 if (bias == PIN_CONFIG_BIAS_PULL_UP)
5919 updown |= BIT(bit);
5920
5921 sh_pfc_write(pfc, reg->pud, updown);
5922 sh_pfc_write(pfc, reg->puen, enable);
5923}
5924
5925static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = {
5926 .pin_to_pocctrl = r8a77965_pin_to_pocctrl,
5927 .get_bias = r8a77965_pinmux_get_bias,
5928 .set_bias = r8a77965_pinmux_set_bias,
5929};
5930
5931const struct sh_pfc_soc_info r8a77965_pinmux_info = {
5932 .name = "r8a77965_pfc",
5933 .ops = &r8a77965_pinmux_ops,
5934 .unlock_reg = 0xe6060000, /* PMMR */
5935
5936 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5937
5938 .pins = pinmux_pins,
5939 .nr_pins = ARRAY_SIZE(pinmux_pins),
5940 .groups = pinmux_groups,
5941 .nr_groups = ARRAY_SIZE(pinmux_groups),
5942 .functions = pinmux_functions,
5943 .nr_functions = ARRAY_SIZE(pinmux_functions),
5944
5945 .cfg_regs = pinmux_config_regs,
5946 .drive_regs = pinmux_drive_regs,
5947 .bias_regs = pinmux_bias_regs,
5948 .ioctrl_regs = pinmux_ioctrl_regs,
5949
5950 .pinmux_data = pinmux_data,
5951 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5952};