blob: 6f3b2ad653ae7c7c623a48219dbb1259539c614d [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Patrice Chotardb312c592017-09-04 17:56:22 +02002/*
Patrice Chotard3bc599c2017-10-23 09:53:58 +02003 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
Patrice Chotardb312c592017-09-04 17:56:22 +02005 */
6
7#include <common.h>
8#include <clk.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -07009#include <cpu_func.h>
Patrice Chotardb312c592017-09-04 17:56:22 +020010#include <dm.h>
11#include <fdtdec.h>
Simon Glass336d4612020-02-03 07:36:16 -070012#include <malloc.h>
Masahiro Yamadab08c8c42018-03-05 01:20:11 +090013#include <linux/libfdt.h>
Patrice Chotardb312c592017-09-04 17:56:22 +020014#include <mmc.h>
15#include <reset.h>
16#include <asm/io.h>
17#include <asm/gpio.h>
18#include <linux/iopoll.h>
Christophe Kerello48ac7232019-07-30 19:16:45 +020019#include <watchdog.h>
Patrice Chotardb312c592017-09-04 17:56:22 +020020
21struct stm32_sdmmc2_plat {
22 struct mmc_config cfg;
23 struct mmc mmc;
24};
25
26struct stm32_sdmmc2_priv {
27 fdt_addr_t base;
28 struct clk clk;
29 struct reset_ctl reset_ctl;
30 struct gpio_desc cd_gpio;
31 u32 clk_reg_msk;
32 u32 pwr_reg_msk;
33};
34
35struct stm32_sdmmc2_ctx {
36 u32 cache_start;
37 u32 cache_end;
38 u32 data_length;
39 bool dpsm_abort;
40};
41
42/* SDMMC REGISTERS OFFSET */
43#define SDMMC_POWER 0x00 /* SDMMC power control */
44#define SDMMC_CLKCR 0x04 /* SDMMC clock control */
45#define SDMMC_ARG 0x08 /* SDMMC argument */
46#define SDMMC_CMD 0x0C /* SDMMC command */
47#define SDMMC_RESP1 0x14 /* SDMMC response 1 */
48#define SDMMC_RESP2 0x18 /* SDMMC response 2 */
49#define SDMMC_RESP3 0x1C /* SDMMC response 3 */
50#define SDMMC_RESP4 0x20 /* SDMMC response 4 */
51#define SDMMC_DTIMER 0x24 /* SDMMC data timer */
52#define SDMMC_DLEN 0x28 /* SDMMC data length */
53#define SDMMC_DCTRL 0x2C /* SDMMC data control */
54#define SDMMC_DCOUNT 0x30 /* SDMMC data counter */
55#define SDMMC_STA 0x34 /* SDMMC status */
56#define SDMMC_ICR 0x38 /* SDMMC interrupt clear */
57#define SDMMC_MASK 0x3C /* SDMMC mask */
58#define SDMMC_IDMACTRL 0x50 /* SDMMC DMA control */
59#define SDMMC_IDMABASE0 0x58 /* SDMMC DMA buffer 0 base address */
60
61/* SDMMC_POWER register */
Patrick Delaunay7d118162018-06-27 10:15:33 +020062#define SDMMC_POWER_PWRCTRL_MASK GENMASK(1, 0)
63#define SDMMC_POWER_PWRCTRL_OFF 0
64#define SDMMC_POWER_PWRCTRL_CYCLE 2
65#define SDMMC_POWER_PWRCTRL_ON 3
Patrice Chotardb312c592017-09-04 17:56:22 +020066#define SDMMC_POWER_VSWITCH BIT(2)
67#define SDMMC_POWER_VSWITCHEN BIT(3)
68#define SDMMC_POWER_DIRPOL BIT(4)
69
70/* SDMMC_CLKCR register */
71#define SDMMC_CLKCR_CLKDIV GENMASK(9, 0)
72#define SDMMC_CLKCR_CLKDIV_MAX SDMMC_CLKCR_CLKDIV
73#define SDMMC_CLKCR_PWRSAV BIT(12)
74#define SDMMC_CLKCR_WIDBUS_4 BIT(14)
75#define SDMMC_CLKCR_WIDBUS_8 BIT(15)
76#define SDMMC_CLKCR_NEGEDGE BIT(16)
77#define SDMMC_CLKCR_HWFC_EN BIT(17)
78#define SDMMC_CLKCR_DDR BIT(18)
79#define SDMMC_CLKCR_BUSSPEED BIT(19)
Patrick Delaunay167f2c92018-02-07 17:19:59 +010080#define SDMMC_CLKCR_SELCLKRX_MASK GENMASK(21, 20)
81#define SDMMC_CLKCR_SELCLKRX_CK 0
82#define SDMMC_CLKCR_SELCLKRX_CKIN BIT(20)
83#define SDMMC_CLKCR_SELCLKRX_FBCK BIT(21)
Patrice Chotardb312c592017-09-04 17:56:22 +020084
85/* SDMMC_CMD register */
86#define SDMMC_CMD_CMDINDEX GENMASK(5, 0)
87#define SDMMC_CMD_CMDTRANS BIT(6)
88#define SDMMC_CMD_CMDSTOP BIT(7)
89#define SDMMC_CMD_WAITRESP GENMASK(9, 8)
90#define SDMMC_CMD_WAITRESP_0 BIT(8)
91#define SDMMC_CMD_WAITRESP_1 BIT(9)
92#define SDMMC_CMD_WAITINT BIT(10)
93#define SDMMC_CMD_WAITPEND BIT(11)
94#define SDMMC_CMD_CPSMEN BIT(12)
95#define SDMMC_CMD_DTHOLD BIT(13)
96#define SDMMC_CMD_BOOTMODE BIT(14)
97#define SDMMC_CMD_BOOTEN BIT(15)
98#define SDMMC_CMD_CMDSUSPEND BIT(16)
99
100/* SDMMC_DCTRL register */
101#define SDMMC_DCTRL_DTEN BIT(0)
102#define SDMMC_DCTRL_DTDIR BIT(1)
103#define SDMMC_DCTRL_DTMODE GENMASK(3, 2)
104#define SDMMC_DCTRL_DBLOCKSIZE GENMASK(7, 4)
105#define SDMMC_DCTRL_DBLOCKSIZE_SHIFT 4
106#define SDMMC_DCTRL_RWSTART BIT(8)
107#define SDMMC_DCTRL_RWSTOP BIT(9)
108#define SDMMC_DCTRL_RWMOD BIT(10)
109#define SDMMC_DCTRL_SDMMCEN BIT(11)
110#define SDMMC_DCTRL_BOOTACKEN BIT(12)
111#define SDMMC_DCTRL_FIFORST BIT(13)
112
113/* SDMMC_STA register */
114#define SDMMC_STA_CCRCFAIL BIT(0)
115#define SDMMC_STA_DCRCFAIL BIT(1)
116#define SDMMC_STA_CTIMEOUT BIT(2)
117#define SDMMC_STA_DTIMEOUT BIT(3)
118#define SDMMC_STA_TXUNDERR BIT(4)
119#define SDMMC_STA_RXOVERR BIT(5)
120#define SDMMC_STA_CMDREND BIT(6)
121#define SDMMC_STA_CMDSENT BIT(7)
122#define SDMMC_STA_DATAEND BIT(8)
123#define SDMMC_STA_DHOLD BIT(9)
124#define SDMMC_STA_DBCKEND BIT(10)
125#define SDMMC_STA_DABORT BIT(11)
126#define SDMMC_STA_DPSMACT BIT(12)
127#define SDMMC_STA_CPSMACT BIT(13)
128#define SDMMC_STA_TXFIFOHE BIT(14)
129#define SDMMC_STA_RXFIFOHF BIT(15)
130#define SDMMC_STA_TXFIFOF BIT(16)
131#define SDMMC_STA_RXFIFOF BIT(17)
132#define SDMMC_STA_TXFIFOE BIT(18)
133#define SDMMC_STA_RXFIFOE BIT(19)
134#define SDMMC_STA_BUSYD0 BIT(20)
135#define SDMMC_STA_BUSYD0END BIT(21)
136#define SDMMC_STA_SDMMCIT BIT(22)
137#define SDMMC_STA_ACKFAIL BIT(23)
138#define SDMMC_STA_ACKTIMEOUT BIT(24)
139#define SDMMC_STA_VSWEND BIT(25)
140#define SDMMC_STA_CKSTOP BIT(26)
141#define SDMMC_STA_IDMATE BIT(27)
142#define SDMMC_STA_IDMABTC BIT(28)
143
144/* SDMMC_ICR register */
145#define SDMMC_ICR_CCRCFAILC BIT(0)
146#define SDMMC_ICR_DCRCFAILC BIT(1)
147#define SDMMC_ICR_CTIMEOUTC BIT(2)
148#define SDMMC_ICR_DTIMEOUTC BIT(3)
149#define SDMMC_ICR_TXUNDERRC BIT(4)
150#define SDMMC_ICR_RXOVERRC BIT(5)
151#define SDMMC_ICR_CMDRENDC BIT(6)
152#define SDMMC_ICR_CMDSENTC BIT(7)
153#define SDMMC_ICR_DATAENDC BIT(8)
154#define SDMMC_ICR_DHOLDC BIT(9)
155#define SDMMC_ICR_DBCKENDC BIT(10)
156#define SDMMC_ICR_DABORTC BIT(11)
157#define SDMMC_ICR_BUSYD0ENDC BIT(21)
158#define SDMMC_ICR_SDMMCITC BIT(22)
159#define SDMMC_ICR_ACKFAILC BIT(23)
160#define SDMMC_ICR_ACKTIMEOUTC BIT(24)
161#define SDMMC_ICR_VSWENDC BIT(25)
162#define SDMMC_ICR_CKSTOPC BIT(26)
163#define SDMMC_ICR_IDMATEC BIT(27)
164#define SDMMC_ICR_IDMABTCC BIT(28)
165#define SDMMC_ICR_STATIC_FLAGS ((GENMASK(28, 21)) | (GENMASK(11, 0)))
166
167/* SDMMC_MASK register */
168#define SDMMC_MASK_CCRCFAILIE BIT(0)
169#define SDMMC_MASK_DCRCFAILIE BIT(1)
170#define SDMMC_MASK_CTIMEOUTIE BIT(2)
171#define SDMMC_MASK_DTIMEOUTIE BIT(3)
172#define SDMMC_MASK_TXUNDERRIE BIT(4)
173#define SDMMC_MASK_RXOVERRIE BIT(5)
174#define SDMMC_MASK_CMDRENDIE BIT(6)
175#define SDMMC_MASK_CMDSENTIE BIT(7)
176#define SDMMC_MASK_DATAENDIE BIT(8)
177#define SDMMC_MASK_DHOLDIE BIT(9)
178#define SDMMC_MASK_DBCKENDIE BIT(10)
179#define SDMMC_MASK_DABORTIE BIT(11)
180#define SDMMC_MASK_TXFIFOHEIE BIT(14)
181#define SDMMC_MASK_RXFIFOHFIE BIT(15)
182#define SDMMC_MASK_RXFIFOFIE BIT(17)
183#define SDMMC_MASK_TXFIFOEIE BIT(18)
184#define SDMMC_MASK_BUSYD0ENDIE BIT(21)
185#define SDMMC_MASK_SDMMCITIE BIT(22)
186#define SDMMC_MASK_ACKFAILIE BIT(23)
187#define SDMMC_MASK_ACKTIMEOUTIE BIT(24)
188#define SDMMC_MASK_VSWENDIE BIT(25)
189#define SDMMC_MASK_CKSTOPIE BIT(26)
190#define SDMMC_MASK_IDMABTCIE BIT(28)
191
192/* SDMMC_IDMACTRL register */
193#define SDMMC_IDMACTRL_IDMAEN BIT(0)
194
195#define SDMMC_CMD_TIMEOUT 0xFFFFFFFF
Patrice Chotard23441fb2019-07-22 11:41:10 +0200196#define SDMMC_BUSYD0END_TIMEOUT_US 2000000
Patrice Chotardb312c592017-09-04 17:56:22 +0200197
Patrice Chotardb312c592017-09-04 17:56:22 +0200198static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv,
199 struct mmc_data *data,
200 struct stm32_sdmmc2_ctx *ctx)
201{
202 u32 data_ctrl, idmabase0;
203
204 /* Configure the SDMMC DPSM (Data Path State Machine) */
205 data_ctrl = (__ilog2(data->blocksize) <<
206 SDMMC_DCTRL_DBLOCKSIZE_SHIFT) &
207 SDMMC_DCTRL_DBLOCKSIZE;
208
209 if (data->flags & MMC_DATA_READ) {
210 data_ctrl |= SDMMC_DCTRL_DTDIR;
211 idmabase0 = (u32)data->dest;
212 } else {
213 idmabase0 = (u32)data->src;
214 }
215
Patrice Chotardb312c592017-09-04 17:56:22 +0200216 /* Set the SDMMC DataLength value */
217 writel(ctx->data_length, priv->base + SDMMC_DLEN);
218
219 /* Write to SDMMC DCTRL */
220 writel(data_ctrl, priv->base + SDMMC_DCTRL);
221
222 /* Cache align */
223 ctx->cache_start = rounddown(idmabase0, ARCH_DMA_MINALIGN);
224 ctx->cache_end = roundup(idmabase0 + ctx->data_length,
225 ARCH_DMA_MINALIGN);
226
227 /*
228 * Flush data cache before DMA start (clean and invalidate)
229 * Clean also needed for read
230 * Avoid issue on buffer not cached-aligned
231 */
232 flush_dcache_range(ctx->cache_start, ctx->cache_end);
233
234 /* Enable internal DMA */
235 writel(idmabase0, priv->base + SDMMC_IDMABASE0);
236 writel(SDMMC_IDMACTRL_IDMAEN, priv->base + SDMMC_IDMACTRL);
237}
238
239static void stm32_sdmmc2_start_cmd(struct stm32_sdmmc2_priv *priv,
Christophe Kerelloc406a472018-12-06 15:58:10 +0100240 struct mmc_cmd *cmd, u32 cmd_param,
241 struct stm32_sdmmc2_ctx *ctx)
Patrice Chotardb312c592017-09-04 17:56:22 +0200242{
Christophe Kerelloc406a472018-12-06 15:58:10 +0100243 u32 timeout = 0;
244
Patrice Chotard635159a2018-05-17 16:53:57 +0200245 if (readl(priv->base + SDMMC_CMD) & SDMMC_CMD_CPSMEN)
246 writel(0, priv->base + SDMMC_CMD);
Patrice Chotardb312c592017-09-04 17:56:22 +0200247
248 cmd_param |= cmd->cmdidx | SDMMC_CMD_CPSMEN;
249 if (cmd->resp_type & MMC_RSP_PRESENT) {
250 if (cmd->resp_type & MMC_RSP_136)
251 cmd_param |= SDMMC_CMD_WAITRESP;
252 else if (cmd->resp_type & MMC_RSP_CRC)
253 cmd_param |= SDMMC_CMD_WAITRESP_0;
254 else
255 cmd_param |= SDMMC_CMD_WAITRESP_1;
256 }
257
Christophe Kerelloc406a472018-12-06 15:58:10 +0100258 /*
259 * SDMMC_DTIME must be set in two case:
260 * - on data transfert.
261 * - on busy request.
262 * If not done or too short, the dtimeout flag occurs and DPSM stays
263 * enabled/busy and waits for abort (stop transmission cmd).
264 * Next data command is not possible whereas DPSM is activated.
265 */
266 if (ctx->data_length) {
267 timeout = SDMMC_CMD_TIMEOUT;
268 } else {
269 writel(0, priv->base + SDMMC_DCTRL);
270
271 if (cmd->resp_type & MMC_RSP_BUSY)
272 timeout = SDMMC_CMD_TIMEOUT;
273 }
274
275 /* Set the SDMMC Data TimeOut value */
276 writel(timeout, priv->base + SDMMC_DTIMER);
277
Patrice Chotardb312c592017-09-04 17:56:22 +0200278 /* Clear flags */
279 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
280
281 /* Set SDMMC argument value */
282 writel(cmd->cmdarg, priv->base + SDMMC_ARG);
283
284 /* Set SDMMC command parameters */
285 writel(cmd_param, priv->base + SDMMC_CMD);
286}
287
288static int stm32_sdmmc2_end_cmd(struct stm32_sdmmc2_priv *priv,
289 struct mmc_cmd *cmd,
290 struct stm32_sdmmc2_ctx *ctx)
291{
292 u32 mask = SDMMC_STA_CTIMEOUT;
293 u32 status;
294 int ret;
295
296 if (cmd->resp_type & MMC_RSP_PRESENT) {
297 mask |= SDMMC_STA_CMDREND;
298 if (cmd->resp_type & MMC_RSP_CRC)
299 mask |= SDMMC_STA_CCRCFAIL;
300 } else {
301 mask |= SDMMC_STA_CMDSENT;
302 }
303
304 /* Polling status register */
305 ret = readl_poll_timeout(priv->base + SDMMC_STA, status, status & mask,
Christophe Kerello6c36e972017-10-09 17:02:28 +0200306 10000);
Patrice Chotardb312c592017-09-04 17:56:22 +0200307
308 if (ret < 0) {
309 debug("%s: timeout reading SDMMC_STA register\n", __func__);
310 ctx->dpsm_abort = true;
311 return ret;
312 }
313
314 /* Check status */
315 if (status & SDMMC_STA_CTIMEOUT) {
316 debug("%s: error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n",
317 __func__, status, cmd->cmdidx);
318 ctx->dpsm_abort = true;
319 return -ETIMEDOUT;
320 }
321
322 if (status & SDMMC_STA_CCRCFAIL && cmd->resp_type & MMC_RSP_CRC) {
323 debug("%s: error SDMMC_STA_CCRCFAIL (0x%x) for cmd %d\n",
324 __func__, status, cmd->cmdidx);
325 ctx->dpsm_abort = true;
326 return -EILSEQ;
327 }
328
329 if (status & SDMMC_STA_CMDREND && cmd->resp_type & MMC_RSP_PRESENT) {
330 cmd->response[0] = readl(priv->base + SDMMC_RESP1);
331 if (cmd->resp_type & MMC_RSP_136) {
332 cmd->response[1] = readl(priv->base + SDMMC_RESP2);
333 cmd->response[2] = readl(priv->base + SDMMC_RESP3);
334 cmd->response[3] = readl(priv->base + SDMMC_RESP4);
335 }
Christophe Kerelloc406a472018-12-06 15:58:10 +0100336
337 /* Wait for BUSYD0END flag if busy status is detected */
338 if (cmd->resp_type & MMC_RSP_BUSY &&
339 status & SDMMC_STA_BUSYD0) {
340 mask = SDMMC_STA_DTIMEOUT | SDMMC_STA_BUSYD0END;
341
342 /* Polling status register */
343 ret = readl_poll_timeout(priv->base + SDMMC_STA,
344 status, status & mask,
345 SDMMC_BUSYD0END_TIMEOUT_US);
346
347 if (ret < 0) {
348 debug("%s: timeout reading SDMMC_STA\n",
349 __func__);
350 ctx->dpsm_abort = true;
351 return ret;
352 }
353
354 if (status & SDMMC_STA_DTIMEOUT) {
355 debug("%s: error SDMMC_STA_DTIMEOUT (0x%x)\n",
356 __func__, status);
357 ctx->dpsm_abort = true;
358 return -ETIMEDOUT;
359 }
360 }
Patrice Chotardb312c592017-09-04 17:56:22 +0200361 }
362
363 return 0;
364}
365
366static int stm32_sdmmc2_end_data(struct stm32_sdmmc2_priv *priv,
367 struct mmc_cmd *cmd,
368 struct mmc_data *data,
369 struct stm32_sdmmc2_ctx *ctx)
370{
371 u32 mask = SDMMC_STA_DCRCFAIL | SDMMC_STA_DTIMEOUT |
372 SDMMC_STA_IDMATE | SDMMC_STA_DATAEND;
373 u32 status;
374
375 if (data->flags & MMC_DATA_READ)
376 mask |= SDMMC_STA_RXOVERR;
377 else
378 mask |= SDMMC_STA_TXUNDERR;
379
380 status = readl(priv->base + SDMMC_STA);
381 while (!(status & mask))
382 status = readl(priv->base + SDMMC_STA);
383
384 /*
385 * Need invalidate the dcache again to avoid any
386 * cache-refill during the DMA operations (pre-fetching)
387 */
388 if (data->flags & MMC_DATA_READ)
389 invalidate_dcache_range(ctx->cache_start, ctx->cache_end);
390
391 if (status & SDMMC_STA_DCRCFAIL) {
392 debug("%s: error SDMMC_STA_DCRCFAIL (0x%x) for cmd %d\n",
393 __func__, status, cmd->cmdidx);
394 if (readl(priv->base + SDMMC_DCOUNT))
395 ctx->dpsm_abort = true;
396 return -EILSEQ;
397 }
398
399 if (status & SDMMC_STA_DTIMEOUT) {
400 debug("%s: error SDMMC_STA_DTIMEOUT (0x%x) for cmd %d\n",
401 __func__, status, cmd->cmdidx);
402 ctx->dpsm_abort = true;
403 return -ETIMEDOUT;
404 }
405
406 if (status & SDMMC_STA_TXUNDERR) {
407 debug("%s: error SDMMC_STA_TXUNDERR (0x%x) for cmd %d\n",
408 __func__, status, cmd->cmdidx);
409 ctx->dpsm_abort = true;
410 return -EIO;
411 }
412
413 if (status & SDMMC_STA_RXOVERR) {
414 debug("%s: error SDMMC_STA_RXOVERR (0x%x) for cmd %d\n",
415 __func__, status, cmd->cmdidx);
416 ctx->dpsm_abort = true;
417 return -EIO;
418 }
419
420 if (status & SDMMC_STA_IDMATE) {
421 debug("%s: error SDMMC_STA_IDMATE (0x%x) for cmd %d\n",
422 __func__, status, cmd->cmdidx);
423 ctx->dpsm_abort = true;
424 return -EIO;
425 }
426
427 return 0;
428}
429
430static int stm32_sdmmc2_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
431 struct mmc_data *data)
432{
433 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
434 struct stm32_sdmmc2_ctx ctx;
435 u32 cmdat = data ? SDMMC_CMD_CMDTRANS : 0;
436 int ret, retry = 3;
437
Christophe Kerello48ac7232019-07-30 19:16:45 +0200438 WATCHDOG_RESET();
439
Patrice Chotardb312c592017-09-04 17:56:22 +0200440retry_cmd:
441 ctx.data_length = 0;
442 ctx.dpsm_abort = false;
443
444 if (data) {
445 ctx.data_length = data->blocks * data->blocksize;
446 stm32_sdmmc2_start_data(priv, data, &ctx);
447 }
448
Christophe Kerelloc406a472018-12-06 15:58:10 +0100449 stm32_sdmmc2_start_cmd(priv, cmd, cmdat, &ctx);
Patrice Chotardb312c592017-09-04 17:56:22 +0200450
451 debug("%s: send cmd %d data: 0x%x @ 0x%x\n",
452 __func__, cmd->cmdidx,
453 data ? ctx.data_length : 0, (unsigned int)data);
454
455 ret = stm32_sdmmc2_end_cmd(priv, cmd, &ctx);
456
457 if (data && !ret)
458 ret = stm32_sdmmc2_end_data(priv, cmd, data, &ctx);
459
460 /* Clear flags */
461 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
462 if (data)
463 writel(0x0, priv->base + SDMMC_IDMACTRL);
464
465 /*
466 * To stop Data Path State Machine, a stop_transmission command
467 * shall be send on cmd or data errors.
468 */
469 if (ctx.dpsm_abort && (cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) {
470 struct mmc_cmd stop_cmd;
471
472 stop_cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
473 stop_cmd.cmdarg = 0;
474 stop_cmd.resp_type = MMC_RSP_R1b;
475
476 debug("%s: send STOP command to abort dpsm treatments\n",
477 __func__);
478
Christophe Kerelloc406a472018-12-06 15:58:10 +0100479 ctx.data_length = 0;
480
481 stm32_sdmmc2_start_cmd(priv, &stop_cmd,
482 SDMMC_CMD_CMDSTOP, &ctx);
Patrice Chotardb312c592017-09-04 17:56:22 +0200483 stm32_sdmmc2_end_cmd(priv, &stop_cmd, &ctx);
484
485 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
486 }
487
488 if ((ret != -ETIMEDOUT) && (ret != 0) && retry) {
489 printf("%s: cmd %d failed, retrying ...\n",
490 __func__, cmd->cmdidx);
491 retry--;
492 goto retry_cmd;
493 }
494
495 debug("%s: end for CMD %d, ret = %d\n", __func__, cmd->cmdidx, ret);
496
497 return ret;
498}
499
Patrick Delaunay7d118162018-06-27 10:15:33 +0200500/*
501 * Reset the SDMMC with the RCC.SDMMCxRST register bit.
502 * This will reset the SDMMC to the reset state and the CPSM and DPSM
503 * to the Idle state. SDMMC is disabled, Signals Hiz.
504 */
505static void stm32_sdmmc2_reset(struct stm32_sdmmc2_priv *priv)
Patrice Chotardb312c592017-09-04 17:56:22 +0200506{
507 /* Reset */
508 reset_assert(&priv->reset_ctl);
509 udelay(2);
510 reset_deassert(&priv->reset_ctl);
511
Patrick Delaunay7d118162018-06-27 10:15:33 +0200512 /* init the needed SDMMC register after reset */
513 writel(priv->pwr_reg_msk, priv->base + SDMMC_POWER);
514}
Patrice Chotardb312c592017-09-04 17:56:22 +0200515
Patrick Delaunay7d118162018-06-27 10:15:33 +0200516/*
517 * Set the SDMMC in power-cycle state.
518 * This will make that the SDMMC_D[7:0],
519 * SDMMC_CMD and SDMMC_CK are driven low, to prevent the card from being
520 * supplied through the signal lines.
521 */
522static void stm32_sdmmc2_pwrcycle(struct stm32_sdmmc2_priv *priv)
523{
524 if ((readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK) ==
525 SDMMC_POWER_PWRCTRL_CYCLE)
526 return;
527
528 stm32_sdmmc2_reset(priv);
Patrick Delaunay7d118162018-06-27 10:15:33 +0200529}
530
531/*
532 * set the SDMMC state Power-on: the card is clocked
533 * manage the SDMMC state control:
534 * Reset => Power-Cycle => Power-Off => Power
535 * PWRCTRL=10 PWCTRL=00 PWCTRL=11
536 */
537static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_priv *priv)
538{
539 u32 pwrctrl =
540 readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK;
541
542 if (pwrctrl == SDMMC_POWER_PWRCTRL_ON)
543 return;
544
545 /* warning: same PWRCTRL value after reset and for power-off state
546 * it is the reset state here = the only managed by the driver
547 */
548 if (pwrctrl == SDMMC_POWER_PWRCTRL_OFF) {
549 writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
550 priv->base + SDMMC_POWER);
551 }
Patrice Chotardb312c592017-09-04 17:56:22 +0200552
553 /*
Patrick Delaunay7d118162018-06-27 10:15:33 +0200554 * the remaining case is SDMMC_POWER_PWRCTRL_CYCLE
555 * switch to Power-Off state: SDMCC disable, signals drive 1
Patrice Chotardb312c592017-09-04 17:56:22 +0200556 */
Patrick Delaunay7d118162018-06-27 10:15:33 +0200557 writel(SDMMC_POWER_PWRCTRL_OFF | priv->pwr_reg_msk,
558 priv->base + SDMMC_POWER);
559
560 /* After the 1ms delay set the SDMMC to power-on */
561 mdelay(1);
562 writel(SDMMC_POWER_PWRCTRL_ON | priv->pwr_reg_msk,
563 priv->base + SDMMC_POWER);
564
565 /* during the first 74 SDMMC_CK cycles the SDMMC is still disabled. */
Patrice Chotardb312c592017-09-04 17:56:22 +0200566}
567
568#define IS_RISING_EDGE(reg) (reg & SDMMC_CLKCR_NEGEDGE ? 0 : 1)
569static int stm32_sdmmc2_set_ios(struct udevice *dev)
570{
571 struct mmc *mmc = mmc_get_mmc_dev(dev);
572 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
Patrice Chotardb312c592017-09-04 17:56:22 +0200573 u32 desired = mmc->clock;
574 u32 sys_clock = clk_get_rate(&priv->clk);
575 u32 clk = 0;
576
577 debug("%s: bus_with = %d, clock = %d\n", __func__,
578 mmc->bus_width, mmc->clock);
579
Patrick Delaunay7d118162018-06-27 10:15:33 +0200580 if (mmc->clk_disable)
581 stm32_sdmmc2_pwrcycle(priv);
582 else
Patrice Chotardb312c592017-09-04 17:56:22 +0200583 stm32_sdmmc2_pwron(priv);
584
585 /*
586 * clk_div = 0 => command and data generated on SDMMCCLK falling edge
587 * clk_div > 0 and NEGEDGE = 0 => command and data generated on
588 * SDMMCCLK rising edge
589 * clk_div > 0 and NEGEDGE = 1 => command and data generated on
590 * SDMMCCLK falling edge
591 */
592 if (desired && ((sys_clock > desired) ||
593 IS_RISING_EDGE(priv->clk_reg_msk))) {
594 clk = DIV_ROUND_UP(sys_clock, 2 * desired);
595 if (clk > SDMMC_CLKCR_CLKDIV_MAX)
596 clk = SDMMC_CLKCR_CLKDIV_MAX;
597 }
598
599 if (mmc->bus_width == 4)
600 clk |= SDMMC_CLKCR_WIDBUS_4;
601 if (mmc->bus_width == 8)
602 clk |= SDMMC_CLKCR_WIDBUS_8;
603
Patrick Delaunaya72dd8e2018-02-07 17:19:58 +0100604 writel(clk | priv->clk_reg_msk | SDMMC_CLKCR_HWFC_EN,
605 priv->base + SDMMC_CLKCR);
Patrice Chotardb312c592017-09-04 17:56:22 +0200606
607 return 0;
608}
609
610static int stm32_sdmmc2_getcd(struct udevice *dev)
611{
612 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
613
614 debug("stm32_sdmmc2_getcd called\n");
615
616 if (dm_gpio_is_valid(&priv->cd_gpio))
617 return dm_gpio_get_value(&priv->cd_gpio);
618
619 return 1;
620}
621
Yann Gautiera8ef8b22019-09-19 17:56:13 +0200622static int stm32_sdmmc2_host_power_cycle(struct udevice *dev)
623{
624 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
625
626 writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
627 priv->base + SDMMC_POWER);
628
629 return 0;
630}
631
Patrice Chotardb312c592017-09-04 17:56:22 +0200632static const struct dm_mmc_ops stm32_sdmmc2_ops = {
633 .send_cmd = stm32_sdmmc2_send_cmd,
634 .set_ios = stm32_sdmmc2_set_ios,
635 .get_cd = stm32_sdmmc2_getcd,
Yann Gautiera8ef8b22019-09-19 17:56:13 +0200636 .host_power_cycle = stm32_sdmmc2_host_power_cycle,
Patrice Chotardb312c592017-09-04 17:56:22 +0200637};
638
639static int stm32_sdmmc2_probe(struct udevice *dev)
640{
641 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
642 struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
643 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
644 struct mmc_config *cfg = &plat->cfg;
645 int ret;
646
647 priv->base = dev_read_addr(dev);
648 if (priv->base == FDT_ADDR_T_NONE)
649 return -EINVAL;
650
Patrick Delaunayb6115352018-11-16 10:25:54 +0100651 if (dev_read_bool(dev, "st,neg-edge"))
Patrice Chotardb312c592017-09-04 17:56:22 +0200652 priv->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE;
Patrick Delaunayb6115352018-11-16 10:25:54 +0100653 if (dev_read_bool(dev, "st,sig-dir"))
Patrice Chotardb312c592017-09-04 17:56:22 +0200654 priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL;
Patrick Delaunayb6115352018-11-16 10:25:54 +0100655 if (dev_read_bool(dev, "st,use-ckin"))
Patrick Delaunay167f2c92018-02-07 17:19:59 +0100656 priv->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN;
Patrice Chotardb312c592017-09-04 17:56:22 +0200657
658 ret = clk_get_by_index(dev, 0, &priv->clk);
659 if (ret)
660 return ret;
661
662 ret = clk_enable(&priv->clk);
663 if (ret)
664 goto clk_free;
665
666 ret = reset_get_by_index(dev, 0, &priv->reset_ctl);
667 if (ret)
668 goto clk_disable;
669
670 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
671 GPIOD_IS_IN);
672
673 cfg->f_min = 400000;
674 cfg->f_max = dev_read_u32_default(dev, "max-frequency", 52000000);
675 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
676 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
677 cfg->name = "STM32 SDMMC2";
678
679 cfg->host_caps = 0;
680 if (cfg->f_max > 25000000)
681 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
682
683 switch (dev_read_u32_default(dev, "bus-width", 1)) {
684 case 8:
685 cfg->host_caps |= MMC_MODE_8BIT;
Patrick Delaunay0e9fb252019-06-21 15:26:42 +0200686 /* fall through */
Patrice Chotardb312c592017-09-04 17:56:22 +0200687 case 4:
688 cfg->host_caps |= MMC_MODE_4BIT;
689 break;
690 case 1:
691 break;
692 default:
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900693 pr_err("invalid \"bus-width\" property, force to 1\n");
Patrice Chotardb312c592017-09-04 17:56:22 +0200694 }
695
696 upriv->mmc = &plat->mmc;
697
Patrick Delaunay7d118162018-06-27 10:15:33 +0200698 /* SDMMC init */
699 stm32_sdmmc2_reset(priv);
Patrice Chotardb312c592017-09-04 17:56:22 +0200700 return 0;
701
702clk_disable:
703 clk_disable(&priv->clk);
704clk_free:
705 clk_free(&priv->clk);
706
707 return ret;
708}
709
Patrick Delaunay0e9fb252019-06-21 15:26:42 +0200710static int stm32_sdmmc_bind(struct udevice *dev)
Patrice Chotardb312c592017-09-04 17:56:22 +0200711{
712 struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
713
714 return mmc_bind(dev, &plat->mmc, &plat->cfg);
715}
716
717static const struct udevice_id stm32_sdmmc2_ids[] = {
718 { .compatible = "st,stm32-sdmmc2" },
719 { }
720};
721
722U_BOOT_DRIVER(stm32_sdmmc2) = {
723 .name = "stm32_sdmmc2",
724 .id = UCLASS_MMC,
725 .of_match = stm32_sdmmc2_ids,
726 .ops = &stm32_sdmmc2_ops,
727 .probe = stm32_sdmmc2_probe,
728 .bind = stm32_sdmmc_bind,
729 .priv_auto_alloc_size = sizeof(struct stm32_sdmmc2_priv),
730 .platdata_auto_alloc_size = sizeof(struct stm32_sdmmc2_plat),
731};