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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stefano Babicc67bee12010-02-05 15:11:27 +01002/*
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
Stefano Babicc67bee12010-02-05 15:11:27 +01008 */
9
10#include <common.h>
Simon Glassd96c2602019-12-28 10:44:58 -070011#include <clock_legacy.h>
Stefano Babicc67bee12010-02-05 15:11:27 +010012#include <asm/arch/imx-regs.h>
Stefano Babice4d34492010-03-05 17:54:37 +010013#include <asm/arch/clock.h>
Stefano Babicc67bee12010-02-05 15:11:27 +010014
Yangbo Lue37ac712019-06-21 11:42:28 +080015#ifdef CONFIG_FSL_ESDHC_IMX
John Rigby29565322010-12-20 18:27:51 -070016DECLARE_GLOBAL_DATA_PTR;
17#endif
18
Stefano Babicc67bee12010-02-05 15:11:27 +010019int get_clocks(void)
20{
Yangbo Lue37ac712019-06-21 11:42:28 +080021#ifdef CONFIG_FSL_ESDHC_IMX
Michael Langer5c237122012-06-14 03:44:33 +000022#ifdef CONFIG_FSL_USDHC
Benoît Thébaudeau32384652012-09-27 10:24:37 +000023#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
Simon Glasse9adeca2012-12-13 20:49:05 +000024 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
Benoît Thébaudeau32384652012-09-27 10:24:37 +000025#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
Simon Glasse9adeca2012-12-13 20:49:05 +000026 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
Benoît Thébaudeau32384652012-09-27 10:24:37 +000027#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
Simon Glasse9adeca2012-12-13 20:49:05 +000028 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
Michael Langer5c237122012-06-14 03:44:33 +000029#else
Simon Glasse9adeca2012-12-13 20:49:05 +000030 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
Benoît Thébaudeau32384652012-09-27 10:24:37 +000031#endif
32#else
33#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
Simon Glasse9adeca2012-12-13 20:49:05 +000034 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
Benoît Thébaudeau32384652012-09-27 10:24:37 +000035#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
Simon Glasse9adeca2012-12-13 20:49:05 +000036 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
Benoît Thébaudeau32384652012-09-27 10:24:37 +000037#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
Simon Glasse9adeca2012-12-13 20:49:05 +000038 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
Benoît Thébaudeau32384652012-09-27 10:24:37 +000039#else
Simon Glasse9adeca2012-12-13 20:49:05 +000040 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
Benoît Thébaudeau32384652012-09-27 10:24:37 +000041#endif
Stefano Babicc67bee12010-02-05 15:11:27 +010042#endif
Michael Langer5c237122012-06-14 03:44:33 +000043#endif
Stefano Babicc67bee12010-02-05 15:11:27 +010044 return 0;
45}