blob: af342f2c290bba71123306969f10e50bd1a7d15e [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Yoshihiro Shimodaafb35662011-07-04 22:21:22 +00002/*
3 * MMCIF driver.
4 *
5 * Copyright (C) 2011 Renesas Solutions Corp.
Yoshihiro Shimodaafb35662011-07-04 22:21:22 +00006 */
7
8#include <config.h>
9#include <common.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060010#include <log.h>
Yoshihiro Shimodaafb35662011-07-04 22:21:22 +000011#include <watchdog.h>
12#include <command.h>
13#include <mmc.h>
Marek Vasut48f54a22018-04-21 17:27:11 +020014#include <clk.h>
15#include <dm.h>
Yoshihiro Shimodaafb35662011-07-04 22:21:22 +000016#include <malloc.h>
Simon Glass336d4612020-02-03 07:36:16 -070017#include <dm/device_compat.h>
Simon Glasscd93d622020-05-10 11:40:13 -060018#include <linux/bitops.h>
Simon Glassc05ed002020-05-10 11:40:11 -060019#include <linux/delay.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090020#include <linux/errno.h>
Marek Vasut48f54a22018-04-21 17:27:11 +020021#include <linux/compat.h>
22#include <linux/io.h>
23#include <linux/sizes.h>
Yoshihiro Shimodaafb35662011-07-04 22:21:22 +000024#include "sh_mmcif.h"
25
26#define DRIVER_NAME "sh_mmcif"
27
Yoshihiro Shimodaafb35662011-07-04 22:21:22 +000028static int sh_mmcif_intr(void *dev_id)
29{
30 struct sh_mmcif_host *host = dev_id;
31 u32 state = 0;
32
33 state = sh_mmcif_read(&host->regs->ce_int);
34 state &= sh_mmcif_read(&host->regs->ce_int_mask);
35
36 if (state & INT_RBSYE) {
37 sh_mmcif_write(~(INT_RBSYE | INT_CRSPE), &host->regs->ce_int);
38 sh_mmcif_bitclr(MASK_MRBSYE, &host->regs->ce_int_mask);
39 goto end;
40 } else if (state & INT_CRSPE) {
41 sh_mmcif_write(~INT_CRSPE, &host->regs->ce_int);
42 sh_mmcif_bitclr(MASK_MCRSPE, &host->regs->ce_int_mask);
43 /* one more interrupt (INT_RBSYE) */
44 if (sh_mmcif_read(&host->regs->ce_cmd_set) & CMD_SET_RBSY)
45 return -EAGAIN;
46 goto end;
47 } else if (state & INT_BUFREN) {
48 sh_mmcif_write(~INT_BUFREN, &host->regs->ce_int);
49 sh_mmcif_bitclr(MASK_MBUFREN, &host->regs->ce_int_mask);
50 goto end;
51 } else if (state & INT_BUFWEN) {
52 sh_mmcif_write(~INT_BUFWEN, &host->regs->ce_int);
53 sh_mmcif_bitclr(MASK_MBUFWEN, &host->regs->ce_int_mask);
54 goto end;
55 } else if (state & INT_CMD12DRE) {
56 sh_mmcif_write(~(INT_CMD12DRE | INT_CMD12RBE | INT_CMD12CRE |
57 INT_BUFRE), &host->regs->ce_int);
58 sh_mmcif_bitclr(MASK_MCMD12DRE, &host->regs->ce_int_mask);
59 goto end;
60 } else if (state & INT_BUFRE) {
61 sh_mmcif_write(~INT_BUFRE, &host->regs->ce_int);
62 sh_mmcif_bitclr(MASK_MBUFRE, &host->regs->ce_int_mask);
63 goto end;
64 } else if (state & INT_DTRANE) {
65 sh_mmcif_write(~INT_DTRANE, &host->regs->ce_int);
66 sh_mmcif_bitclr(MASK_MDTRANE, &host->regs->ce_int_mask);
67 goto end;
68 } else if (state & INT_CMD12RBE) {
69 sh_mmcif_write(~(INT_CMD12RBE | INT_CMD12CRE),
70 &host->regs->ce_int);
71 sh_mmcif_bitclr(MASK_MCMD12RBE, &host->regs->ce_int_mask);
72 goto end;
73 } else if (state & INT_ERR_STS) {
74 /* err interrupts */
75 sh_mmcif_write(~state, &host->regs->ce_int);
76 sh_mmcif_bitclr(state, &host->regs->ce_int_mask);
77 goto err;
78 } else
79 return -EAGAIN;
80
81err:
82 host->sd_error = 1;
83 debug("%s: int err state = %08x\n", DRIVER_NAME, state);
84end:
85 host->wait_int = 1;
86 return 0;
87}
88
89static int mmcif_wait_interrupt_flag(struct sh_mmcif_host *host)
90{
91 int timeout = 10000000;
92
93 while (1) {
94 timeout--;
95 if (timeout < 0) {
96 printf("timeout\n");
97 return 0;
98 }
99
100 if (!sh_mmcif_intr(host))
101 break;
102
103 udelay(1); /* 1 usec */
104 }
105
106 return 1; /* Return value: NOT 0 = complete waiting */
107}
108
109static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
110{
Yoshihiro Shimodaafb35662011-07-04 22:21:22 +0000111 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl);
112 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl);
113
114 if (!clk)
115 return;
Nobuhiro Iwamatsu21ea3502014-12-03 17:57:00 +0900116
117 if (clk == CLKDEV_EMMC_DATA)
Yoshihiro Shimodaafb35662011-07-04 22:21:22 +0000118 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl);
Nobuhiro Iwamatsu21ea3502014-12-03 17:57:00 +0900119 else
120 sh_mmcif_bitset((fls(DIV_ROUND_UP(host->clk,
121 clk) - 1) - 1) << 16,
122 &host->regs->ce_clk_ctrl);
Yoshihiro Shimodaafb35662011-07-04 22:21:22 +0000123 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl);
124}
125
126static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
127{
128 u32 tmp;
129
130 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE |
131 CLK_CLEAR);
132
133 sh_mmcif_write(SOFT_RST_ON, &host->regs->ce_version);
134 sh_mmcif_write(SOFT_RST_OFF, &host->regs->ce_version);
135 sh_mmcif_bitset(tmp | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29,
136 &host->regs->ce_clk_ctrl);
137 /* byte swap on */
138 sh_mmcif_bitset(BUF_ACC_ATYP, &host->regs->ce_buf_acc);
139}
140
141static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
142{
143 u32 state1, state2;
144 int ret, timeout = 10000000;
145
146 host->sd_error = 0;
147 host->wait_int = 0;
148
149 state1 = sh_mmcif_read(&host->regs->ce_host_sts1);
150 state2 = sh_mmcif_read(&host->regs->ce_host_sts2);
151 debug("%s: ERR HOST_STS1 = %08x\n", \
152 DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts1));
153 debug("%s: ERR HOST_STS2 = %08x\n", \
154 DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts2));
155
156 if (state1 & STS1_CMDSEQ) {
157 debug("%s: Forced end of command sequence\n", DRIVER_NAME);
158 sh_mmcif_bitset(CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);
159 sh_mmcif_bitset(~CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);
160 while (1) {
161 timeout--;
162 if (timeout < 0) {
163 printf(DRIVER_NAME": Forceed end of " \
164 "command sequence timeout err\n");
165 return -EILSEQ;
166 }
167 if (!(sh_mmcif_read(&host->regs->ce_host_sts1)
168 & STS1_CMDSEQ))
169 break;
170 }
171 sh_mmcif_sync_reset(host);
172 return -EILSEQ;
173 }
174
175 if (state2 & STS2_CRC_ERR)
176 ret = -EILSEQ;
177 else if (state2 & STS2_TIMEOUT_ERR)
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900178 ret = -ETIMEDOUT;
Yoshihiro Shimodaafb35662011-07-04 22:21:22 +0000179 else
180 ret = -EILSEQ;
181 return ret;
182}
183
184static int sh_mmcif_single_read(struct sh_mmcif_host *host,
185 struct mmc_data *data)
186{
187 long time;
188 u32 blocksize, i;
189 unsigned long *p = (unsigned long *)data->dest;
190
191 if ((unsigned long)p & 0x00000001) {
192 printf("%s: The data pointer is unaligned.", __func__);
193 return -EIO;
194 }
195
196 host->wait_int = 0;
197
198 /* buf read enable */
199 sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);
200 time = mmcif_wait_interrupt_flag(host);
201 if (time == 0 || host->sd_error != 0)
202 return sh_mmcif_error_manage(host);
203
204 host->wait_int = 0;
205 blocksize = (BLOCK_SIZE_MASK &
206 sh_mmcif_read(&host->regs->ce_block_set)) + 3;
207 for (i = 0; i < blocksize / 4; i++)
208 *p++ = sh_mmcif_read(&host->regs->ce_data);
209
210 /* buffer read end */
211 sh_mmcif_bitset(MASK_MBUFRE, &host->regs->ce_int_mask);
212 time = mmcif_wait_interrupt_flag(host);
213 if (time == 0 || host->sd_error != 0)
214 return sh_mmcif_error_manage(host);
215
216 host->wait_int = 0;
217 return 0;
218}
219
220static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
221 struct mmc_data *data)
222{
223 long time;
224 u32 blocksize, i, j;
225 unsigned long *p = (unsigned long *)data->dest;
226
227 if ((unsigned long)p & 0x00000001) {
228 printf("%s: The data pointer is unaligned.", __func__);
229 return -EIO;
230 }
231
232 host->wait_int = 0;
233 blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);
234 for (j = 0; j < data->blocks; j++) {
235 sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);
236 time = mmcif_wait_interrupt_flag(host);
237 if (time == 0 || host->sd_error != 0)
238 return sh_mmcif_error_manage(host);
239
240 host->wait_int = 0;
241 for (i = 0; i < blocksize / 4; i++)
242 *p++ = sh_mmcif_read(&host->regs->ce_data);
243
244 WATCHDOG_RESET();
245 }
246 return 0;
247}
248
249static int sh_mmcif_single_write(struct sh_mmcif_host *host,
250 struct mmc_data *data)
251{
252 long time;
253 u32 blocksize, i;
254 const unsigned long *p = (unsigned long *)data->dest;
255
256 if ((unsigned long)p & 0x00000001) {
257 printf("%s: The data pointer is unaligned.", __func__);
258 return -EIO;
259 }
260
261 host->wait_int = 0;
262 sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);
263
264 time = mmcif_wait_interrupt_flag(host);
265 if (time == 0 || host->sd_error != 0)
266 return sh_mmcif_error_manage(host);
267
268 host->wait_int = 0;
269 blocksize = (BLOCK_SIZE_MASK &
270 sh_mmcif_read(&host->regs->ce_block_set)) + 3;
271 for (i = 0; i < blocksize / 4; i++)
272 sh_mmcif_write(*p++, &host->regs->ce_data);
273
274 /* buffer write end */
275 sh_mmcif_bitset(MASK_MDTRANE, &host->regs->ce_int_mask);
276
277 time = mmcif_wait_interrupt_flag(host);
278 if (time == 0 || host->sd_error != 0)
279 return sh_mmcif_error_manage(host);
280
281 host->wait_int = 0;
282 return 0;
283}
284
285static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
286 struct mmc_data *data)
287{
288 long time;
289 u32 i, j, blocksize;
290 const unsigned long *p = (unsigned long *)data->dest;
291
292 if ((unsigned long)p & 0x00000001) {
293 printf("%s: The data pointer is unaligned.", __func__);
294 return -EIO;
295 }
296
297 host->wait_int = 0;
298 blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);
299 for (j = 0; j < data->blocks; j++) {
300 sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);
301
302 time = mmcif_wait_interrupt_flag(host);
303
304 if (time == 0 || host->sd_error != 0)
305 return sh_mmcif_error_manage(host);
306
307 host->wait_int = 0;
308 for (i = 0; i < blocksize / 4; i++)
309 sh_mmcif_write(*p++, &host->regs->ce_data);
310
311 WATCHDOG_RESET();
312 }
313 return 0;
314}
315
316static void sh_mmcif_get_response(struct sh_mmcif_host *host,
317 struct mmc_cmd *cmd)
318{
319 if (cmd->resp_type & MMC_RSP_136) {
320 cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp3);
321 cmd->response[1] = sh_mmcif_read(&host->regs->ce_resp2);
322 cmd->response[2] = sh_mmcif_read(&host->regs->ce_resp1);
323 cmd->response[3] = sh_mmcif_read(&host->regs->ce_resp0);
324 debug(" RESP %08x, %08x, %08x, %08x\n", cmd->response[0],
325 cmd->response[1], cmd->response[2], cmd->response[3]);
326 } else {
327 cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp0);
328 }
329}
330
331static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
332 struct mmc_cmd *cmd)
333{
334 cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp_cmd12);
335}
336
337static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
338 struct mmc_data *data, struct mmc_cmd *cmd)
339{
340 u32 tmp = 0;
341 u32 opc = cmd->cmdidx;
342
343 /* Response Type check */
344 switch (cmd->resp_type) {
345 case MMC_RSP_NONE:
346 tmp |= CMD_SET_RTYP_NO;
347 break;
348 case MMC_RSP_R1:
349 case MMC_RSP_R1b:
350 case MMC_RSP_R3:
351 tmp |= CMD_SET_RTYP_6B;
352 break;
353 case MMC_RSP_R2:
354 tmp |= CMD_SET_RTYP_17B;
355 break;
356 default:
357 printf(DRIVER_NAME": Not support type response.\n");
358 break;
359 }
360
361 /* RBSY */
362 if (opc == MMC_CMD_SWITCH)
363 tmp |= CMD_SET_RBSY;
364
365 /* WDAT / DATW */
366 if (host->data) {
367 tmp |= CMD_SET_WDAT;
368 switch (host->bus_width) {
369 case MMC_BUS_WIDTH_1:
370 tmp |= CMD_SET_DATW_1;
371 break;
372 case MMC_BUS_WIDTH_4:
373 tmp |= CMD_SET_DATW_4;
374 break;
375 case MMC_BUS_WIDTH_8:
376 tmp |= CMD_SET_DATW_8;
377 break;
378 default:
379 printf(DRIVER_NAME": Not support bus width.\n");
380 break;
381 }
382 }
383 /* DWEN */
384 if (opc == MMC_CMD_WRITE_SINGLE_BLOCK ||
385 opc == MMC_CMD_WRITE_MULTIPLE_BLOCK)
386 tmp |= CMD_SET_DWEN;
387 /* CMLTE/CMD12EN */
388 if (opc == MMC_CMD_READ_MULTIPLE_BLOCK ||
389 opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) {
390 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
391 sh_mmcif_bitset(data->blocks << 16, &host->regs->ce_block_set);
392 }
393 /* RIDXC[1:0] check bits */
394 if (opc == MMC_CMD_SEND_OP_COND || opc == MMC_CMD_ALL_SEND_CID ||
395 opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID)
396 tmp |= CMD_SET_RIDXC_BITS;
397 /* RCRC7C[1:0] check bits */
398 if (opc == MMC_CMD_SEND_OP_COND)
399 tmp |= CMD_SET_CRC7C_BITS;
400 /* RCRC7C[1:0] internal CRC7 */
401 if (opc == MMC_CMD_ALL_SEND_CID ||
402 opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID)
403 tmp |= CMD_SET_CRC7C_INTERNAL;
404
405 return opc = ((opc << 24) | tmp);
406}
407
408static u32 sh_mmcif_data_trans(struct sh_mmcif_host *host,
409 struct mmc_data *data, u16 opc)
410{
411 u32 ret;
412
413 switch (opc) {
414 case MMC_CMD_READ_MULTIPLE_BLOCK:
415 ret = sh_mmcif_multi_read(host, data);
416 break;
417 case MMC_CMD_WRITE_MULTIPLE_BLOCK:
418 ret = sh_mmcif_multi_write(host, data);
419 break;
420 case MMC_CMD_WRITE_SINGLE_BLOCK:
421 ret = sh_mmcif_single_write(host, data);
422 break;
423 case MMC_CMD_READ_SINGLE_BLOCK:
424 case MMC_CMD_SEND_EXT_CSD:
425 ret = sh_mmcif_single_read(host, data);
426 break;
427 default:
428 printf(DRIVER_NAME": NOT SUPPORT CMD = d'%08d\n", opc);
429 ret = -EINVAL;
430 break;
431 }
432 return ret;
433}
434
435static int sh_mmcif_start_cmd(struct sh_mmcif_host *host,
436 struct mmc_data *data, struct mmc_cmd *cmd)
437{
438 long time;
439 int ret = 0, mask = 0;
440 u32 opc = cmd->cmdidx;
441
442 if (opc == MMC_CMD_STOP_TRANSMISSION) {
443 /* MMCIF sends the STOP command automatically */
444 if (host->last_cmd == MMC_CMD_READ_MULTIPLE_BLOCK)
445 sh_mmcif_bitset(MASK_MCMD12DRE,
446 &host->regs->ce_int_mask);
447 else
448 sh_mmcif_bitset(MASK_MCMD12RBE,
449 &host->regs->ce_int_mask);
450
451 time = mmcif_wait_interrupt_flag(host);
452 if (time == 0 || host->sd_error != 0)
453 return sh_mmcif_error_manage(host);
454
455 sh_mmcif_get_cmd12response(host, cmd);
456 return 0;
457 }
458 if (opc == MMC_CMD_SWITCH)
459 mask = MASK_MRBSYE;
460 else
461 mask = MASK_MCRSPE;
462
463 mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR |
464 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR |
465 MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO |
466 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO;
467
468 if (host->data) {
469 sh_mmcif_write(0, &host->regs->ce_block_set);
470 sh_mmcif_write(data->blocksize, &host->regs->ce_block_set);
471 }
472 opc = sh_mmcif_set_cmd(host, data, cmd);
473
474 sh_mmcif_write(INT_START_MAGIC, &host->regs->ce_int);
475 sh_mmcif_write(mask, &host->regs->ce_int_mask);
476
477 debug("CMD%d ARG:%08x\n", cmd->cmdidx, cmd->cmdarg);
478 /* set arg */
479 sh_mmcif_write(cmd->cmdarg, &host->regs->ce_arg);
480 host->wait_int = 0;
481 /* set cmd */
482 sh_mmcif_write(opc, &host->regs->ce_cmd_set);
483
484 time = mmcif_wait_interrupt_flag(host);
485 if (time == 0)
486 return sh_mmcif_error_manage(host);
487
488 if (host->sd_error) {
489 switch (cmd->cmdidx) {
490 case MMC_CMD_ALL_SEND_CID:
491 case MMC_CMD_SELECT_CARD:
492 case MMC_CMD_APP_CMD:
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900493 ret = -ETIMEDOUT;
Yoshihiro Shimodaafb35662011-07-04 22:21:22 +0000494 break;
495 default:
496 printf(DRIVER_NAME": Cmd(d'%d) err\n", cmd->cmdidx);
497 ret = sh_mmcif_error_manage(host);
498 break;
499 }
500 host->sd_error = 0;
501 host->wait_int = 0;
502 return ret;
503 }
504
505 /* if no response */
506 if (!(opc & 0x00C00000))
507 return 0;
508
509 if (host->wait_int == 1) {
510 sh_mmcif_get_response(host, cmd);
511 host->wait_int = 0;
512 }
513 if (host->data)
514 ret = sh_mmcif_data_trans(host, data, cmd->cmdidx);
515 host->last_cmd = cmd->cmdidx;
516
517 return ret;
518}
519
Marek Vasut48f54a22018-04-21 17:27:11 +0200520static int sh_mmcif_send_cmd_common(struct sh_mmcif_host *host,
521 struct mmc_cmd *cmd, struct mmc_data *data)
Yoshihiro Shimodaafb35662011-07-04 22:21:22 +0000522{
Yoshihiro Shimodaafb35662011-07-04 22:21:22 +0000523 int ret;
524
525 WATCHDOG_RESET();
526
527 switch (cmd->cmdidx) {
528 case MMC_CMD_APP_CMD:
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900529 return -ETIMEDOUT;
Yoshihiro Shimodaafb35662011-07-04 22:21:22 +0000530 case MMC_CMD_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
531 if (data)
532 /* ext_csd */
533 break;
534 else
535 /* send_if_cond cmd (not support) */
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900536 return -ETIMEDOUT;
Yoshihiro Shimodaafb35662011-07-04 22:21:22 +0000537 default:
538 break;
539 }
540 host->sd_error = 0;
541 host->data = data;
542 ret = sh_mmcif_start_cmd(host, data, cmd);
543 host->data = NULL;
544
545 return ret;
546}
547
Marek Vasut48f54a22018-04-21 17:27:11 +0200548static int sh_mmcif_set_ios_common(struct sh_mmcif_host *host, struct mmc *mmc)
Yoshihiro Shimodaafb35662011-07-04 22:21:22 +0000549{
Yoshihiro Shimodaafb35662011-07-04 22:21:22 +0000550 if (mmc->clock)
551 sh_mmcif_clock_control(host, mmc->clock);
552
553 if (mmc->bus_width == 8)
554 host->bus_width = MMC_BUS_WIDTH_8;
555 else if (mmc->bus_width == 4)
556 host->bus_width = MMC_BUS_WIDTH_4;
557 else
558 host->bus_width = MMC_BUS_WIDTH_1;
559
560 debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width);
Jaehoon Chung07b0b9c2016-12-30 15:30:16 +0900561
562 return 0;
Yoshihiro Shimodaafb35662011-07-04 22:21:22 +0000563}
564
Marek Vasut48f54a22018-04-21 17:27:11 +0200565static int sh_mmcif_initialize_common(struct sh_mmcif_host *host)
Yoshihiro Shimodaafb35662011-07-04 22:21:22 +0000566{
Yoshihiro Shimodaafb35662011-07-04 22:21:22 +0000567 sh_mmcif_sync_reset(host);
568 sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask);
569 return 0;
570}
571
Marek Vasut48f54a22018-04-21 17:27:11 +0200572#ifndef CONFIG_DM_MMC
573static void *mmc_priv(struct mmc *mmc)
574{
575 return (void *)mmc->priv;
576}
577
578static int sh_mmcif_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
579 struct mmc_data *data)
580{
581 struct sh_mmcif_host *host = mmc_priv(mmc);
582
583 return sh_mmcif_send_cmd_common(host, cmd, data);
584}
585
586static int sh_mmcif_set_ios(struct mmc *mmc)
587{
588 struct sh_mmcif_host *host = mmc_priv(mmc);
589
590 return sh_mmcif_set_ios_common(host, mmc);
591}
592
593static int sh_mmcif_initialize(struct mmc *mmc)
594{
595 struct sh_mmcif_host *host = mmc_priv(mmc);
596
597 return sh_mmcif_initialize_common(host);
598}
599
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200600static const struct mmc_ops sh_mmcif_ops = {
Marek Vasut48f54a22018-04-21 17:27:11 +0200601 .send_cmd = sh_mmcif_send_cmd,
602 .set_ios = sh_mmcif_set_ios,
603 .init = sh_mmcif_initialize,
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200604};
605
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200606static struct mmc_config sh_mmcif_cfg = {
607 .name = DRIVER_NAME,
608 .ops = &sh_mmcif_ops,
609 .host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT |
Rob Herring5a203972015-03-23 17:56:59 -0500610 MMC_MODE_8BIT,
Nobuhiro Iwamatsucd2bf482014-03-31 14:54:28 +0900611 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200612 .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
613};
614
Yoshihiro Shimodaafb35662011-07-04 22:21:22 +0000615int mmcif_mmc_init(void)
616{
Yoshihiro Shimodaafb35662011-07-04 22:21:22 +0000617 struct mmc *mmc;
618 struct sh_mmcif_host *host = NULL;
619
Yoshihiro Shimodaafb35662011-07-04 22:21:22 +0000620 host = malloc(sizeof(struct sh_mmcif_host));
621 if (!host)
Nobuhiro Iwamatsu74c32ef2014-03-31 14:54:29 +0900622 return -ENOMEM;
Yoshihiro Shimodaafb35662011-07-04 22:21:22 +0000623 memset(host, 0, sizeof(*host));
624
Yoshihiro Shimodaafb35662011-07-04 22:21:22 +0000625 host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR;
626 host->clk = CONFIG_SH_MMCIF_CLK;
Yoshihiro Shimodaafb35662011-07-04 22:21:22 +0000627
Nobuhiro Iwamatsu7a7eb982014-12-03 17:57:01 +0900628 sh_mmcif_cfg.f_min = MMC_CLK_DIV_MIN(host->clk);
Nobuhiro Iwamatsu9675f612014-12-03 17:57:48 +0900629 sh_mmcif_cfg.f_max = MMC_CLK_DIV_MAX(host->clk);
Nobuhiro Iwamatsu7a7eb982014-12-03 17:57:01 +0900630
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200631 mmc = mmc_create(&sh_mmcif_cfg, host);
632 if (mmc == NULL) {
633 free(host);
634 return -ENOMEM;
635 }
Yoshihiro Shimodaafb35662011-07-04 22:21:22 +0000636
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200637 return 0;
Yoshihiro Shimodaafb35662011-07-04 22:21:22 +0000638}
Marek Vasut48f54a22018-04-21 17:27:11 +0200639
640#else
641struct sh_mmcif_plat {
642 struct mmc_config cfg;
643 struct mmc mmc;
644};
645
646int sh_mmcif_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
647 struct mmc_data *data)
648{
649 struct sh_mmcif_host *host = dev_get_priv(dev);
650
651 return sh_mmcif_send_cmd_common(host, cmd, data);
652}
653
654int sh_mmcif_dm_set_ios(struct udevice *dev)
655{
656 struct sh_mmcif_host *host = dev_get_priv(dev);
657 struct mmc *mmc = mmc_get_mmc_dev(dev);
658
659 return sh_mmcif_set_ios_common(host, mmc);
660}
661
662static const struct dm_mmc_ops sh_mmcif_dm_ops = {
663 .send_cmd = sh_mmcif_dm_send_cmd,
664 .set_ios = sh_mmcif_dm_set_ios,
665};
666
667static int sh_mmcif_dm_bind(struct udevice *dev)
668{
Simon Glassc69cda22020-12-03 16:55:20 -0700669 struct sh_mmcif_plat *plat = dev_get_plat(dev);
Marek Vasut48f54a22018-04-21 17:27:11 +0200670
671 return mmc_bind(dev, &plat->mmc, &plat->cfg);
672}
673
674static int sh_mmcif_dm_probe(struct udevice *dev)
675{
Simon Glassc69cda22020-12-03 16:55:20 -0700676 struct sh_mmcif_plat *plat = dev_get_plat(dev);
Marek Vasut48f54a22018-04-21 17:27:11 +0200677 struct sh_mmcif_host *host = dev_get_priv(dev);
678 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
679 struct clk sh_mmcif_clk;
680 fdt_addr_t base;
681 int ret;
682
Masahiro Yamada25484932020-07-17 14:36:48 +0900683 base = dev_read_addr(dev);
Marek Vasut48f54a22018-04-21 17:27:11 +0200684 if (base == FDT_ADDR_T_NONE)
685 return -EINVAL;
686
687 host->regs = (struct sh_mmcif_regs *)devm_ioremap(dev, base, SZ_2K);
688 if (!host->regs)
689 return -ENOMEM;
690
691 ret = clk_get_by_index(dev, 0, &sh_mmcif_clk);
692 if (ret) {
693 debug("failed to get clock, ret=%d\n", ret);
694 return ret;
695 }
696
697 ret = clk_enable(&sh_mmcif_clk);
698 if (ret) {
699 debug("failed to enable clock, ret=%d\n", ret);
700 return ret;
701 }
702
Marek Vasutf4eaa562019-03-18 06:04:17 +0100703 host->clk = clk_set_rate(&sh_mmcif_clk, 97500000);
Marek Vasut48f54a22018-04-21 17:27:11 +0200704
705 plat->cfg.name = dev->name;
706 plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
707
708 switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
709 1)) {
710 case 8:
711 plat->cfg.host_caps |= MMC_MODE_8BIT;
712 break;
713 case 4:
714 plat->cfg.host_caps |= MMC_MODE_4BIT;
715 break;
716 case 1:
717 break;
718 default:
719 dev_err(dev, "Invalid \"bus-width\" value\n");
720 return -EINVAL;
721 }
722
723 sh_mmcif_initialize_common(host);
724
725 plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
726 plat->cfg.f_min = MMC_CLK_DIV_MIN(host->clk);
727 plat->cfg.f_max = MMC_CLK_DIV_MAX(host->clk);
728 plat->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
729
730 upriv->mmc = &plat->mmc;
731
732 return 0;
733}
734
735static const struct udevice_id sh_mmcif_sd_match[] = {
736 { .compatible = "renesas,sh-mmcif" },
737 { /* sentinel */ }
738};
739
740U_BOOT_DRIVER(sh_mmcif_mmc) = {
741 .name = "sh-mmcif",
742 .id = UCLASS_MMC,
743 .of_match = sh_mmcif_sd_match,
744 .bind = sh_mmcif_dm_bind,
745 .probe = sh_mmcif_dm_probe,
Simon Glass41575d82020-12-03 16:55:17 -0700746 .priv_auto = sizeof(struct sh_mmcif_host),
Simon Glasscaa4daa2020-12-03 16:55:18 -0700747 .plat_auto = sizeof(struct sh_mmcif_plat),
Marek Vasut48f54a22018-04-21 17:27:11 +0200748 .ops = &sh_mmcif_dm_ops,
749};
750#endif