Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Stelian Pop | 8e429b3 | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2007-2008 |
Stelian Pop | c9e798d | 2011-11-01 00:00:39 +0100 | [diff] [blame] | 4 | * Stelian Pop <stelian@popies.net> |
Stelian Pop | 8e429b3 | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 5 | * Lead Tech Design <www.leadtechdesign.com> |
| 6 | * |
| 7 | * Configuation settings for the AT91SAM9263EK board. |
Stelian Pop | 8e429b3 | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef __CONFIG_H |
| 11 | #define __CONFIG_H |
| 12 | |
Simon Glass | 1af3c7f | 2020-05-10 11:40:09 -0600 | [diff] [blame] | 13 | #include <linux/stringify.h> |
| 14 | |
Xu, Hong | cd46b0f | 2011-06-10 21:31:26 +0000 | [diff] [blame] | 15 | /* |
| 16 | * SoC must be defined first, before hardware.h is included. |
| 17 | * In this case SoC is defined in boards.cfg. |
| 18 | */ |
| 19 | #include <asm/hardware.h> |
Stelian Pop | 8e429b3 | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 20 | |
Xu, Hong | cd46b0f | 2011-06-10 21:31:26 +0000 | [diff] [blame] | 21 | /* ARM asynchronous clock */ |
| 22 | #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ |
| 23 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 |
Xu, Hong | cd46b0f | 2011-06-10 21:31:26 +0000 | [diff] [blame] | 24 | |
Stelian Pop | 8e429b3 | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 25 | /* SDRAM */ |
Xu, Hong | cd46b0f | 2011-06-10 21:31:26 +0000 | [diff] [blame] | 26 | #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 |
| 27 | #define CONFIG_SYS_SDRAM_SIZE 0x04000000 |
| 28 | |
Tom Rini | eaf6ea6 | 2022-05-25 12:16:03 -0400 | [diff] [blame] | 29 | #define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) |
| 30 | #define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 |
Stelian Pop | 8e429b3 | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 31 | |
Stelian Pop | 8e429b3 | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 32 | /* NOR flash, if populated */ |
Jean-Christophe PLAGNIOL-VILLARD | 1b3b7c6 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 33 | #ifdef CONFIG_SYS_USE_NORFLASH |
Jean-Christophe PLAGNIOL-VILLARD | 1b3b7c6 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 34 | #define PHYS_FLASH_1 0x10000000 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 35 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
Jean-Christophe PLAGNIOL-VILLARD | 1b3b7c6 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 36 | |
| 37 | #define CONFIG_SYS_MONITOR_SEC 1:0-3 |
Jean-Christophe PLAGNIOL-VILLARD | 1b3b7c6 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 38 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) |
Jean-Christophe PLAGNIOL-VILLARD | 1b3b7c6 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 39 | |
| 40 | /* Address and size of Primary Environment Sector */ |
Jean-Christophe PLAGNIOL-VILLARD | 1b3b7c6 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 41 | |
Jean-Christophe PLAGNIOL-VILLARD | 1b3b7c6 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 42 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Marek Vasut | 93ea89f | 2012-09-23 17:41:23 +0200 | [diff] [blame] | 43 | "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ |
Jean-Christophe PLAGNIOL-VILLARD | 1b3b7c6 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 44 | "update=" \ |
| 45 | "protect off ${monitor_base} +${filesize};" \ |
| 46 | "erase ${monitor_base} +${filesize};" \ |
Andreas Bießmann | 88461f1 | 2012-06-28 02:32:32 +0000 | [diff] [blame] | 47 | "cp.b ${fileaddr} ${monitor_base} ${filesize};" \ |
Jean-Christophe PLAGNIOL-VILLARD | 1b3b7c6 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 48 | "protect on ${monitor_base} +${filesize}\0" |
| 49 | |
| 50 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
| 51 | #define MASTER_PLL_MUL 171 |
| 52 | #define MASTER_PLL_DIV 14 |
Jens Scharsig | 1b34f00 | 2010-02-03 22:47:18 +0100 | [diff] [blame] | 53 | #define MASTER_PLL_OUT 3 |
Jean-Christophe PLAGNIOL-VILLARD | 1b3b7c6 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 54 | |
| 55 | /* clocks */ |
| 56 | #define CONFIG_SYS_MOR_VAL \ |
Jens Scharsig | 1b34f00 | 2010-02-03 22:47:18 +0100 | [diff] [blame] | 57 | (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) |
| 58 | #define CONFIG_SYS_PLLAR_VAL \ |
| 59 | (AT91_PMC_PLLAR_29 | \ |
| 60 | AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ |
| 61 | AT91_PMC_PLLXR_PLLCOUNT(63) | \ |
Wolfgang Denk | 0cf207e | 2021-09-27 17:42:39 +0200 | [diff] [blame] | 62 | AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ |
Jens Scharsig | 1b34f00 | 2010-02-03 22:47:18 +0100 | [diff] [blame] | 63 | AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) |
Jean-Christophe PLAGNIOL-VILLARD | 1b3b7c6 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 64 | |
| 65 | /* PCK/2 = MCK Master Clock from PLLA */ |
| 66 | #define CONFIG_SYS_MCKR1_VAL \ |
Jens Scharsig | 1b34f00 | 2010-02-03 22:47:18 +0100 | [diff] [blame] | 67 | (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ |
| 68 | AT91_PMC_MCKR_MDIV_2) |
| 69 | |
Jean-Christophe PLAGNIOL-VILLARD | 1b3b7c6 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 70 | /* PCK/2 = MCK Master Clock from PLLA */ |
| 71 | #define CONFIG_SYS_MCKR2_VAL \ |
Wolfgang Denk | 0cf207e | 2021-09-27 17:42:39 +0200 | [diff] [blame] | 72 | (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ |
Jens Scharsig | 1b34f00 | 2010-02-03 22:47:18 +0100 | [diff] [blame] | 73 | AT91_PMC_MCKR_MDIV_2) |
Jean-Christophe PLAGNIOL-VILLARD | 1b3b7c6 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 74 | |
| 75 | /* define PDC[31:16] as DATA[31:16] */ |
| 76 | #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 |
| 77 | /* no pull-up for D[31:16] */ |
| 78 | #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 |
| 79 | /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ |
Jens Scharsig | 1b34f00 | 2010-02-03 22:47:18 +0100 | [diff] [blame] | 80 | #define CONFIG_SYS_MATRIX_EBICSA_VAL \ |
| 81 | (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ |
| 82 | AT91_MATRIX_CSA_EBI_CS1A) |
Jean-Christophe PLAGNIOL-VILLARD | 1b3b7c6 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 83 | |
| 84 | /* SDRAM */ |
| 85 | /* SDRAMC_MR Mode register */ |
| 86 | #define CONFIG_SYS_SDRC_MR_VAL1 0 |
| 87 | /* SDRAMC_TR - Refresh Timer register */ |
| 88 | #define CONFIG_SYS_SDRC_TR_VAL1 0x13C |
| 89 | /* SDRAMC_CR - Configuration register*/ |
| 90 | #define CONFIG_SYS_SDRC_CR_VAL \ |
| 91 | (AT91_SDRAMC_NC_9 | \ |
| 92 | AT91_SDRAMC_NR_13 | \ |
| 93 | AT91_SDRAMC_NB_4 | \ |
| 94 | AT91_SDRAMC_CAS_3 | \ |
| 95 | AT91_SDRAMC_DBW_32 | \ |
| 96 | (1 << 8) | /* Write Recovery Delay */ \ |
| 97 | (7 << 12) | /* Row Cycle Delay */ \ |
| 98 | (2 << 16) | /* Row Precharge Delay */ \ |
| 99 | (2 << 20) | /* Row to Column Delay */ \ |
| 100 | (5 << 24) | /* Active to Precharge Delay */ \ |
| 101 | (1 << 28)) /* Exit Self Refresh to Active Delay */ |
| 102 | |
| 103 | /* Memory Device Register -> SDRAM */ |
| 104 | #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM |
| 105 | #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE |
| 106 | #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ |
| 107 | #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH |
| 108 | #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ |
| 109 | #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ |
| 110 | #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ |
| 111 | #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ |
| 112 | #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ |
| 113 | #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ |
| 114 | #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ |
| 115 | #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ |
| 116 | #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR |
| 117 | #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ |
| 118 | #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL |
| 119 | #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ |
| 120 | #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ |
| 121 | #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ |
| 122 | |
| 123 | /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ |
Jens Scharsig | 1b34f00 | 2010-02-03 22:47:18 +0100 | [diff] [blame] | 124 | #define CONFIG_SYS_SMC0_SETUP0_VAL \ |
| 125 | (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ |
| 126 | AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) |
| 127 | #define CONFIG_SYS_SMC0_PULSE0_VAL \ |
| 128 | (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ |
| 129 | AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) |
Jean-Christophe PLAGNIOL-VILLARD | 1b3b7c6 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 130 | #define CONFIG_SYS_SMC0_CYCLE0_VAL \ |
Jens Scharsig | 1b34f00 | 2010-02-03 22:47:18 +0100 | [diff] [blame] | 131 | (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) |
Jean-Christophe PLAGNIOL-VILLARD | 1b3b7c6 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 132 | #define CONFIG_SYS_SMC0_MODE0_VAL \ |
Jens Scharsig | 1b34f00 | 2010-02-03 22:47:18 +0100 | [diff] [blame] | 133 | (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ |
| 134 | AT91_SMC_MODE_DBW_16 | \ |
| 135 | AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) |
Jean-Christophe PLAGNIOL-VILLARD | 1b3b7c6 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 136 | |
| 137 | /* user reset enable */ |
| 138 | #define CONFIG_SYS_RSTC_RMR_VAL \ |
| 139 | (AT91_RSTC_KEY | \ |
Jens Scharsig | 1b34f00 | 2010-02-03 22:47:18 +0100 | [diff] [blame] | 140 | AT91_RSTC_MR_URSTEN | \ |
| 141 | AT91_RSTC_MR_ERSTL(15)) |
Jean-Christophe PLAGNIOL-VILLARD | 1b3b7c6 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 142 | |
| 143 | /* Disable Watchdog */ |
| 144 | #define CONFIG_SYS_WDTC_WDMR_VAL \ |
Jens Scharsig | 1b34f00 | 2010-02-03 22:47:18 +0100 | [diff] [blame] | 145 | (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ |
| 146 | AT91_WDT_MR_WDV(0xfff) | \ |
| 147 | AT91_WDT_MR_WDDIS | \ |
| 148 | AT91_WDT_MR_WDD(0xfff)) |
| 149 | |
Jean-Christophe PLAGNIOL-VILLARD | 1b3b7c6 | 2009-06-13 12:48:36 +0200 | [diff] [blame] | 150 | #endif |
Simon Glass | 1af3c7f | 2020-05-10 11:40:09 -0600 | [diff] [blame] | 151 | #include <linux/stringify.h> |
Stelian Pop | 8e429b3 | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 152 | #endif |
| 153 | |
| 154 | /* NAND flash */ |
Jean-Christophe PLAGNIOL-VILLARD | 74c076d | 2009-03-22 10:22:34 +0100 | [diff] [blame] | 155 | #ifdef CONFIG_CMD_NAND |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 156 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
Xu, Hong | cd46b0f | 2011-06-10 21:31:26 +0000 | [diff] [blame] | 157 | #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 158 | #define CONFIG_SYS_NAND_DBW_8 1 |
Jean-Christophe PLAGNIOL-VILLARD | 74c076d | 2009-03-22 10:22:34 +0100 | [diff] [blame] | 159 | /* our ALE is AD21 */ |
| 160 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) |
| 161 | /* our CLE is AD22 */ |
| 162 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) |
Xu, Hong | cd46b0f | 2011-06-10 21:31:26 +0000 | [diff] [blame] | 163 | #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 |
| 164 | #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 |
Jean-Christophe PLAGNIOL-VILLARD | 74c076d | 2009-03-22 10:22:34 +0100 | [diff] [blame] | 165 | #endif |
Stelian Pop | 8e429b3 | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 166 | |
Stelian Pop | 8e429b3 | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 167 | /* USB */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 168 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ |
Stelian Pop | 8e429b3 | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 169 | |
Stelian Pop | 8e429b3 | 2008-05-08 18:52:23 +0200 | [diff] [blame] | 170 | #endif |