| wdenk | 6876609 | 2004-01-29 09:22:58 +0000 | [diff] [blame] | 1 | The current implementation allows the user to specify the desired CPU |
| 2 | clock value, in MHz, via an environment variable "cpuclk". |
| 3 | |
| wdenk | 66ca92a | 2004-09-28 17:59:53 +0000 | [diff] [blame] | 4 | Four compile-time constants are used: |
| wdenk | 6876609 | 2004-01-29 09:22:58 +0000 | [diff] [blame] | 5 | |
| wdenk | 66ca92a | 2004-09-28 17:59:53 +0000 | [diff] [blame] | 6 | CONFIG_8xx_OSCLK - input quartz clock |
| 7 | CFG_8xx_CPUCLK_MIN - minimum allowed CPU clock |
| 8 | CFG_8xx_CPUCLK_MAX - maximum allowed CPU clock |
| 9 | CONFIG_8xx_CPUCLK_DEFAULT - default CPU clock value |
| wdenk | 6876609 | 2004-01-29 09:22:58 +0000 | [diff] [blame] | 10 | |
| 11 | If the "cpuclk" environment variable value is within the CPUCLK_MIN / |
| 12 | CPUCLK_MAX limits, the specified value is used. Otherwise, the |
| 13 | default CPU clock value is set. |
| 14 | |
| wdenk | 75d1ea7 | 2004-01-31 20:06:54 +0000 | [diff] [blame] | 15 | Please make sure you understand what you are doing, and understand |
| 16 | the restrictions of your hardware (board, processor). For example, |
| 17 | ethernet will stop working for CPU clock frequencies below 25 MHz. |
| 18 | |
| wdenk | 66ca92a | 2004-09-28 17:59:53 +0000 | [diff] [blame] | 19 | Please note that the new clock-handling code is enabled if |
| 20 | CONFIG_8xx_CPUCLK_DEFAULT is defined. Since this mechanism supports |
| 21 | only MPC866 and newer CPUs, this constant MUST NOT be defined for |
| 22 | MPC823/850/860/862 series. The clock generation algorithm for older |
| 23 | chips is different and has not been implemented yet. If you need it, |
| 24 | your patch is welcome. |