blob: c595f70e939931359f08d7b8f0184c054baeab8d [file] [log] [blame]
Jimmy Zhang6860b4a2012-04-02 13:18:53 +00001/*
2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Jimmy Zhang6860b4a2012-04-02 13:18:53 +00006 */
7
8#include <common.h>
9#include <tps6586x.h>
10#include <asm/io.h>
Tom Warren150c2492012-09-19 15:50:56 -070011#include <asm/arch/tegra.h>
12#include <asm/arch-tegra/ap.h>
13#include <asm/arch-tegra/tegra_i2c.h>
14#include <asm/arch-tegra/sys_proto.h>
Jimmy Zhang6860b4a2012-04-02 13:18:53 +000015
16#define VDD_CORE_NOMINAL_T25 0x17 /* 1.3v */
17#define VDD_CPU_NOMINAL_T25 0x10 /* 1.125v */
18
19#define VDD_CORE_NOMINAL_T20 0x16 /* 1.275v */
20#define VDD_CPU_NOMINAL_T20 0x0f /* 1.1v */
21
22#define VDD_RELATION 0x02 /* 50mv */
23#define VDD_TRANSITION_STEP 0x06 /* 150mv */
24#define VDD_TRANSITION_RATE 0x06 /* 3.52mv/us */
25
26int pmu_set_nominal(void)
27{
28 int core, cpu, bus;
29
30 /* by default, the table has been filled with T25 settings */
Tom Warren49493cb2013-04-10 10:32:32 -070031 switch (tegra_get_chip_sku()) {
Jimmy Zhang6860b4a2012-04-02 13:18:53 +000032 case TEGRA_SOC_T20:
33 core = VDD_CORE_NOMINAL_T20;
34 cpu = VDD_CPU_NOMINAL_T20;
35 break;
36 case TEGRA_SOC_T25:
37 core = VDD_CORE_NOMINAL_T25;
38 cpu = VDD_CPU_NOMINAL_T25;
39 break;
40 default:
Tom Warren49493cb2013-04-10 10:32:32 -070041 debug("%s: Unknown SKU id\n", __func__);
Jimmy Zhang6860b4a2012-04-02 13:18:53 +000042 return -1;
43 }
44
45 bus = tegra_i2c_get_dvc_bus_num();
46 if (bus == -1) {
47 debug("%s: Cannot find DVC I2C bus\n", __func__);
48 return -1;
49 }
50 tps6586x_init(bus);
51 tps6586x_set_pwm_mode(TPS6586X_PWM_SM1);
52 return tps6586x_adjust_sm0_sm1(core, cpu, VDD_TRANSITION_STEP,
53 VDD_TRANSITION_RATE, VDD_RELATION);
54}