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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / c74665155068c3300b7745cd6add4676f604a285 / . / drivers / clk / mediatek / clk-mt7623.c
blob: c6b09d8e18dce994882dc1c69e4a9ff0066a714c [file] [log] [blame]
Ryder Leec7466512018-11-15 10:07:55 +0800[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MediaTek clock driver for MT7623 SoC
4 *
5 * Copyright (C) 2018 MediaTek Inc.
6 * Author: Ryder Lee <ryder.lee@mediatek.com>
7 */
8
9#include <common.h>
10#include <dm.h>
11#include <asm/io.h>
12#include <dt-bindings/clock/mt7623-clk.h>
13
14#include "clk-mtk.h"
15
16#define MT7623_CLKSQ_STB_CON0 0x18
17#define MT7623_PLL_ISO_CON0 0x24
18#define MT7623_PLL_FMAX (2000UL * MHZ)
19#define MT7623_CON0_RST_BAR BIT(27)
20
21#define MCU_AXI_DIV 0x60
22#define AXI_DIV_MSK GENMASK(4, 0)
23#define AXI_DIV_SEL(x) (x)
24
25/* apmixedsys */
26#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
27 _pd_shift, _pcw_reg, _pcw_shift) { \
28 .id = _id, \
29 .reg = _reg, \
30 .pwr_reg = _pwr_reg, \
31 .en_mask = _en_mask, \
32 .rst_bar_mask = MT7623_CON0_RST_BAR, \
33 .fmax = MT7623_PLL_FMAX, \
34 .flags = _flags, \
35 .pcwbits = _pcwbits, \
36 .pd_reg = _pd_reg, \
37 .pd_shift = _pd_shift, \
38 .pcw_reg = _pcw_reg, \
39 .pcw_shift = _pcw_shift, \
40 }
41
42static const struct mtk_pll_data apmixed_plls[] = {
43 PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x80000001, 0,
44 21, 0x204, 24, 0x204, 0),
45 PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0xf0000001, HAVE_RST_BAR,
46 21, 0x210, 4, 0x214, 0),
47 PLL(CLK_APMIXED_UNIVPLL, 0x220, 0x22c, 0xf3000001, HAVE_RST_BAR,
48 7, 0x220, 4, 0x224, 14),
49 PLL(CLK_APMIXED_MMPLL, 0x230, 0x23c, 0x00000001, 0,
50 21, 0x230, 4, 0x234, 0),
51 PLL(CLK_APMIXED_MSDCPLL, 0x240, 0x24c, 0x00000001, 0,
52 21, 0x240, 4, 0x244, 0),
53 PLL(CLK_APMIXED_TVDPLL, 0x250, 0x25c, 0x00000001, 0,
54 21, 0x250, 4, 0x254, 0),
55 PLL(CLK_APMIXED_AUD1PLL, 0x270, 0x27c, 0x00000001, 0,
56 31, 0x270, 4, 0x274, 0),
57 PLL(CLK_APMIXED_TRGPLL, 0x280, 0x28c, 0x00000001, 0,
58 31, 0x280, 4, 0x284, 0),
59 PLL(CLK_APMIXED_ETHPLL, 0x290, 0x29c, 0x00000001, 0,
60 31, 0x290, 4, 0x294, 0),
61 PLL(CLK_APMIXED_VDECPLL, 0x2a0, 0x2ac, 0x00000001, 0,
62 31, 0x2a0, 4, 0x2a4, 0),
63 PLL(CLK_APMIXED_HADDS2PLL, 0x2b0, 0x2bc, 0x00000001, 0,
64 31, 0x2b0, 4, 0x2b4, 0),
65 PLL(CLK_APMIXED_AUD2PLL, 0x2c0, 0x2cc, 0x00000001, 0,
66 31, 0x2c0, 4, 0x2c4, 0),
67 PLL(CLK_APMIXED_TVD2PLL, 0x2d0, 0x2dc, 0x00000001, 0,
68 21, 0x2d0, 4, 0x2d4, 0),
69};
70
71/* topckgen */
72#define FACTOR0(_id, _parent, _mult, _div) \
73 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
74
75#define FACTOR1(_id, _parent, _mult, _div) \
76 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
77
78#define FACTOR2(_id, _parent, _mult, _div) \
79 FACTOR(_id, _parent, _mult, _div, 0)
80
81static const struct mtk_fixed_clk top_fixed_clks[] = {
82 FIXED_CLK(CLK_TOP_DPI, CLK_XTAL, 108 * MHZ),
83 FIXED_CLK(CLK_TOP_DMPLL, CLK_XTAL, 400 * MHZ),
84 FIXED_CLK(CLK_TOP_VENCPLL, CLK_XTAL, 295.75 * MHZ),
85 FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, CLK_XTAL, 340 * MHZ),
86 FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, CLK_XTAL, 340 * MHZ),
87 FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, CLK_XTAL, 340 * MHZ),
88 FIXED_CLK(CLK_TOP_HADDS2_FB, CLK_XTAL, 27 * MHZ),
89 FIXED_CLK(CLK_TOP_WBG_DIG_416M, CLK_XTAL, 416 * MHZ),
90 FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, CLK_XTAL, 143 * MHZ),
91 FIXED_CLK(CLK_TOP_HDMI_SCL_RX, CLK_XTAL, 27 * MHZ),
92 FIXED_CLK(CLK_TOP_32K_EXTERNAL, CLK_XTAL, 32000),
93 FIXED_CLK(CLK_TOP_HDMITX_CLKDIG_CTS, CLK_XTAL, 300 * MHZ),
94 FIXED_CLK(CLK_TOP_AUD_EXT1, CLK_XTAL, 0),
95 FIXED_CLK(CLK_TOP_AUD_EXT2, CLK_XTAL, 0),
96 FIXED_CLK(CLK_TOP_NFI1X_PAD, CLK_XTAL, 0),
97};
98
99static const struct mtk_fixed_factor top_fixed_divs[] = {
100 FACTOR0(CLK_TOP_SYSPLL, CLK_APMIXED_MAINPLL, 1, 1),
101 FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
102 FACTOR0(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
103 FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
104 FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
105 FACTOR1(CLK_TOP_SYSPLL1_D2, CLK_TOP_SYSPLL_D2, 1, 2),
106 FACTOR1(CLK_TOP_SYSPLL1_D4, CLK_TOP_SYSPLL_D2, 1, 4),
107 FACTOR1(CLK_TOP_SYSPLL1_D8, CLK_TOP_SYSPLL_D2, 1, 8),
108 FACTOR1(CLK_TOP_SYSPLL1_D16, CLK_TOP_SYSPLL_D2, 1, 16),
109 FACTOR1(CLK_TOP_SYSPLL2_D2, CLK_TOP_SYSPLL_D3, 1, 2),
110 FACTOR1(CLK_TOP_SYSPLL2_D4, CLK_TOP_SYSPLL_D3, 1, 4),
111 FACTOR1(CLK_TOP_SYSPLL2_D8, CLK_TOP_SYSPLL_D3, 1, 8),
112 FACTOR1(CLK_TOP_SYSPLL3_D2, CLK_TOP_SYSPLL_D5, 1, 2),
113 FACTOR1(CLK_TOP_SYSPLL3_D4, CLK_TOP_SYSPLL_D5, 1, 4),
114 FACTOR1(CLK_TOP_SYSPLL4_D2, CLK_TOP_SYSPLL_D7, 1, 2),
115 FACTOR1(CLK_TOP_SYSPLL4_D4, CLK_TOP_SYSPLL_D7, 1, 4),
116
117 FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIVPLL, 1, 1),
118 FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
119 FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
120 FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5),
121 FACTOR0(CLK_TOP_UNIVPLL_D7, CLK_APMIXED_UNIVPLL, 1, 7),
122 FACTOR0(CLK_TOP_UNIVPLL_D26, CLK_APMIXED_UNIVPLL, 1, 26),
123 FACTOR0(CLK_TOP_UNIVPLL_D52, CLK_APMIXED_UNIVPLL, 1, 52),
124 FACTOR0(CLK_TOP_UNIVPLL_D108, CLK_APMIXED_UNIVPLL, 1, 108),
125 FACTOR0(CLK_TOP_USB_PHY48M, CLK_APMIXED_UNIVPLL, 1, 26),
126 FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL_D2, 1, 2),
127 FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL_D2, 1, 4),
128 FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL_D2, 1, 8),
129 FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL_D3, 1, 2),
130 FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL_D3, 1, 4),
131 FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL_D3, 1, 8),
132 FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL_D3, 1, 16),
133 FACTOR1(CLK_TOP_UNIVPLL2_D32, CLK_TOP_UNIVPLL_D3, 1, 32),
134 FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL_D5, 1, 2),
135 FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL_D5, 1, 4),
136 FACTOR1(CLK_TOP_UNIVPLL3_D8, CLK_TOP_UNIVPLL_D5, 1, 8),
137
138 FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1),
139 FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2),
140 FACTOR0(CLK_TOP_MSDCPLL_D4, CLK_APMIXED_MSDCPLL, 1, 4),
141 FACTOR0(CLK_TOP_MSDCPLL_D8, CLK_APMIXED_MSDCPLL, 1, 8),
142
143 FACTOR0(CLK_TOP_MMPLL, CLK_APMIXED_MMPLL, 1, 1),
144 FACTOR0(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2),
145
146 FACTOR1(CLK_TOP_DMPLL_D2, CLK_TOP_DMPLL, 1, 2),
147 FACTOR1(CLK_TOP_DMPLL_D4, CLK_TOP_DMPLL, 1, 4),
148 FACTOR1(CLK_TOP_DMPLL_X2, CLK_TOP_DMPLL, 1, 1),
149
150 FACTOR0(CLK_TOP_TVDPLL, CLK_APMIXED_TVDPLL, 1, 1),
151 FACTOR0(CLK_TOP_TVDPLL_D2, CLK_APMIXED_TVDPLL, 1, 2),
152 FACTOR0(CLK_TOP_TVDPLL_D4, CLK_APMIXED_TVDPLL, 1, 4),
153
154 FACTOR0(CLK_TOP_VDECPLL, CLK_APMIXED_VDECPLL, 1, 1),
155 FACTOR0(CLK_TOP_TVD2PLL, CLK_APMIXED_TVD2PLL, 1, 1),
156 FACTOR0(CLK_TOP_TVD2PLL_D2, CLK_APMIXED_TVD2PLL, 1, 2),
157
158 FACTOR1(CLK_TOP_MIPIPLL, CLK_TOP_DPI, 1, 1),
159 FACTOR1(CLK_TOP_MIPIPLL_D2, CLK_TOP_DPI, 1, 2),
160 FACTOR1(CLK_TOP_MIPIPLL_D4, CLK_TOP_DPI, 1, 4),
161
162 FACTOR1(CLK_TOP_HDMIPLL, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 1),
163 FACTOR1(CLK_TOP_HDMIPLL_D2, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 2),
164 FACTOR1(CLK_TOP_HDMIPLL_D3, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 3),
165
166 FACTOR0(CLK_TOP_ARMPLL_1P3G, CLK_APMIXED_ARMPLL, 1, 1),
167
168 FACTOR1(CLK_TOP_AUDPLL, CLK_TOP_AUDPLL_MUX_SEL, 1, 1),
169 FACTOR1(CLK_TOP_AUDPLL_D4, CLK_TOP_AUDPLL_MUX_SEL, 1, 4),
170 FACTOR1(CLK_TOP_AUDPLL_D8, CLK_TOP_AUDPLL_MUX_SEL, 1, 8),
171 FACTOR1(CLK_TOP_AUDPLL_D16, CLK_TOP_AUDPLL_MUX_SEL, 1, 16),
172 FACTOR1(CLK_TOP_AUDPLL_D24, CLK_TOP_AUDPLL_MUX_SEL, 1, 24),
173
174 FACTOR0(CLK_TOP_AUD1PLL_98M, CLK_APMIXED_AUD1PLL, 1, 3),
175 FACTOR0(CLK_TOP_AUD2PLL_90M, CLK_APMIXED_AUD2PLL, 1, 3),
176 FACTOR0(CLK_TOP_HADDS2PLL_98M, CLK_APMIXED_HADDS2PLL, 1, 3),
177 FACTOR0(CLK_TOP_HADDS2PLL_294M, CLK_APMIXED_HADDS2PLL, 1, 1),
178 FACTOR0(CLK_TOP_ETHPLL_500M, CLK_APMIXED_ETHPLL, 1, 1),
179 FACTOR2(CLK_TOP_CLK26M_D8, CLK_XTAL, 1, 8),
180 FACTOR2(CLK_TOP_32K_INTERNAL, CLK_XTAL, 1, 793),
181 FACTOR1(CLK_TOP_AXISEL_D4, CLK_TOP_AXI_SEL, 1, 4),
182 FACTOR1(CLK_TOP_8BDAC, CLK_TOP_UNIVPLL_D2, 1, 1),
183};
184
185static const int axi_parents[] = {
186 CLK_XTAL,
187 CLK_TOP_SYSPLL1_D2,
188 CLK_TOP_SYSPLL_D5,
189 CLK_TOP_SYSPLL1_D4,
190 CLK_TOP_UNIVPLL_D5,
191 CLK_TOP_UNIVPLL2_D2,
192 CLK_TOP_MMPLL_D2,
193 CLK_TOP_DMPLL_D2
194};
195
196static const int mem_parents[] = {
197 CLK_XTAL,
198 CLK_TOP_DMPLL
199};
200
201static const int ddrphycfg_parents[] = {
202 CLK_XTAL,
203 CLK_TOP_SYSPLL1_D8
204};
205
206static const int mm_parents[] = {
207 CLK_XTAL,
208 CLK_TOP_VENCPLL,
209 CLK_TOP_SYSPLL1_D2,
210 CLK_TOP_SYSPLL1_D4,
211 CLK_TOP_UNIVPLL_D5,
212 CLK_TOP_UNIVPLL1_D2,
213 CLK_TOP_UNIVPLL2_D2,
214 CLK_TOP_DMPLL
215};
216
217static const int pwm_parents[] = {
218 CLK_XTAL,
219 CLK_TOP_UNIVPLL2_D4,
220 CLK_TOP_UNIVPLL3_D2,
221 CLK_TOP_UNIVPLL1_D4
222};
223
224static const int vdec_parents[] = {
225 CLK_XTAL,
226 CLK_TOP_VDECPLL,
227 CLK_TOP_SYSPLL_D5,
228 CLK_TOP_SYSPLL1_D4,
229 CLK_TOP_UNIVPLL_D5,
230 CLK_TOP_UNIVPLL2_D2,
231 CLK_TOP_VENCPLL,
232 CLK_TOP_MSDCPLL_D2,
233 CLK_TOP_MMPLL_D2
234};
235
236static const int mfg_parents[] = {
237 CLK_XTAL,
238 CLK_TOP_MMPLL,
239 CLK_TOP_DMPLL_X2,
240 CLK_TOP_MSDCPLL,
241 CLK_XTAL,
242 CLK_TOP_SYSPLL_D3,
243 CLK_TOP_UNIVPLL_D3,
244 CLK_TOP_UNIVPLL1_D2
245};
246
247static const int camtg_parents[] = {
248 CLK_XTAL,
249 CLK_TOP_UNIVPLL_D26,
250 CLK_TOP_UNIVPLL2_D2,
251 CLK_TOP_SYSPLL3_D2,
252 CLK_TOP_SYSPLL3_D4,
253 CLK_TOP_MSDCPLL_D2,
254 CLK_TOP_MMPLL_D2
255};
256
257static const int uart_parents[] = {
258 CLK_XTAL,
259 CLK_TOP_UNIVPLL2_D8
260};
261
262static const int spi_parents[] = {
263 CLK_XTAL,
264 CLK_TOP_SYSPLL3_D2,
265 CLK_TOP_SYSPLL4_D2,
266 CLK_TOP_UNIVPLL2_D4,
267 CLK_TOP_UNIVPLL1_D8
268};
269
270static const int usb20_parents[] = {
271 CLK_XTAL,
272 CLK_TOP_UNIVPLL1_D8,
273 CLK_TOP_UNIVPLL3_D4
274};
275
276static const int msdc30_parents[] = {
277 CLK_XTAL,
278 CLK_TOP_MSDCPLL_D2,
279 CLK_TOP_SYSPLL2_D2,
280 CLK_TOP_SYSPLL1_D4,
281 CLK_TOP_UNIVPLL1_D4,
282 CLK_TOP_UNIVPLL2_D4,
283};
284
285static const int aud_intbus_parents[] = {
286 CLK_XTAL,
287 CLK_TOP_SYSPLL1_D4,
288 CLK_TOP_SYSPLL3_D2,
289 CLK_TOP_SYSPLL4_D2,
290 CLK_TOP_UNIVPLL3_D2,
291 CLK_TOP_UNIVPLL2_D4
292};
293
294static const int pmicspi_parents[] = {
295 CLK_XTAL,
296 CLK_TOP_SYSPLL1_D8,
297 CLK_TOP_SYSPLL2_D4,
298 CLK_TOP_SYSPLL4_D2,
299 CLK_TOP_SYSPLL3_D4,
300 CLK_TOP_SYSPLL2_D8,
301 CLK_TOP_SYSPLL1_D16,
302 CLK_TOP_UNIVPLL3_D4,
303 CLK_TOP_UNIVPLL_D26,
304 CLK_TOP_DMPLL_D2,
305 CLK_TOP_DMPLL_D4
306};
307
308static const int scp_parents[] = {
309 CLK_XTAL,
310 CLK_TOP_SYSPLL1_D8,
311 CLK_TOP_DMPLL_D2,
312 CLK_TOP_DMPLL_D4
313};
314
315static const int dpi0_tve_parents[] = {
316 CLK_XTAL,
317 CLK_TOP_MIPIPLL,
318 CLK_TOP_MIPIPLL_D2,
319 CLK_TOP_MIPIPLL_D4,
320 CLK_XTAL,
321 CLK_TOP_TVDPLL,
322 CLK_TOP_TVDPLL_D2,
323 CLK_TOP_TVDPLL_D4
324};
325
326static const int dpi1_parents[] = {
327 CLK_XTAL,
328 CLK_TOP_TVDPLL,
329 CLK_TOP_TVDPLL_D2,
330 CLK_TOP_TVDPLL_D4
331};
332
333static const int hdmi_parents[] = {
334 CLK_XTAL,
335 CLK_TOP_HDMIPLL,
336 CLK_TOP_HDMIPLL_D2,
337 CLK_TOP_HDMIPLL_D3
338};
339
340static const int apll_parents[] = {
341 CLK_XTAL,
342 CLK_TOP_AUDPLL,
343 CLK_TOP_AUDPLL_D4,
344 CLK_TOP_AUDPLL_D8,
345 CLK_TOP_AUDPLL_D16,
346 CLK_TOP_AUDPLL_D24,
347 CLK_XTAL,
348 CLK_XTAL
349};
350
351static const int rtc_parents[] = {
352 CLK_TOP_32K_INTERNAL,
353 CLK_TOP_32K_EXTERNAL,
354 CLK_XTAL,
355 CLK_TOP_UNIVPLL3_D8
356};
357
358static const int nfi2x_parents[] = {
359 CLK_XTAL,
360 CLK_TOP_SYSPLL2_D2,
361 CLK_TOP_SYSPLL_D7,
362 CLK_TOP_UNIVPLL3_D2,
363 CLK_TOP_SYSPLL2_D4,
364 CLK_TOP_UNIVPLL3_D4,
365 CLK_TOP_SYSPLL4_D4,
366 CLK_XTAL
367};
368
369static const int emmc_hclk_parents[] = {
370 CLK_XTAL,
371 CLK_TOP_SYSPLL1_D2,
372 CLK_TOP_SYSPLL1_D4,
373 CLK_TOP_SYSPLL2_D2
374};
375
376static const int flash_parents[] = {
377 CLK_TOP_CLK26M_D8,
378 CLK_XTAL,
379 CLK_TOP_SYSPLL2_D8,
380 CLK_TOP_SYSPLL3_D4,
381 CLK_TOP_UNIVPLL3_D4,
382 CLK_TOP_SYSPLL4_D2,
383 CLK_TOP_SYSPLL2_D4,
384 CLK_TOP_UNIVPLL2_D4
385};
386
387static const int di_parents[] = {
388 CLK_XTAL,
389 CLK_TOP_TVD2PLL,
390 CLK_TOP_TVD2PLL_D2,
391 CLK_XTAL
392};
393
394static const int nr_osd_parents[] = {
395 CLK_XTAL,
396 CLK_TOP_VENCPLL,
397 CLK_TOP_SYSPLL1_D2,
398 CLK_TOP_SYSPLL1_D4,
399 CLK_TOP_UNIVPLL_D5,
400 CLK_TOP_UNIVPLL1_D2,
401 CLK_TOP_UNIVPLL2_D2,
402 CLK_TOP_DMPLL
403};
404
405static const int hdmirx_bist_parents[] = {
406 CLK_XTAL,
407 CLK_TOP_SYSPLL_D3,
408 CLK_XTAL,
409 CLK_TOP_SYSPLL1_D16,
410 CLK_TOP_SYSPLL4_D2,
411 CLK_TOP_SYSPLL1_D4,
412 CLK_TOP_VENCPLL,
413 CLK_XTAL
414};
415
416static const int intdir_parents[] = {
417 CLK_XTAL,
418 CLK_TOP_MMPLL,
419 CLK_TOP_SYSPLL_D2,
420 CLK_TOP_UNIVPLL_D2
421};
422
423static const int asm_parents[] = {
424 CLK_XTAL,
425 CLK_TOP_UNIVPLL2_D4,
426 CLK_TOP_UNIVPLL2_D2,
427 CLK_TOP_SYSPLL_D5
428};
429
430static const int ms_card_parents[] = {
431 CLK_XTAL,
432 CLK_TOP_UNIVPLL3_D8,
433 CLK_TOP_SYSPLL4_D4
434};
435
436static const int ethif_parents[] = {
437 CLK_XTAL,
438 CLK_TOP_SYSPLL1_D2,
439 CLK_TOP_SYSPLL_D5,
440 CLK_TOP_SYSPLL1_D4,
441 CLK_TOP_UNIVPLL_D5,
442 CLK_TOP_UNIVPLL1_D2,
443 CLK_TOP_DMPLL,
444 CLK_TOP_DMPLL_D2
445};
446
447static const int hdmirx_parents[] = {
448 CLK_XTAL,
449 CLK_TOP_UNIVPLL_D52
450};
451
452static const int cmsys_parents[] = {
453 CLK_XTAL,
454 CLK_TOP_SYSPLL1_D2,
455 CLK_TOP_UNIVPLL1_D2,
456 CLK_TOP_UNIVPLL_D5,
457 CLK_TOP_SYSPLL_D5,
458 CLK_TOP_SYSPLL2_D2,
459 CLK_TOP_SYSPLL1_D4,
460 CLK_TOP_SYSPLL3_D2,
461 CLK_TOP_SYSPLL2_D4,
462 CLK_TOP_SYSPLL1_D8,
463 CLK_XTAL,
464 CLK_XTAL,
465 CLK_XTAL,
466 CLK_XTAL,
467 CLK_XTAL
468};
469
470static const int clk_8bdac_parents[] = {
471 CLK_TOP_32K_INTERNAL,
472 CLK_TOP_8BDAC,
473 CLK_XTAL,
474 CLK_XTAL
475};
476
477static const int aud2dvd_parents[] = {
478 CLK_TOP_AUD_48K_TIMING,
479 CLK_TOP_AUD_44K_TIMING
480};
481
482static const int padmclk_parents[] = {
483 CLK_XTAL,
484 CLK_TOP_UNIVPLL_D26,
485 CLK_TOP_UNIVPLL_D52,
486 CLK_TOP_UNIVPLL_D108,
487 CLK_TOP_UNIVPLL2_D8,
488 CLK_TOP_UNIVPLL2_D16,
489 CLK_TOP_UNIVPLL2_D32
490};
491
492static const int aud_mux_parents[] = {
493 CLK_XTAL,
494 CLK_TOP_AUD1PLL_98M,
495 CLK_TOP_AUD2PLL_90M,
496 CLK_TOP_HADDS2PLL_98M,
497 CLK_TOP_AUD_EXTCK1_DIV,
498 CLK_TOP_AUD_EXTCK2_DIV
499};
500
501static const int aud_src_parents[] = {
502 CLK_TOP_AUD_MUX1_SEL,
503 CLK_TOP_AUD_MUX2_SEL
504};
505
506static const struct mtk_composite top_muxes[] = {
507 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
508 MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
509 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
510 MUX_GATE_FLAGS(CLK_TOP_MM_SEL, mm_parents, 0x40, 24, 3, 31,
511 CLK_DOMAIN_SCPSYS),
512
513 MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
514 MUX_GATE(CLK_TOP_VDEC_SEL, vdec_parents, 0x50, 8, 4, 15),
515 MUX_GATE_FLAGS(CLK_TOP_MFG_SEL, mfg_parents, 0x50, 16, 3, 23,
516 CLK_DOMAIN_SCPSYS),
517 MUX_GATE(CLK_TOP_CAMTG_SEL, camtg_parents, 0x50, 24, 3, 31),
518
519 MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
520 MUX_GATE(CLK_TOP_SPI0_SEL, spi_parents, 0x60, 8, 3, 15),
521 MUX_GATE(CLK_TOP_USB20_SEL, usb20_parents, 0x60, 16, 2, 23),
522 MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_parents, 0x60, 24, 3, 31),
523
524 MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_parents, 0x70, 0, 3, 7),
525 MUX_GATE(CLK_TOP_MSDC30_2_SEL, msdc30_parents, 0x70, 8, 3, 15),
526 MUX_GATE(CLK_TOP_AUDIO_SEL, msdc30_parents, 0x70, 16, 1, 23),
527 MUX_GATE(CLK_TOP_AUDINTBUS_SEL, aud_intbus_parents, 0x70, 24, 3, 31),
528
529 MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 0, 4, 7),
530 MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x80, 8, 2, 15),
531 MUX_GATE(CLK_TOP_DPI0_SEL, dpi0_tve_parents, 0x80, 16, 3, 23),
532 MUX_GATE(CLK_TOP_DPI1_SEL, dpi1_parents, 0x80, 24, 2, 31),
533
534 MUX_GATE(CLK_TOP_TVE_SEL, dpi0_tve_parents, 0x90, 0, 3, 7),
535 MUX_GATE(CLK_TOP_HDMI_SEL, hdmi_parents, 0x90, 8, 2, 15),
536 MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23),
537
538 MUX_GATE(CLK_TOP_RTC_SEL, rtc_parents, 0xA0, 0, 2, 7),
539 MUX_GATE(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0xA0, 8, 3, 15),
540 MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, emmc_hclk_parents, 0xA0, 24, 2, 31),
541
542 MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0xB0, 0, 3, 7),
543 MUX_GATE(CLK_TOP_DI_SEL, di_parents, 0xB0, 8, 2, 15),
544 MUX_GATE(CLK_TOP_NR_SEL, nr_osd_parents, 0xB0, 16, 3, 23),
545 MUX_GATE(CLK_TOP_OSD_SEL, nr_osd_parents, 0xB0, 24, 3, 31),
546
547 MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, hdmirx_bist_parents, 0xC0, 0, 3, 7),
548 MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0xC0, 8, 2, 15),
549 MUX_GATE(CLK_TOP_ASM_I_SEL, asm_parents, 0xC0, 16, 2, 23),
550 MUX_GATE(CLK_TOP_ASM_M_SEL, asm_parents, 0xC0, 24, 3, 31),
551
552 MUX_GATE(CLK_TOP_ASM_H_SEL, asm_parents, 0xD0, 0, 2, 7),
553 MUX_GATE(CLK_TOP_MS_CARD_SEL, ms_card_parents, 0xD0, 16, 2, 23),
554 MUX_GATE_FLAGS(CLK_TOP_ETHIF_SEL, ethif_parents, 0xD0, 24, 3, 31,
555 CLK_DOMAIN_SCPSYS),
556
557 MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, hdmirx_parents, 0xE0, 0, 1, 7),
558 MUX_GATE(CLK_TOP_MSDC30_3_SEL, msdc30_parents, 0xE0, 8, 3, 15),
559 MUX_GATE(CLK_TOP_CMSYS_SEL, cmsys_parents, 0xE0, 16, 4, 23),
560
561 MUX_GATE(CLK_TOP_SPI1_SEL, spi_parents, 0xE0, 24, 3, 31),
562 MUX_GATE(CLK_TOP_SPI2_SEL, spi_parents, 0xF0, 0, 3, 7),
563 MUX_GATE(CLK_TOP_8BDAC_SEL, clk_8bdac_parents, 0xF0, 8, 2, 15),
564 MUX_GATE(CLK_TOP_AUD2DVD_SEL, aud2dvd_parents, 0xF0, 16, 1, 23),
565
566 MUX(CLK_TOP_PADMCLK_SEL, padmclk_parents, 0x100, 0, 3),
567
568 MUX(CLK_TOP_AUD_MUX1_SEL, aud_mux_parents, 0x12c, 0, 3),
569 MUX(CLK_TOP_AUD_MUX2_SEL, aud_mux_parents, 0x12c, 3, 3),
570 MUX(CLK_TOP_AUDPLL_MUX_SEL, aud_mux_parents, 0x12c, 6, 3),
571
572 MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, aud_src_parents, 0x12c, 15, 1, 23),
573 MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, aud_src_parents, 0x12c, 16, 1, 24),
574 MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, aud_src_parents, 0x12c, 17, 1, 25),
575 MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, aud_src_parents, 0x12c, 18, 1, 26),
576 MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, aud_src_parents, 0x12c, 19, 1, 27),
577 MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, aud_src_parents, 0x12c, 20, 1, 28),
578};
579
580/* infracfg */
581static const struct mtk_gate_regs infra_cg_regs = {
582 .set_ofs = 0x40,
583 .clr_ofs = 0x44,
584 .sta_ofs = 0x48,
585};
586
587#define GATE_INFRA(_id, _parent, _shift) { \
588 .id = _id, \
589 .parent = _parent, \
590 .regs = &infra_cg_regs, \
591 .shift = _shift, \
592 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
593 }
594
595static const struct mtk_gate infra_cgs[] = {
596 GATE_INFRA(CLK_INFRA_DBG, CLK_TOP_AXI_SEL, 0),
597 GATE_INFRA(CLK_INFRA_SMI, CLK_TOP_MM_SEL, 1),
598 GATE_INFRA(CLK_INFRA_QAXI_CM4, CLK_TOP_AXI_SEL, 2),
599 GATE_INFRA(CLK_INFRA_AUD_SPLIN_B, CLK_TOP_HADDS2PLL_294M, 4),
600 GATE_INFRA(CLK_INFRA_AUDIO, CLK_XTAL, 5),
601 GATE_INFRA(CLK_INFRA_EFUSE, CLK_XTAL, 6),
602 GATE_INFRA(CLK_INFRA_L2C_SRAM, CLK_TOP_MM_SEL, 7),
603 GATE_INFRA(CLK_INFRA_M4U, CLK_TOP_MEM_SEL, 8),
604 GATE_INFRA(CLK_INFRA_CONNMCU, CLK_TOP_WBG_DIG_416M, 12),
605 GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 13),
606 GATE_INFRA(CLK_INFRA_RAMBUFIF, CLK_TOP_MEM_SEL, 14),
607 GATE_INFRA(CLK_INFRA_CPUM, CLK_TOP_MEM_SEL, 15),
608 GATE_INFRA(CLK_INFRA_KP, CLK_TOP_AXI_SEL, 16),
609 GATE_INFRA(CLK_INFRA_CEC, CLK_TOP_RTC_SEL, 18),
610 GATE_INFRA(CLK_INFRA_IRRX, CLK_TOP_AXI_SEL, 19),
611 GATE_INFRA(CLK_INFRA_PMICSPI, CLK_TOP_PMICSPI_SEL, 22),
612 GATE_INFRA(CLK_INFRA_PMICWRAP, CLK_TOP_AXI_SEL, 23),
613 GATE_INFRA(CLK_INFRA_DDCCI, CLK_TOP_AXI_SEL, 24),
614};
615
616/* pericfg */
617static const struct mtk_gate_regs peri0_cg_regs = {
618 .set_ofs = 0x8,
619 .clr_ofs = 0x10,
620 .sta_ofs = 0x18,
621};
622
623static const struct mtk_gate_regs peri1_cg_regs = {
624 .set_ofs = 0xC,
625 .clr_ofs = 0x14,
626 .sta_ofs = 0x1C,
627};
628
629#define GATE_PERI0(_id, _parent, _shift) { \
630 .id = _id, \
631 .parent = _parent, \
632 .regs = &peri0_cg_regs, \
633 .shift = _shift, \
634 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
635 }
636
637#define GATE_PERI1(_id, _parent, _shift) { \
638 .id = _id, \
639 .parent = _parent, \
640 .regs = &peri1_cg_regs, \
641 .shift = _shift, \
642 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
643 }
644
645static const struct mtk_gate peri_cgs[] = {
646 GATE_PERI0(CLK_PERI_NFI, CLK_TOP_NFI2X_SEL, 0),
647 GATE_PERI0(CLK_PERI_THERM, CLK_TOP_AXI_SEL, 1),
648 GATE_PERI0(CLK_PERI_PWM1, CLK_TOP_AXISEL_D4, 2),
649 GATE_PERI0(CLK_PERI_PWM2, CLK_TOP_AXISEL_D4, 3),
650 GATE_PERI0(CLK_PERI_PWM3, CLK_TOP_AXISEL_D4, 4),
651 GATE_PERI0(CLK_PERI_PWM4, CLK_TOP_AXISEL_D4, 5),
652 GATE_PERI0(CLK_PERI_PWM5, CLK_TOP_AXISEL_D4, 6),
653 GATE_PERI0(CLK_PERI_PWM6, CLK_TOP_AXISEL_D4, 7),
654 GATE_PERI0(CLK_PERI_PWM7, CLK_TOP_AXISEL_D4, 8),
655 GATE_PERI0(CLK_PERI_PWM, CLK_TOP_AXI_SEL, 9),
656 GATE_PERI0(CLK_PERI_USB0, CLK_TOP_USB20_SEL, 10),
657 GATE_PERI0(CLK_PERI_USB1, CLK_TOP_USB20_SEL, 11),
658 GATE_PERI0(CLK_PERI_AP_DMA, CLK_TOP_AXI_SEL, 12),
659 GATE_PERI0(CLK_PERI_MSDC30_0, CLK_TOP_MSDC30_0_SEL, 13),
660 GATE_PERI0(CLK_PERI_MSDC30_1, CLK_TOP_MSDC30_1_SEL, 14),
661 GATE_PERI0(CLK_PERI_MSDC30_2, CLK_TOP_MSDC30_2_SEL, 15),
662 GATE_PERI0(CLK_PERI_MSDC30_3, CLK_TOP_MSDC30_3_SEL, 16),
663 GATE_PERI0(CLK_PERI_MSDC50_3, CLK_TOP_EMMC_HCLK_SEL, 17),
664 GATE_PERI0(CLK_PERI_NLI, CLK_TOP_AXI_SEL, 18),
665 GATE_PERI0(CLK_PERI_UART0, CLK_TOP_AXI_SEL, 19),
666 GATE_PERI0(CLK_PERI_UART1, CLK_TOP_AXI_SEL, 20),
667 GATE_PERI0(CLK_PERI_UART2, CLK_TOP_AXI_SEL, 21),
668 GATE_PERI0(CLK_PERI_UART3, CLK_TOP_AXI_SEL, 22),
669 GATE_PERI0(CLK_PERI_BTIF, CLK_TOP_AXI_SEL, 23),
670 GATE_PERI0(CLK_PERI_I2C0, CLK_TOP_AXI_SEL, 24),
671 GATE_PERI0(CLK_PERI_I2C1, CLK_TOP_AXI_SEL, 25),
672 GATE_PERI0(CLK_PERI_I2C2, CLK_TOP_AXI_SEL, 26),
673 GATE_PERI0(CLK_PERI_I2C3, CLK_XTAL, 27),
674 GATE_PERI0(CLK_PERI_AUXADC, CLK_XTAL, 28),
675 GATE_PERI0(CLK_PERI_SPI0, CLK_TOP_SPI0_SEL, 29),
676 GATE_PERI0(CLK_PERI_ETH, CLK_XTAL, 30),
677 GATE_PERI0(CLK_PERI_USB0_MCU, CLK_TOP_AXI_SEL, 31),
678
679 GATE_PERI1(CLK_PERI_USB1_MCU, CLK_TOP_AXI_SEL, 0),
680 GATE_PERI1(CLK_PERI_USB_SLV, CLK_TOP_AXI_SEL, 1),
681 GATE_PERI1(CLK_PERI_GCPU, CLK_TOP_AXI_SEL, 2),
682 GATE_PERI1(CLK_PERI_NFI_ECC, CLK_TOP_NFI1X_PAD, 3),
683 GATE_PERI1(CLK_PERI_NFI_PAD, CLK_TOP_NFI1X_PAD, 4),
684 GATE_PERI1(CLK_PERI_FLASH, CLK_TOP_NFI2X_SEL, 5),
685 GATE_PERI1(CLK_PERI_HOST89_INT, CLK_TOP_AXI_SEL, 6),
686 GATE_PERI1(CLK_PERI_HOST89_SPI, CLK_TOP_SPI0_SEL, 7),
687 GATE_PERI1(CLK_PERI_HOST89_DVD, CLK_TOP_AUD2DVD_SEL, 8),
688 GATE_PERI1(CLK_PERI_SPI1, CLK_TOP_SPI1_SEL, 9),
689 GATE_PERI1(CLK_PERI_SPI2, CLK_TOP_SPI2_SEL, 10),
690 GATE_PERI1(CLK_PERI_FCI, CLK_TOP_MS_CARD_SEL, 11),
691};
692
693/* ethsys */
694static const struct mtk_gate_regs eth_cg_regs = {
695 .sta_ofs = 0x30,
696};
697
698#define GATE_ETH(_id, _parent, _shift, _flag) { \
699 .id = _id, \
700 .parent = _parent, \
701 .regs = &eth_cg_regs, \
702 .shift = _shift, \
703 .flags = CLK_GATE_NO_SETCLR_INV | (_flag), \
704 }
705
706#define GATE_ETH0(_id, _parent, _shift) \
707 GATE_ETH(_id, _parent, _shift, CLK_PARENT_APMIXED)
708
709#define GATE_ETH1(_id, _parent, _shift) \
710 GATE_ETH(_id, _parent, _shift, CLK_PARENT_TOPCKGEN)
711
712static const struct mtk_gate eth_cgs[] = {
713 GATE_ETH1(CLK_ETHSYS_HSDMA, CLK_TOP_ETHIF_SEL, 5),
714 GATE_ETH1(CLK_ETHSYS_ESW, CLK_TOP_ETHPLL_500M, 6),
715 GATE_ETH0(CLK_ETHSYS_GP2, CLK_APMIXED_TRGPLL, 7),
716 GATE_ETH1(CLK_ETHSYS_GP1, CLK_TOP_ETHPLL_500M, 8),
717 GATE_ETH1(CLK_ETHSYS_PCM, CLK_TOP_ETHIF_SEL, 11),
718 GATE_ETH1(CLK_ETHSYS_GDMA, CLK_TOP_ETHIF_SEL, 14),
719 GATE_ETH1(CLK_ETHSYS_I2S, CLK_TOP_ETHIF_SEL, 17),
720 GATE_ETH1(CLK_ETHSYS_CRYPTO, CLK_TOP_ETHIF_SEL, 29),
721};
722
723static const struct mtk_clk_tree mt7623_clk_tree = {
724 .xtal_rate = 26 * MHZ,
725 .xtal2_rate = 26 * MHZ,
726 .fdivs_offs = CLK_TOP_SYSPLL,
727 .muxes_offs = CLK_TOP_AXI_SEL,
728 .plls = apmixed_plls,
729 .fclks = top_fixed_clks,
730 .fdivs = top_fixed_divs,
731 .muxes = top_muxes,
732};
733
734static int mt7623_mcucfg_probe(struct udevice *dev)
735{
736 void __iomem *base;
737
738 base = dev_read_addr_ptr(dev);
739 if (!base)
740 return -ENOENT;
741
742 clrsetbits_le32(base + MCU_AXI_DIV, AXI_DIV_MSK,
743 AXI_DIV_SEL(0x12));
744
745 return 0;
746}
747
748static int mt7623_apmixedsys_probe(struct udevice *dev)
749{
750 struct mtk_clk_priv *priv = dev_get_priv(dev);
751 int ret;
752
753 ret = mtk_common_clk_init(dev, &mt7623_clk_tree);
754 if (ret)
755 return ret;
756
757 /* reduce clock square disable time */
758 writel(0x50001, priv->base + MT7623_CLKSQ_STB_CON0);
759 /* extend control timing to 1us */
760 writel(0x888, priv->base + MT7623_PLL_ISO_CON0);
761
762 return 0;
763}
764
765static int mt7623_topckgen_probe(struct udevice *dev)
766{
767 return mtk_common_clk_init(dev, &mt7623_clk_tree);
768}
769
770static int mt7623_infracfg_probe(struct udevice *dev)
771{
772 return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, infra_cgs);
773}
774
775static int mt7623_pericfg_probe(struct udevice *dev)
776{
777 return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, peri_cgs);
778}
779
780static int mt7623_ethsys_probe(struct udevice *dev)
781{
782 return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, eth_cgs);
783}
784
785static const struct udevice_id mt7623_apmixed_compat[] = {
786 { .compatible = "mediatek,mt7623-apmixedsys" },
787 { }
788};
789
790static const struct udevice_id mt7623_topckgen_compat[] = {
791 { .compatible = "mediatek,mt7623-topckgen" },
792 { }
793};
794
795static const struct udevice_id mt7623_infracfg_compat[] = {
796 { .compatible = "mediatek,mt7623-infracfg", },
797 { }
798};
799
800static const struct udevice_id mt7623_pericfg_compat[] = {
801 { .compatible = "mediatek,mt7623-pericfg", },
802 { }
803};
804
805static const struct udevice_id mt7623_ethsys_compat[] = {
806 { .compatible = "mediatek,mt7623-ethsys" },
807 { }
808};
809
810static const struct udevice_id mt7623_mcucfg_compat[] = {
811 { .compatible = "mediatek,mt7623-mcucfg" },
812 { }
813};
814
815U_BOOT_DRIVER(mtk_mcucfg) = {
816 .name = "mt7623-mcucfg",
817 .id = UCLASS_SYSCON,
818 .of_match = mt7623_mcucfg_compat,
819 .probe = mt7623_mcucfg_probe,
820 .flags = DM_FLAG_PRE_RELOC,
821};
822
823U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
824 .name = "mt7623-clock-apmixedsys",
825 .id = UCLASS_CLK,
826 .of_match = mt7623_apmixed_compat,
827 .probe = mt7623_apmixedsys_probe,
828 .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
829 .ops = &mtk_clk_apmixedsys_ops,
830 .flags = DM_FLAG_PRE_RELOC,
831};
832
833U_BOOT_DRIVER(mtk_clk_topckgen) = {
834 .name = "mt7623-clock-topckgen",
835 .id = UCLASS_CLK,
836 .of_match = mt7623_topckgen_compat,
837 .probe = mt7623_topckgen_probe,
838 .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
839 .ops = &mtk_clk_topckgen_ops,
840 .flags = DM_FLAG_PRE_RELOC,
841};
842
843U_BOOT_DRIVER(mtk_clk_infracfg) = {
844 .name = "mt7623-infracfg",
845 .id = UCLASS_CLK,
846 .of_match = mt7623_infracfg_compat,
847 .probe = mt7623_infracfg_probe,
848 .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
849 .ops = &mtk_clk_gate_ops,
850 .flags = DM_FLAG_PRE_RELOC,
851};
852
853U_BOOT_DRIVER(mtk_clk_pericfg) = {
854 .name = "mt7623-pericfg",
855 .id = UCLASS_CLK,
856 .of_match = mt7623_pericfg_compat,
857 .probe = mt7623_pericfg_probe,
858 .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
859 .ops = &mtk_clk_gate_ops,
860 .flags = DM_FLAG_PRE_RELOC,
861};
862
863U_BOOT_DRIVER(mtk_clk_ethsys) = {
864 .name = "mt7623-clock-ethsys",
865 .id = UCLASS_CLK,
866 .of_match = mt7623_ethsys_compat,
867 .probe = mt7623_ethsys_probe,
868 .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
869 .ops = &mtk_clk_gate_ops,
870};