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TsiChungLiew8ae158c2007-08-16 15:05:11 -05001/*
2 * Configuation settings for the Freescale MCF54455 EVB board.
3 *
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/*
27 * board/config.h - configuration options, board specific
28 */
29
30#ifndef _JAMICA54455_H
31#define _JAMICA54455_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37#define CONFIG_MCF5445x /* define processor family */
38#define CONFIG_M54455 /* define processor type */
39#define CONFIG_M54455EVB /* M54455EVB board */
40
41#undef DEBUG
42
43#define CONFIG_MCFUART
44#define CFG_UART_PORT (0)
45#define CONFIG_BAUDRATE 115200
46#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
47
48#undef CONFIG_WATCHDOG
49
50#define CONFIG_TIMESTAMP /* Print image info with timestamp */
51
52/*
53 * BOOTP options
54 */
55#define CONFIG_BOOTP_BOOTFILESIZE
56#define CONFIG_BOOTP_BOOTPATH
57#define CONFIG_BOOTP_GATEWAY
58#define CONFIG_BOOTP_HOSTNAME
59
60/* Command line configuration */
61#include <config_cmd_default.h>
62
63#define CONFIG_CMD_BOOTD
64#define CONFIG_CMD_CACHE
65#define CONFIG_CMD_DATE
66#define CONFIG_CMD_DHCP
67#define CONFIG_CMD_ELF
68#define CONFIG_CMD_EXT2
69#define CONFIG_CMD_FAT
70#define CONFIG_CMD_FLASH
71#define CONFIG_CMD_I2C
72#define CONFIG_CMD_IDE
73#define CONFIG_CMD_JFFS2
74#define CONFIG_CMD_MEMORY
75#define CONFIG_CMD_MISC
76#define CONFIG_CMD_MII
77#define CONFIG_CMD_NET
78#define CONFIG_CMD_PCI
79#define CONFIG_CMD_PING
80#define CONFIG_CMD_REGINFO
81
82#undef CONFIG_CMD_LOADB
83#undef CONFIG_CMD_LOADS
84
85/* Network configuration */
86#define CONFIG_MCFFEC
87#ifdef CONFIG_MCFFEC
88# define CONFIG_NET_MULTI 1
89# define CONFIG_MII 1
90# define CONFIG_CF_DOMII
91# define CFG_DISCOVER_PHY
92# define CFG_RX_ETH_BUFFER 8
93# define CFG_FAULT_ECHO_LINK_DOWN
94
95# define CFG_FEC0_PINMUX 0
96# define CFG_FEC1_PINMUX 0
97# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
98# define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE
99# define MCFFEC_TOUT_LOOP 50000
100# define CONFIG_HAS_ETH1
101
102# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
103# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
104# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
105# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
106# define CONFIG_ETHPRIME "FEC0"
107# define CONFIG_IPADDR 192.162.1.2
108# define CONFIG_NETMASK 255.255.255.0
109# define CONFIG_SERVERIP 192.162.1.1
110# define CONFIG_GATEWAYIP 192.162.1.1
111# define CONFIG_OVERWRITE_ETHADDR_ONCE
112
113/* If CFG_DISCOVER_PHY is not defined - hardcoded */
114# ifndef CFG_DISCOVER_PHY
115# define FECDUPLEX FULL
116# define FECSPEED _100BASET
117# else
118# ifndef CFG_FAULT_ECHO_LINK_DOWN
119# define CFG_FAULT_ECHO_LINK_DOWN
120# endif
121# endif /* CFG_DISCOVER_PHY */
122#endif
123
124#define CONFIG_HOSTNAME M54455EVB
125#define CONFIG_EXTRA_ENV_SETTINGS \
126 "netdev=eth0\0" \
127 "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \
128 "loadaddr=40010000\0" \
129 "u-boot=u-boot.bin\0" \
130 "load=tftp ${loadaddr) ${u-boot}\0" \
131 "upd=run load; run prog\0" \
132 "prog=prot off 0 2ffff;" \
133 "era 0 2ffff;" \
134 "cp.b ${loadaddr} 0 ${filesize};" \
135 "save\0" \
136 ""
137
138/* ATA configuration */
139#define CONFIG_ISO_PARTITION
140#define CONFIG_DOS_PARTITION
141#define CONFIG_IDE_RESET 1
142#define CONFIG_IDE_PREINIT 1
143#define CONFIG_ATAPI
144#undef CONFIG_LBA48
145
146#define CFG_IDE_MAXBUS 1
147#define CFG_IDE_MAXDEVICE 2
148
149#define CFG_ATA_BASE_ADDR 0x90000000
150#define CFG_ATA_IDE0_OFFSET 0
151
152#define CFG_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
153#define CFG_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
154#define CFG_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
155#define CFG_ATA_STRIDE 4 /* Interval between registers */
156#define _IO_BASE 0
157
158/* Realtime clock */
159#define CONFIG_MCFRTC
160#undef RTC_DEBUG
161#define CFG_RTC_OSCILLATOR (32 * CFG_HZ)
162
163/* Timer */
164#define CONFIG_MCFTMR
165#undef CONFIG_MCFPIT
166
167/* I2c */
168#define CONFIG_FSL_I2C
169#define CONFIG_HARD_I2C /* I2C with hardware support */
170#undef CONFIG_SOFT_I2C /* I2C bit-banged */
171#define CFG_I2C_SPEED 80000 /* I2C speed and slave address */
172#define CFG_I2C_SLAVE 0x7F
173#define CFG_I2C_OFFSET 0x58000
174#define CFG_IMMR CFG_MBAR
175
176/* PCI */
177#define CONFIG_PCI 1
178
179#define CFG_PCI_MEM_BUS 0xA0000000
180#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS
181#define CFG_PCI_MEM_SIZE 0x10000000
182
183#define CFG_PCI_IO_BUS 0xB1000000
184#define CFG_PCI_IO_PHYS CFG_PCI_IO_BUS
185#define CFG_PCI_IO_SIZE 0x01000000
186
187#define CFG_PCI_CFG_BUS 0xB0000000
188#define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS
189#define CFG_PCI_CFG_SIZE 0x01000000
190
191/* FPGA - Spartan 2 */
192/* experiment
193#define CONFIG_FPGA CFG_SPARTAN3
194#define CONFIG_FPGA_COUNT 1
195#define CFG_FPGA_PROG_FEEDBACK
196#define CFG_FPGA_CHECK_CTRLC
197*/
198
199/* Input, PCI, Flexbus, and VCO */
200#define CONFIG_EXTRA_CLOCK
201
202#define CONFIG_PRAM 512 /* 512 KB */
203
204#define CFG_PROMPT "-> "
205#define CFG_LONGHELP /* undef to save memory */
206
207#if defined(CONFIG_CMD_KGDB)
208#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
209#else
210#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
211#endif
212#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
213#define CFG_MAXARGS 16 /* max number of command args */
214#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
215
216#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x10000)
217
218#define CFG_HZ 1000
219
220#define CFG_MBAR 0xFC000000
221
222/*
223 * Low Level Configuration Settings
224 * (address mappings, register initial values, etc.)
225 * You should know what you are doing if you make changes here.
226 */
227
228/*-----------------------------------------------------------------------
229 * Definitions for initial stack pointer and data area (in DPRAM)
230 */
231#define CFG_INIT_RAM_ADDR 0x80000000
232#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
233#define CFG_INIT_RAM_CTRL 0x221
234#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
235#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 16)
236#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
237
238/*-----------------------------------------------------------------------
239 * Start addresses for the final memory configuration
240 * (Set up by the startup code)
241 * Please note that CFG_SDRAM_BASE _must_ start at 0
242 */
243#define CFG_SDRAM_BASE 0x40000000
244#define CFG_SDRAM_BASE1 0x48000000
245#define CFG_SDRAM_SIZE 256 /* SDRAM size in MB */
246#define CFG_SDRAM_CFG1 0x65311610
247#define CFG_SDRAM_CFG2 0x59670000
248#define CFG_SDRAM_CTRL 0xEA0B2000
249#define CFG_SDRAM_EMOD 0x40010000
250#define CFG_SDRAM_MODE 0x00010033
251
252#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
253#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
254
255#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
256#define CFG_BOOTPARAMS_LEN 64*1024
257#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
258#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
259
260/*
261 * For booting Linux, the board info and command line data
262 * have to be in the first 8 MB of memory, since this is
263 * the maximum mapped by the Linux kernel during initialization ??
264 */
265/* Initial Memory map for Linux */
266#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
267
268/* Configuration for environment
269 * Environment is embedded in u-boot in the second sector of the flash
270 */
271#define CFG_ENV_OFFSET 0x4000
272#define CFG_ENV_SECT_SIZE 0x2000
273#define CFG_ENV_IS_IN_FLASH 1
274#define CONFIG_ENV_OVERWRITE 1
275#undef CFG_ENV_IS_EMBEDDED
276
277/*-----------------------------------------------------------------------
278 * FLASH organization
279 */
280#ifdef CFG_ATMEL_BOOT
281# define CFG_FLASH_BASE 0
282# define CFG_FLASH0_BASE CFG_CS0_BASE
283# define CFG_FLASH1_BASE CFG_CS1_BASE
284#else
285# define CFG_FLASH_BASE CFG_FLASH0_BASE
286# define CFG_FLASH0_BASE CFG_CS1_BASE
287# define CFG_FLASH1_BASE CFG_CS0_BASE
288#endif
289
290/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system
291/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system
292 keep reset. */
293#undef CFG_FLASH_CFI
294#ifdef CFG_FLASH_CFI
295
296# define CFG_FLASH_CFI_DRIVER 1
297# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */
298# define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
299# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
300# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
301# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
302# define CFG_FLASH_CHECKSUM
303# define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE, CFG_CS1_BASE }
304
305#else
306
307# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
308
309# define CFG_ATMEL_REGION 4
310# define CFG_ATMEL_TOTALSECT 11
311# define CFG_ATMEL_SECT {1, 2, 1, 7}
312# define CFG_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
313# define CFG_INTEL_SECT 137
314
315/* max number of sectors on one chip */
316# define CFG_MAX_FLASH_SECT (CFG_ATMEL_TOTALSECT + CFG_INTEL_SECT)
317# define CFG_FLASH_ERASE_TOUT 2000 /* Atmel needs longer timeout */
318# define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
319# define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
320# define CFG_FLASH_UNLOCK_TOUT 100 /* Timeout for Flash Clear Lock Bits (in ms) */
321# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
322# define CFG_FLASH_CHECKSUM
323
324#endif
325
326/*
327 * This is setting for JFFS2 support in u-boot.
328 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
329 */
330#ifdef CFG_ATMEL_BOOT
331# define CONFIG_JFFS2_DEV "nor0"
332# define CONFIG_JFFS2_PART_SIZE 0x01000000
333# define CONFIG_JFFS2_PART_OFFSET CFG_FLASH1_BASE
334#else
335# define CONFIG_JFFS2_DEV "nor0"
336# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000)
337# define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000)
338#endif
339
340/*-----------------------------------------------------------------------
341 * Cache Configuration
342 */
343#define CFG_CACHELINE_SIZE 16
344
345/*-----------------------------------------------------------------------
346 * Memory bank definitions
347 */
348/*
349 * CS0 - NOR Flash 1, 2, 4, or 8MB
350 * CS1 - CompactFlash and registers
351 * CS2 - CPLD
352 * CS3 - FPGA
353 * CS4 - Available
354 * CS5 - Available
355 */
356
357#ifdef CFG_ATMEL_BOOT
358 /* Atmel Flash */
359#define CFG_CS0_BASE 0
360#define CFG_CS0_MASK 0x00070001
361#define CFG_CS0_CTRL 0x00001140
362/* Intel Flash */
363#define CFG_CS1_BASE 0x04000000
364#define CFG_CS1_MASK 0x01FF0001
365#define CFG_CS1_CTRL 0x003F3D60
366
367#define CFG_ATMEL_BASE CFG_CS0_BASE
368#else
369/* Intel Flash */
370#define CFG_CS0_BASE 0
371#define CFG_CS0_MASK 0x01FF0001
372#define CFG_CS0_CTRL 0x003F3D60
373 /* Atmel Flash */
374#define CFG_CS1_BASE 0x04000000
375#define CFG_CS1_MASK 0x00070001
376#define CFG_CS1_CTRL 0x00001140
377
378#define CFG_ATMEL_BASE CFG_CS1_BASE
379#endif
380
381/* CPLD */
382#define CFG_CS2_BASE 0x08000000
383#define CFG_CS2_MASK 0x00070001
384#define CFG_CS2_CTRL 0x003f1140
385
386/* FPGA */
387#define CFG_CS3_BASE 0x09000000
388#define CFG_CS3_MASK 0x00070001
389#define CFG_CS3_CTRL 0x00000020
390
391#endif /* _JAMICA54455_H */