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wdenke2211742002-11-02 23:30:20 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2001-2005
wdenke2211742002-11-02 23:30:20 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
wdenk56f94be2002-11-05 16:35:14 +000031/* External logbuffer support */
32#define CONFIG_LOGBUFFER
33
wdenke2211742002-11-02 23:30:20 +000034/*
35 * High Level Configuration Options
36 * (easy to change)
37 */
38
39#define CONFIG_MPC823 1 /* This is a MPC823E CPU */
40#define CONFIG_LWMON 1 /* ...on a LWMON board */
41
wdenke3c9b9f2004-10-24 23:54:40 +000042/* Default Ethernet MAC address */
43#define CONFIG_ETHADDR 00:11:B0:00:00:00
44
45/* The default Ethernet MAC address can be overwritten just once */
46#ifdef CONFIG_ETHADDR
47#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
48#endif
49
wdenkc837dcb2004-01-20 23:12:12 +000050#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
wdenk4532cb62003-04-27 22:52:51 +000051#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */
wdenke2211742002-11-02 23:30:20 +000052
53#define CONFIG_LCD 1 /* use LCD controller ... */
54#define CONFIG_HLD1045 1 /* ... with a HLD1045 display */
55
wdenk88804d12005-07-04 00:03:16 +000056#define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */
57#define CONFIG_LCD_INFO 1 /* ... and some board info */
wdenk4532cb62003-04-27 22:52:51 +000058#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
59
wdenk281e00a2004-08-01 22:48:16 +000060#define CONFIG_SERIAL_MULTI 1
wdenke2211742002-11-02 23:30:20 +000061#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
wdenk281e00a2004-08-01 22:48:16 +000062#define CONFIG_8xx_CONS_SCC2 1 /* Console is on SCC2 */
wdenke2211742002-11-02 23:30:20 +000063
64#define CONFIG_BAUDRATE 115200 /* with watchdog >= 38400 needed */
65
66#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
67
68#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
69
70/* pre-boot commands */
71#define CONFIG_PREBOOT "setenv bootdelay 15"
72
73#undef CONFIG_BOOTARGS
74
75/* POST support */
wdenkea909b72002-11-21 23:11:29 +000076#define CONFIG_POST (CFG_POST_CACHE | \
wdenke2211742002-11-02 23:30:20 +000077 CFG_POST_WATCHDOG | \
wdenkea909b72002-11-21 23:11:29 +000078 CFG_POST_RTC | \
79 CFG_POST_MEMORY | \
80 CFG_POST_CPU | \
81 CFG_POST_UART | \
82 CFG_POST_ETHER | \
83 CFG_POST_I2C | \
84 CFG_POST_SPI | \
85 CFG_POST_USB | \
wdenk4532cb62003-04-27 22:52:51 +000086 CFG_POST_SPR | \
87 CFG_POST_SYSMON)
wdenke2211742002-11-02 23:30:20 +000088
wdenk31a64922004-08-28 21:09:14 +000089/*
90 * Keyboard commands:
91 * # = 0x28 = ENTER : enable bootmessages on LCD
92 * 2 = 0x3A+0x3C = F1 + F3 : enable update mode
93 * 3 = 0x3C+0x3F = F3 + F6 : enable test mode
94 */
wdenke3c9b9f2004-10-24 23:54:40 +000095
96#define CONFIG_BOOTCOMMAND "autoscr 40040000;saveenv"
97
98/* "gatewayip=10.8.211.250\0" \ */
wdenkd126bfb2003-04-10 11:18:18 +000099#define CONFIG_EXTRA_ENV_SETTINGS \
100 "kernel_addr=40080000\0" \
101 "ramdisk_addr=40280000\0" \
wdenke3c9b9f2004-10-24 23:54:40 +0000102 "netmask=255.255.192.0\0" \
103 "serverip=10.8.2.101\0" \
104 "ipaddr=10.8.57.0\0" \
wdenk31a64922004-08-28 21:09:14 +0000105 "magic_keys=#23\0" \
wdenkd126bfb2003-04-10 11:18:18 +0000106 "key_magic#=28\0" \
107 "key_cmd#=setenv addfb setenv 'bootargs $bootargs console=tty0'\0" \
wdenk31a64922004-08-28 21:09:14 +0000108 "key_magic2=3A+3C\0" \
109 "key_cmd2=echo *** Entering Update Mode ***;" \
110 "if fatload ide 0:3 10000 update.scr;" \
111 "then autoscr 10000;" \
112 "else echo *** UPDATE FAILED ***;" \
113 "fi\0" \
wdenkd126bfb2003-04-10 11:18:18 +0000114 "key_magic3=3C+3F\0" \
115 "key_cmd3=echo *** Entering Test Mode ***;" \
116 "setenv add_misc 'setenv bootargs $bootargs testmode'\0" \
117 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \
118 "ramargs=setenv bootargs root=/dev/ram rw\0" \
119 "addfb=setenv bootargs $bootargs console=ttyS1,$baudrate\0" \
120 "addip=setenv bootargs $bootargs " \
121 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
122 "panic=1\0" \
123 "add_wdt=setenv bootargs $bootargs $wdt_args\0" \
124 "add_misc=setenv bootargs $bootargs runmode\0" \
125 "flash_nfs=run nfsargs addip add_wdt addfb add_misc;" \
126 "bootm $kernel_addr\0" \
127 "flash_self=run ramargs addip add_wdt addfb add_misc;" \
128 "bootm $kernel_addr $ramdisk_addr\0" \
129 "net_nfs=tftp 100000 /tftpboot/uImage.lwmon;" \
130 "run nfsargs addip add_wdt addfb;bootm\0" \
131 "rootpath=/opt/eldk/ppc_8xx\0" \
132 "load=tftp 100000 /tftpboot/u-boot.bin\0" \
133 "update=protect off 1:0;era 1:0;cp.b 100000 40000000 $filesize\0" \
134 "wdt_args=wdt_8xx=off\0" \
wdenke2211742002-11-02 23:30:20 +0000135 "verify=no"
136
137#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
138#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
139
140#define CONFIG_WATCHDOG 1 /* watchdog enabled */
wdenka8c7c702003-12-06 19:49:23 +0000141#define CFG_WATCHDOG_FREQ (CFG_HZ / 20)
wdenke2211742002-11-02 23:30:20 +0000142
143#undef CONFIG_STATUS_LED /* Status LED disabled */
144
145/* enable I2C and select the hardware/software driver */
wdenkea909b72002-11-21 23:11:29 +0000146#undef CONFIG_HARD_I2C /* I2C with hardware support */
147#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
wdenke2211742002-11-02 23:30:20 +0000148
wdenkea909b72002-11-21 23:11:29 +0000149#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
150#define CFG_I2C_SLAVE 0xFE
wdenke2211742002-11-02 23:30:20 +0000151
152#ifdef CONFIG_SOFT_I2C
153/*
154 * Software (bit-bang) I2C driver configuration
155 */
156#define PB_SCL 0x00000020 /* PB 26 */
157#define PB_SDA 0x00000010 /* PB 27 */
158
159#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
160#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
161#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
162#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
163#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
164 else immr->im_cpm.cp_pbdat &= ~PB_SDA
165#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
166 else immr->im_cpm.cp_pbdat &= ~PB_SCL
wdenk4532cb62003-04-27 22:52:51 +0000167#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
wdenke2211742002-11-02 23:30:20 +0000168#endif /* CONFIG_SOFT_I2C */
169
170
171#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
172
Jon Loeliger9bbb1c02007-07-04 22:32:57 -0500173
174/*
175 * Command line configuration.
176 */
177#include <config_cmd_default.h>
178
179#define CONFIG_CMD_ASKENV
180#define CONFIG_CMD_BMP
181#define CONFIG_CMD_BSP
182#define CONFIG_CMD_DATE
183#define CONFIG_CMD_DHCP
184#define CONFIG_CMD_EEPROM
185#define CONFIG_CMD_FAT
186#define CONFIG_CMD_I2C
187#define CONFIG_CMD_IDE
188#define CONFIG_CMD_NFS
Jon Loeliger9bbb1c02007-07-04 22:32:57 -0500189#define CONFIG_CMD_SNTP
190
Jon Loeligeraf075ee2007-07-08 17:02:01 -0500191#ifdef CONFIG_POST
192#define CONFIG_CMD_DIAG
193#endif
194
Jon Loeliger9bbb1c02007-07-04 22:32:57 -0500195
wdenke2211742002-11-02 23:30:20 +0000196#define CONFIG_MAC_PARTITION
197#define CONFIG_DOS_PARTITION
198
Jon Loeliger2fd90ce2007-07-09 21:48:26 -0500199/*
200 * BOOTP options
201 */
202#define CONFIG_BOOTP_SUBNETMASK
203#define CONFIG_BOOTP_GATEWAY
204#define CONFIG_BOOTP_HOSTNAME
205#define CONFIG_BOOTP_BOOTPATH
206#define CONFIG_BOOTP_BOOTFILESIZE
wdenke2211742002-11-02 23:30:20 +0000207
wdenke2211742002-11-02 23:30:20 +0000208
209/*
210 * Miscellaneous configurable options
211 */
212#define CFG_LONGHELP /* undef to save memory */
213#define CFG_PROMPT "=> " /* Monitor Command Prompt */
214
wdenkd126bfb2003-04-10 11:18:18 +0000215#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
wdenke2211742002-11-02 23:30:20 +0000216#ifdef CFG_HUSH_PARSER
217#define CFG_PROMPT_HUSH_PS2 "> "
wdenkf12e5682003-07-07 20:07:54 +0000218#endif
wdenke2211742002-11-02 23:30:20 +0000219
Jon Loeliger9bbb1c02007-07-04 22:32:57 -0500220#if defined(CONFIG_CMD_KGDB)
wdenke2211742002-11-02 23:30:20 +0000221#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
222#else
223#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
224#endif
225#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
226#define CFG_MAXARGS 16 /* max number of command args */
227#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
228
229#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
230#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
231
232#define CFG_LOAD_ADDR 0x00100000 /* default load address */
233
234#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
235
236#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
237
wdenkd0fb80c2003-01-11 09:48:40 +0000238/*
239 * When the watchdog is enabled, output must be fast enough in Linux.
240 */
241#ifdef CONFIG_WATCHDOG
242#define CFG_BAUDRATE_TABLE { 38400, 57600, 115200 }
243#else
244#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
245#endif
wdenke2211742002-11-02 23:30:20 +0000246
wdenk2e5983d2003-07-15 20:04:06 +0000247/*----------------------------------------------------------------------*/
248#define CONFIG_MODEM_SUPPORT 1 /* enable modem initialization stuff */
249#undef CONFIG_MODEM_SUPPORT_DEBUG
250
wdenkad129652003-07-15 22:00:22 +0000251#define CONFIG_MODEM_KEY_MAGIC "3C+3D" /* press F3 + F4 keys to enable modem */
wdenk2e5983d2003-07-15 20:04:06 +0000252#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
253#if 0
254#define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */
255#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n"
256#define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */
257#endif
258/*----------------------------------------------------------------------*/
259
wdenke2211742002-11-02 23:30:20 +0000260/*
261 * Low Level Configuration Settings
262 * (address mappings, register initial values, etc.)
263 * You should know what you are doing if you make changes here.
264 */
265/*-----------------------------------------------------------------------
266 * Internal Memory Mapped Register
267 */
268#define CFG_IMMR 0xFFF00000
269
270/*-----------------------------------------------------------------------
271 * Definitions for initial stack pointer and data area (in DPRAM)
272 */
273#define CFG_INIT_RAM_ADDR CFG_IMMR
274#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
wdenk4532cb62003-04-27 22:52:51 +0000275#define CFG_GBL_DATA_SIZE 68 /* size in bytes reserved for initial data */
wdenke2211742002-11-02 23:30:20 +0000276#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
277#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
278
279/*-----------------------------------------------------------------------
280 * Start addresses for the final memory configuration
281 * (Set up by the startup code)
282 * Please note that CFG_SDRAM_BASE _must_ start at 0
283 */
284#define CFG_SDRAM_BASE 0x00000000
285#define CFG_FLASH_BASE 0x40000000
Wolfgang Denke4dbe1b2007-07-05 17:56:27 +0200286#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
wdenke2211742002-11-02 23:30:20 +0000287#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
288#else
289#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
290#endif
291#define CFG_MONITOR_BASE CFG_FLASH_BASE
292#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
293
294/*
295 * For booting Linux, the board info and command line data
296 * have to be in the first 8 MB of memory, since this is
297 * the maximum mapped by the Linux kernel during initialization.
298 */
299#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
300/*-----------------------------------------------------------------------
301 * FLASH organization
302 */
303#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
304#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
305
306#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
307#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */
wdenkc837dcb2004-01-20 23:12:12 +0000308#define CFG_FLASH_USE_BUFFER_WRITE
309#define CFG_FLASH_BUFFER_WRITE_TOUT 2048 /* Timeout for Flash Buffer Write (in ms) */
wdenka2d18bb2004-02-11 21:35:18 +0000310/* Buffer size.
311 We have two flash devices connected in parallel.
312 Each device incorporates a Write Buffer of 32 bytes.
313 */
314#define CFG_FLASH_BUFFER_SIZE (2*32)
wdenke2211742002-11-02 23:30:20 +0000315
wdenk31a64922004-08-28 21:09:14 +0000316/* Put environment in flash which is much faster to boot than using the EEPROM */
wdenke2211742002-11-02 23:30:20 +0000317#define CFG_ENV_IS_IN_FLASH 1
318#define CFG_ENV_ADDR 0x40040000 /* Address of Environment Sector */
319#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment */
320#define CFG_ENV_SECT_SIZE 0x40000 /* we have BIG sectors only :-( */
wdenk31a64922004-08-28 21:09:14 +0000321
wdenke2211742002-11-02 23:30:20 +0000322/*-----------------------------------------------------------------------
323 * I2C/EEPROM Configuration
324 */
325
326#define CFG_I2C_AUDIO_ADDR 0x28 /* Audio volume control */
327#define CFG_I2C_SYSMON_ADDR 0x2E /* LM87 System Monitor */
328#define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
329#define CFG_I2C_POWER_A_ADDR 0x52 /* PCMCIA/USB power switch, channel A */
330#define CFG_I2C_POWER_B_ADDR 0x53 /* PCMCIA/USB power switch, channel B */
331#define CFG_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
332#define CFG_I2C_PICIO_ADDR 0x57 /* PIC IO Expander */
333
wdenk288b3d72002-12-20 23:42:25 +0000334#undef CONFIG_USE_FRAM /* Use FRAM instead of EEPROM */
335
wdenke2211742002-11-02 23:30:20 +0000336#ifdef CONFIG_USE_FRAM /* use FRAM */
337#define CFG_I2C_EEPROM_ADDR 0x55 /* FRAM FM24CL64 */
338#define CFG_I2C_EEPROM_ADDR_LEN 2
339#else /* use EEPROM */
340#define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */
341#define CFG_I2C_EEPROM_ADDR_LEN 1
342#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
343#endif /* CONFIG_USE_FRAM */
344#define CFG_EEPROM_PAGE_WRITE_BITS 4
345
wdenk6aff3112002-12-17 01:51:00 +0000346/* List of I2C addresses to be verified by POST */
wdenk288b3d72002-12-20 23:42:25 +0000347#ifdef CONFIG_USE_FRAM
wdenk6aff3112002-12-17 01:51:00 +0000348#define I2C_ADDR_LIST { /* CFG_I2C_AUDIO_ADDR, */ \
349 CFG_I2C_SYSMON_ADDR, \
350 CFG_I2C_RTC_ADDR, \
351 CFG_I2C_POWER_A_ADDR, \
352 CFG_I2C_POWER_B_ADDR, \
353 CFG_I2C_KEYBD_ADDR, \
354 CFG_I2C_PICIO_ADDR, \
355 CFG_I2C_EEPROM_ADDR, \
356 }
wdenk288b3d72002-12-20 23:42:25 +0000357#else /* Use EEPROM - which show up on 8 consequtive addresses */
358#define I2C_ADDR_LIST { /* CFG_I2C_AUDIO_ADDR, */ \
359 CFG_I2C_SYSMON_ADDR, \
360 CFG_I2C_RTC_ADDR, \
361 CFG_I2C_POWER_A_ADDR, \
362 CFG_I2C_POWER_B_ADDR, \
363 CFG_I2C_KEYBD_ADDR, \
364 CFG_I2C_PICIO_ADDR, \
365 CFG_I2C_EEPROM_ADDR+0, \
366 CFG_I2C_EEPROM_ADDR+1, \
367 CFG_I2C_EEPROM_ADDR+2, \
368 CFG_I2C_EEPROM_ADDR+3, \
369 CFG_I2C_EEPROM_ADDR+4, \
370 CFG_I2C_EEPROM_ADDR+5, \
371 CFG_I2C_EEPROM_ADDR+6, \
372 CFG_I2C_EEPROM_ADDR+7, \
373 }
374#endif /* CONFIG_USE_FRAM */
wdenk6aff3112002-12-17 01:51:00 +0000375
wdenke2211742002-11-02 23:30:20 +0000376/*-----------------------------------------------------------------------
377 * Cache Configuration
378 */
379#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger9bbb1c02007-07-04 22:32:57 -0500380#if defined(CONFIG_CMD_KGDB)
wdenke2211742002-11-02 23:30:20 +0000381#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
382#endif
383
384/*-----------------------------------------------------------------------
385 * SYPCR - System Protection Control 11-9
386 * SYPCR can only be written once after reset!
387 *-----------------------------------------------------------------------
388 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
389 */
390#if 0 && defined(CONFIG_WATCHDOG) /* LWMON uses external MAX706TESA WD */
391#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
392 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
393#else
394#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
395#endif
396
397/*-----------------------------------------------------------------------
398 * SIUMCR - SIU Module Configuration 11-6
399 *-----------------------------------------------------------------------
400 * PCMCIA config., multi-function pin tri-state
401 */
402/* EARB, DBGC and DBPC are initialised by the HCW */
403/* => 0x000000C0 */
404#define CFG_SIUMCR (SIUMCR_GB5E)
405/*#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) */
406
407/*-----------------------------------------------------------------------
408 * TBSCR - Time Base Status and Control 11-26
409 *-----------------------------------------------------------------------
410 * Clear Reference Interrupt Status, Timebase freezing enabled
411 */
412#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
413
414/*-----------------------------------------------------------------------
415 * PISCR - Periodic Interrupt Status and Control 11-31
416 *-----------------------------------------------------------------------
417 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
418 */
419#define CFG_PISCR (PISCR_PS | PISCR_PITF)
420
421/*-----------------------------------------------------------------------
422 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
423 *-----------------------------------------------------------------------
424 * Reset PLL lock status sticky bit, timer expired status bit and timer
425 * interrupt status bit, set PLL multiplication factor !
426 */
427/* 0x00405000 */
428#define CFG_PLPRCR_MF 4 /* (4+1) * 13.2 = 66 MHz Clock */
429#define CFG_PLPRCR \
430 ( (CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) | \
431 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
432 /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
433 PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \
434 )
435
436#define CONFIG_8xx_GCLK_FREQ ((CFG_PLPRCR_MF+1)*13200000)
437
438/*-----------------------------------------------------------------------
439 * SCCR - System Clock and reset Control Register 15-27
440 *-----------------------------------------------------------------------
441 * Set clock output, timebase and RTC source and divider,
442 * power management and some other internal clocks
443 */
444#define SCCR_MASK SCCR_EBDF11
445/* 0x01800000 */
446#define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \
447 SCCR_RTDIV | SCCR_RTSEL | \
448 /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
449 SCCR_EBDF00 | SCCR_DFSYNC00 | \
450 SCCR_DFBRG00 | SCCR_DFNL000 | \
451 SCCR_DFNH000 | SCCR_DFLCD100 | \
452 SCCR_DFALCD01)
453
454/*-----------------------------------------------------------------------
455 * RTCSC - Real-Time Clock Status and Control Register 11-27
456 *-----------------------------------------------------------------------
457 */
458/* 0x00C3 => 0x0003 */
459#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
460
461
462/*-----------------------------------------------------------------------
463 * RCCR - RISC Controller Configuration Register 19-4
464 *-----------------------------------------------------------------------
465 */
466#define CFG_RCCR 0x0000
467
468/*-----------------------------------------------------------------------
469 * RMDS - RISC Microcode Development Support Control Register
470 *-----------------------------------------------------------------------
471 */
472#define CFG_RMDS 0
473
474/*-----------------------------------------------------------------------
475 *
476 * Interrupt Levels
477 *-----------------------------------------------------------------------
478 */
479#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
480
481/*-----------------------------------------------------------------------
482 * PCMCIA stuff
483 *-----------------------------------------------------------------------
484 *
485 */
486#define CFG_PCMCIA_MEM_ADDR (0x50000000)
487#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
488#define CFG_PCMCIA_DMA_ADDR (0x54000000)
489#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
490#define CFG_PCMCIA_ATTRB_ADDR (0x58000000)
491#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
492#define CFG_PCMCIA_IO_ADDR (0x5C000000)
493#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
494
495/*-----------------------------------------------------------------------
496 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
497 *-----------------------------------------------------------------------
498 */
499
500#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
501
502#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
503#undef CONFIG_IDE_LED /* LED for ide not supported */
504#undef CONFIG_IDE_RESET /* reset for ide not supported */
505
506#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
507#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
508
509#define CFG_ATA_IDE0_OFFSET 0x0000
510
511#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
512
513/* Offset for data I/O */
514#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
515
516/* Offset for normal register accesses */
517#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
518
519/* Offset for alternate registers */
520#define CFG_ATA_ALT_OFFSET 0x0100
521
wdenk31a64922004-08-28 21:09:14 +0000522#define CONFIG_SUPPORT_VFAT /* enable VFAT support */
523
wdenke2211742002-11-02 23:30:20 +0000524/*-----------------------------------------------------------------------
525 *
526 *-----------------------------------------------------------------------
527 *
528 */
wdenke2211742002-11-02 23:30:20 +0000529#define CFG_DER 0
530
531/*
532 * Init Memory Controller:
533 *
534 * BR0/1 and OR0/1 (FLASH) - second Flash bank optional
535 */
536
537#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
538#define FLASH_BASE1_PRELIM 0x41000000 /* FLASH bank #1 */
539
540/* used to re-map FLASH:
541 * restrict access enough to keep SRAM working (if any)
542 * but not too much to meddle with FLASH accesses
543 */
544#define CFG_REMAP_OR_AM 0xFF000000 /* OR addr mask */
545#define CFG_PRELIM_OR_AM 0xFF000000 /* OR addr mask */
546
547/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */
548#define CFG_OR_TIMING_FLASH (OR_SCY_8_CLK)
549
550#define CFG_OR0_REMAP ( CFG_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
551 CFG_OR_TIMING_FLASH)
552#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
553 CFG_OR_TIMING_FLASH)
554/* 16 bit, bank valid */
555#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
556
557#define CFG_OR1_REMAP CFG_OR0_REMAP
558#define CFG_OR1_PRELIM CFG_OR0_PRELIM
559#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
560
561/*
562 * BR3/OR3: SDRAM
563 *
564 * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
565 */
566#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
567#define SDRAM_PRELIM_OR_AM 0xF0000000 /* map 256 MB (>SDRAM_MAX_SIZE!) */
568#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */
569
570#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB SDRAM */
571
572#define CFG_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
573#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
574
575/*
576 * BR5/OR5: Touch Panel
577 *
578 * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
579 */
580#define TOUCHPNL_BASE 0x20000000
581#define TOUCHPNL_OR_AM 0xFFFF8000
582#define TOUCHPNL_TIMING OR_SCY_0_CLK
583
584#define CFG_OR5_PRELIM (TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
585 TOUCHPNL_TIMING )
586#define CFG_BR5_PRELIM ((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
587
588#define CFG_MEMORY_75
589#undef CFG_MEMORY_7E
590#undef CFG_MEMORY_8E
591
592/*
593 * Memory Periodic Timer Prescaler
594 */
595
596/* periodic timer for refresh */
597#define CFG_MPTPR 0x200
598
599/*
600 * MAMR settings for SDRAM
601 */
602
603#define CFG_MAMR_8COL 0x80802114
604#define CFG_MAMR_9COL 0x80904114
605
606/*
607 * MAR setting for SDRAM
608 */
609#define CFG_MAR 0x00000088
610
611/*
612 * Internal Definitions
613 *
614 * Boot Flags
615 */
616#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
617#define BOOTFLAG_WARM 0x02 /* Software reboot */
618
wdenke2211742002-11-02 23:30:20 +0000619#endif /* __CONFIG_H */