blob: c7200ee71aeb2e0e622c5993bf5185f52658250a [file] [log] [blame]
Marek Vasut71a758e12011-11-08 23:18:09 +00001/*
2 * Freescale i.MX28 SSP MMC driver
3 *
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
6 *
7 * Based on code from LTIB:
8 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
9 * Terry Lv
10 *
11 * Copyright 2007, Freescale Semiconductor, Inc
12 * Andy Fleming
13 *
14 * Based vaguely on the pxa mmc code:
15 * (C) Copyright 2003
16 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
17 *
18 * See file CREDITS for list of people who contributed to this
19 * project.
20 *
21 * This program is free software; you can redistribute it and/or
22 * modify it under the terms of the GNU General Public License as
23 * published by the Free Software Foundation; either version 2 of
24 * the License, or (at your option) any later version.
25 *
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
30 *
31 * You should have received a copy of the GNU General Public License
32 * along with this program; if not, write to the Free Software
33 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 * MA 02111-1307 USA
35 */
36#include <common.h>
37#include <malloc.h>
38#include <mmc.h>
39#include <asm/errno.h>
40#include <asm/io.h>
41#include <asm/arch/clock.h>
42#include <asm/arch/imx-regs.h>
43#include <asm/arch/sys_proto.h>
Marek Vasut3687c412012-03-15 18:33:21 +000044#include <asm/arch/dma.h>
Marek Vasut71a758e12011-11-08 23:18:09 +000045
Marek Vasut4cc76c62012-04-05 03:30:35 +000046/*
47 * CONFIG_MXS_MMC_DMA: This feature is highly experimental and has no
48 * performance benefit unless you operate the platform with
49 * data cache enabled. This is disabled by default, enable
50 * only if you know what you're doing.
51 */
52
Marek Vasut71a758e12011-11-08 23:18:09 +000053struct mxsmmc_priv {
54 int id;
55 struct mx28_ssp_regs *regs;
56 uint32_t clkseq_bypass;
57 uint32_t *clkctrl_ssp;
58 uint32_t buswidth;
59 int (*mmc_is_wp)(int);
Marek Vasut3687c412012-03-15 18:33:21 +000060 struct mxs_dma_desc *desc;
Marek Vasut71a758e12011-11-08 23:18:09 +000061};
62
63#define MXSMMC_MAX_TIMEOUT 10000
64
65/*
66 * Sends a command out on the bus. Takes the mmc pointer,
67 * a command pointer, and an optional data pointer.
68 */
69static int
70mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
71{
72 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
73 struct mx28_ssp_regs *ssp_regs = priv->regs;
74 uint32_t reg;
75 int timeout;
Marek Vasut4cc76c62012-04-05 03:30:35 +000076 uint32_t data_count;
Marek Vasut71a758e12011-11-08 23:18:09 +000077 uint32_t ctrl0;
Marek Vasut4cc76c62012-04-05 03:30:35 +000078#ifndef CONFIG_MXS_MMC_DMA
79 uint32_t *data_ptr;
80#else
81 uint32_t cache_data_count;
82#endif
Marek Vasut71a758e12011-11-08 23:18:09 +000083
84 debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
85
86 /* Check bus busy */
87 timeout = MXSMMC_MAX_TIMEOUT;
88 while (--timeout) {
89 udelay(1000);
90 reg = readl(&ssp_regs->hw_ssp_status);
91 if (!(reg &
92 (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
93 SSP_STATUS_CMD_BUSY))) {
94 break;
95 }
96 }
97
98 if (!timeout) {
99 printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev);
100 return TIMEOUT;
101 }
102
103 /* See if card is present */
104 if (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT) {
105 printf("MMC%d: No card detected!\n", mmc->block_dev.dev);
106 return NO_CARD_ERR;
107 }
108
109 /* Start building CTRL0 contents */
110 ctrl0 = priv->buswidth;
111
112 /* Set up command */
113 if (!(cmd->resp_type & MMC_RSP_CRC))
114 ctrl0 |= SSP_CTRL0_IGNORE_CRC;
115 if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
116 ctrl0 |= SSP_CTRL0_GET_RESP;
117 if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
118 ctrl0 |= SSP_CTRL0_LONG_RESP;
119
120 /* Command index */
121 reg = readl(&ssp_regs->hw_ssp_cmd0);
122 reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
123 reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
124 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
125 reg |= SSP_CMD0_APPEND_8CYC;
126 writel(reg, &ssp_regs->hw_ssp_cmd0);
127
128 /* Command argument */
129 writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
130
131 /* Set up data */
132 if (data) {
133 /* READ or WRITE */
134 if (data->flags & MMC_DATA_READ) {
135 ctrl0 |= SSP_CTRL0_READ;
Marek Vasutc7527b72012-05-01 11:09:52 +0000136 } else if (priv->mmc_is_wp &&
137 priv->mmc_is_wp(mmc->block_dev.dev)) {
Marek Vasut71a758e12011-11-08 23:18:09 +0000138 printf("MMC%d: Can not write a locked card!\n",
139 mmc->block_dev.dev);
140 return UNUSABLE_ERR;
141 }
142
143 ctrl0 |= SSP_CTRL0_DATA_XFER;
144 reg = ((data->blocks - 1) <<
145 SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
146 ((ffs(data->blocksize) - 1) <<
147 SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
148 writel(reg, &ssp_regs->hw_ssp_block_size);
149
150 reg = data->blocksize * data->blocks;
151 writel(reg, &ssp_regs->hw_ssp_xfer_size);
152 }
153
154 /* Kick off the command */
155 ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
156 writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
157
158 /* Wait for the command to complete */
159 timeout = MXSMMC_MAX_TIMEOUT;
160 while (--timeout) {
161 udelay(1000);
162 reg = readl(&ssp_regs->hw_ssp_status);
163 if (!(reg & SSP_STATUS_CMD_BUSY))
164 break;
165 }
166
167 if (!timeout) {
168 printf("MMC%d: Command %d busy\n",
169 mmc->block_dev.dev, cmd->cmdidx);
170 return TIMEOUT;
171 }
172
173 /* Check command timeout */
174 if (reg & SSP_STATUS_RESP_TIMEOUT) {
175 printf("MMC%d: Command %d timeout (status 0x%08x)\n",
176 mmc->block_dev.dev, cmd->cmdidx, reg);
177 return TIMEOUT;
178 }
179
180 /* Check command errors */
181 if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
182 printf("MMC%d: Command %d error (status 0x%08x)!\n",
183 mmc->block_dev.dev, cmd->cmdidx, reg);
184 return COMM_ERR;
185 }
186
187 /* Copy response to response buffer */
188 if (cmd->resp_type & MMC_RSP_136) {
189 cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
190 cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
191 cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
192 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
193 } else
194 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
195
196 /* Return if no data to process */
197 if (!data)
198 return 0;
199
Marek Vasut71a758e12011-11-08 23:18:09 +0000200 data_count = data->blocksize * data->blocks;
Marek Vasut4cc76c62012-04-05 03:30:35 +0000201 timeout = MXSMMC_MAX_TIMEOUT;
Marek Vasut3687c412012-03-15 18:33:21 +0000202
Marek Vasut4cc76c62012-04-05 03:30:35 +0000203#ifdef CONFIG_MXS_MMC_DMA
Marek Vasut3687c412012-03-15 18:33:21 +0000204 if (data_count % ARCH_DMA_MINALIGN)
205 cache_data_count = roundup(data_count, ARCH_DMA_MINALIGN);
206 else
207 cache_data_count = data_count;
208
Marek Vasut71a758e12011-11-08 23:18:09 +0000209 if (data->flags & MMC_DATA_READ) {
Marek Vasut3687c412012-03-15 18:33:21 +0000210 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
211 priv->desc->cmd.address = (dma_addr_t)data->dest;
Marek Vasut71a758e12011-11-08 23:18:09 +0000212 } else {
Marek Vasut3687c412012-03-15 18:33:21 +0000213 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
214 priv->desc->cmd.address = (dma_addr_t)data->src;
215
216 /* Flush data to DRAM so DMA can pick them up */
217 flush_dcache_range((uint32_t)priv->desc->cmd.address,
218 (uint32_t)(priv->desc->cmd.address + cache_data_count));
Marek Vasut71a758e12011-11-08 23:18:09 +0000219 }
220
Marek Vasut3687c412012-03-15 18:33:21 +0000221 priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
222 (data_count << MXS_DMA_DESC_BYTES_OFFSET);
223
224
225 mxs_dma_desc_append(MXS_DMA_CHANNEL_AHB_APBH_SSP0, priv->desc);
226 if (mxs_dma_go(MXS_DMA_CHANNEL_AHB_APBH_SSP0)) {
227 printf("MMC%d: DMA transfer failed\n", mmc->block_dev.dev);
Marek Vasut71a758e12011-11-08 23:18:09 +0000228 return COMM_ERR;
229 }
230
Marek Vasut3687c412012-03-15 18:33:21 +0000231 /* The data arrived into DRAM, invalidate cache over them */
232 if (data->flags & MMC_DATA_READ) {
233 invalidate_dcache_range((uint32_t)priv->desc->cmd.address,
234 (uint32_t)(priv->desc->cmd.address + cache_data_count));
235 }
Marek Vasut4cc76c62012-04-05 03:30:35 +0000236#else
237 if (data->flags & MMC_DATA_READ) {
238 data_ptr = (uint32_t *)data->dest;
239 while (data_count && --timeout) {
240 reg = readl(&ssp_regs->hw_ssp_status);
241 if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
242 *data_ptr++ = readl(&ssp_regs->hw_ssp_data);
243 data_count -= 4;
244 timeout = MXSMMC_MAX_TIMEOUT;
245 } else
246 udelay(1000);
247 }
248 } else {
249 data_ptr = (uint32_t *)data->src;
250 timeout *= 100;
251 while (data_count && --timeout) {
252 reg = readl(&ssp_regs->hw_ssp_status);
253 if (!(reg & SSP_STATUS_FIFO_FULL)) {
254 writel(*data_ptr++, &ssp_regs->hw_ssp_data);
255 data_count -= 4;
256 timeout = MXSMMC_MAX_TIMEOUT;
257 } else
258 udelay(1000);
259 }
260 }
261
262 if (!timeout) {
263 printf("MMC%d: Data timeout with command %d (status 0x%08x)!\n",
264 mmc->block_dev.dev, cmd->cmdidx, reg);
265 return COMM_ERR;
266 }
267#endif
Marek Vasut3687c412012-03-15 18:33:21 +0000268
Marek Vasut71a758e12011-11-08 23:18:09 +0000269 /* Check data errors */
270 reg = readl(&ssp_regs->hw_ssp_status);
271 if (reg &
272 (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
273 SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
274 printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
275 mmc->block_dev.dev, cmd->cmdidx, reg);
276 return COMM_ERR;
277 }
278
279 return 0;
280}
281
282static void mxsmmc_set_ios(struct mmc *mmc)
283{
284 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
285 struct mx28_ssp_regs *ssp_regs = priv->regs;
286
287 /* Set the clock speed */
288 if (mmc->clock)
289 mx28_set_ssp_busclock(priv->id, mmc->clock / 1000);
290
291 switch (mmc->bus_width) {
292 case 1:
293 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
294 break;
295 case 4:
296 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
297 break;
298 case 8:
299 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
300 break;
301 }
302
303 /* Set the bus width */
304 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
305 SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
306
307 debug("MMC%d: Set %d bits bus width\n",
308 mmc->block_dev.dev, mmc->bus_width);
309}
310
311static int mxsmmc_init(struct mmc *mmc)
312{
313 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
314 struct mx28_ssp_regs *ssp_regs = priv->regs;
315
316 /* Reset SSP */
317 mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
318
319 /* 8 bits word length in MMC mode */
320 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1,
321 SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK,
Marek Vasut3687c412012-03-15 18:33:21 +0000322 SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
323 SSP_CTRL1_DMA_ENABLE);
Marek Vasut71a758e12011-11-08 23:18:09 +0000324
325 /* Set initial bit clock 400 KHz */
326 mx28_set_ssp_busclock(priv->id, 400);
327
328 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
329 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
330 udelay(200);
331 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
332
333 return 0;
334}
335
336int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int))
337{
338 struct mx28_clkctrl_regs *clkctrl_regs =
339 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
340 struct mmc *mmc = NULL;
341 struct mxsmmc_priv *priv = NULL;
Marek Vasut96666a32012-04-08 17:34:46 +0000342 int ret;
Marek Vasut71a758e12011-11-08 23:18:09 +0000343
344 mmc = malloc(sizeof(struct mmc));
345 if (!mmc)
346 return -ENOMEM;
347
348 priv = malloc(sizeof(struct mxsmmc_priv));
349 if (!priv) {
350 free(mmc);
351 return -ENOMEM;
352 }
353
Marek Vasut3687c412012-03-15 18:33:21 +0000354 priv->desc = mxs_dma_desc_alloc();
355 if (!priv->desc) {
356 free(priv);
357 free(mmc);
358 return -ENOMEM;
359 }
360
Marek Vasut96666a32012-04-08 17:34:46 +0000361 ret = mxs_dma_init_channel(id);
362 if (ret)
363 return ret;
364
Marek Vasut71a758e12011-11-08 23:18:09 +0000365 priv->mmc_is_wp = wp;
366 priv->id = id;
367 switch (id) {
368 case 0:
369 priv->regs = (struct mx28_ssp_regs *)MXS_SSP0_BASE;
370 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP0;
371 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp0;
372 break;
373 case 1:
374 priv->regs = (struct mx28_ssp_regs *)MXS_SSP1_BASE;
375 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP1;
376 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp1;
377 break;
378 case 2:
379 priv->regs = (struct mx28_ssp_regs *)MXS_SSP2_BASE;
380 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP2;
381 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp2;
382 break;
383 case 3:
384 priv->regs = (struct mx28_ssp_regs *)MXS_SSP3_BASE;
385 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP3;
386 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp3;
387 break;
388 }
389
390 sprintf(mmc->name, "MXS MMC");
391 mmc->send_cmd = mxsmmc_send_cmd;
392 mmc->set_ios = mxsmmc_set_ios;
393 mmc->init = mxsmmc_init;
Thierry Reding48972d92012-01-02 01:15:37 +0000394 mmc->getcd = NULL;
Marek Vasut71a758e12011-11-08 23:18:09 +0000395 mmc->priv = priv;
396
397 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
398
399 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
400 MMC_MODE_HS_52MHz | MMC_MODE_HS;
401
402 /*
403 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
404 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
405 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
406 * CLOCK_RATE could be any integer from 0 to 255.
407 */
408 mmc->f_min = 400000;
409 mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2;
Marek Vasut3687c412012-03-15 18:33:21 +0000410 mmc->b_max = 0x40;
Marek Vasut71a758e12011-11-08 23:18:09 +0000411
412 mmc_register(mmc);
413 return 0;
414}