| Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Rick Chen | 6020faf | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2017 Andes Technology Corporation |
| 4 | * Rick Chen, Andes Technology Corporation <rick@andestech.com> |
| Rick Chen | 6020faf | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _ASM_RISCV_CACHE_H |
| 8 | #define _ASM_RISCV_CACHE_H |
| 9 | |
| Rick Chen | 52923c6 | 2018-11-07 09:34:06 +0800 | [diff] [blame] | 10 | /* cache */ |
| Zong Li | 30fa33d | 2021-09-01 15:01:43 +0800 | [diff] [blame] | 11 | void cache_flush(void); |
| Rick Chen | 52923c6 | 2018-11-07 09:34:06 +0800 | [diff] [blame] | 12 | |
| Rick Chen | 6020faf | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 13 | /* |
| 14 | * The current upper bound for RISCV L1 data cache line sizes is 32 bytes. |
| 15 | * We use that value for aligning DMA buffers unless the board config has |
| 16 | * specified an alternate cache line size. |
| 17 | */ |
| 18 | #ifdef CONFIG_SYS_CACHELINE_SIZE |
| 19 | #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE |
| 20 | #else |
| 21 | #define ARCH_DMA_MINALIGN 32 |
| 22 | #endif |
| 23 | |
| 24 | #endif /* _ASM_RISCV_CACHE_H */ |